VNR VIGNANA JYOTHI INSTITUTE OF ENGINEERING AND TECHNOLOGY
[Link]. IV Semester
(22PC1CS203) COMPUTER ORGANIZATION
TEACHING SCHEME EVALUATION SCHEME
L T/P C SE CA ELA SEE TOTAL
3 0 3 30 5 5 60 100
COURSE OBJECTIVES:
• To understand the functional blocks of computer and instruction set architecture
• To describe micro programming and addressing modes of Central Processing Unit
• To perform arithmetic micro operations on integers and floating-point numbers
• To discuss the different ways of communicating with I/O devices
• To design techniques to enhance the performance using pipelining, parallelism
COURSE OUTCOMES: After completion of the course, the student should be able to
CO-1: Understand the basic components and the design of CPU, instruction set
CO-2: Understand the micro programming, instruction formats and addressing modes
CO-3: Implement arithmetic operations on integer and floating type values
CO-4: Analyze and understand the input organization and memory organization
CO-5: Explore pipeline processing, vector processing and array processing
COURSE ARTICULATION MATRIX:
(Correlation of Course Outcomes with Program Outcomes and Program Specific Outcomes using
mapping levels 1 = Slight, 2 = Moderate and 3 = Substantial)
PROGRAM SPECIFIC
PROGRAM OUTCOMES (PO)
CO OUTCOMES (PSO)
PO-1 PO-2 PO-3 PO-4 PO-5 PO-6 PO-7 PO-8 PO-9 PO-10 PO-11 PO-12 PSO-1 PSO-2 PSO-3
CO-1 2 3 - - - 2 - - - - - 2 1 2 3
CO-2 2 3 2 3 2 2 - - - - 2 3 1 3 3
CO-3 3 3 - 3 - - - - - - - 3 1 3 3
CO-4 2 3 - 2 3 2 2 - - - - 3 1 2 3
CO-5 2 3 - 2 3 2 2 - - - 3 3 1 3 3
UNIT-I:
Functional Blocks of a Computer: Introduction, Block Diagram, Definition of Computer
Organization, Computer Design and Computer Architecture
Instruction Set Architecture: Register Transfer language, Register Transfer, Arithmetic
Micro operations, logic micro-operations, shift micro-operations, Arithmetic logic shift
unit. Instruction codes, Computer Registers Computer instructions, Timing and Control,
Instruction cycle, Memory Reference Instructions, Register Reference and Input –
Output.
UNIT-II:
Central Processing Unit: General Register Organization, Instruction Formats,
Addressing modes, Data Transfer and Manipulation.
Microprogrammed Control: Control memory, Address sequencing, micro program
example, design of control unit.
UNIT-III:
Data Representation: Data types, Complements, Fixed Point Representation, Floating
Point Representation.
Computer Arithmetic: Addition and subtraction, multiplication Algorithms, Division
Algorithms, Restoring and Non-restoring, floating – point Arithmetic operations.
UNIT-IV:
Input-Output Organization: Input-Output Interface, Asynchronous data transfer,
Modes of Transfer, Program Controlled, Priority, Interrupt, Direct memory Access.
Privileged and Non-Privileged Instructions.
Memory Organization: Memory Hierarchy, Main Memory, Auxiliary memory, Associate
memory, Cache Memory, Mapping Techniques, Replacement Algorithms, Write
Policies, Memory interleaving.
UNIT-V:
Pipeline and Vector Processing: Parallel Processing, Pipelining, Arithmetic Pipeline,
Instruction Pipeline, RISC Pipeline, Vector Processing, Array Processor.
TEXT BOOKS:
1. Computer System Architecture, M. Morris Mano, 3rd Edition
2. Computer Organization and Embedded Systems, Carl Hamacher, 6th Edition,
McGraw-Hill
REFERENCES:
1. Computer Organization and Design: The Hardware/Software Interfaces, David A.
Patterson and John L. Hennessy, 5th Edition, Elsevier
2. Computer Architecture and Organization, John P. Hayes, 3rd Edition,
WCB/McGraw-Hill
3. Computer Organization and Architecture: Designing for Performance, William
Stallings, 10th Edition, Pearson Education
4. Computer System Design and Architecture, Vincent P. Heuring and Harry F.
Jordan, 2nd Edition, Pearson Education