Intrinsity FASTMATH
• The Intrinsity FastMATH is an embedded microprocessor that uses the MIPS architecture and a simple
cache implementation.
• This processor has a 12-stage pipeline.
• When operating at peak speed, the processor can request both an instruction word and a data word on
every clock.
• To satisfy the demands of the pipeline without stalling, separate instruction and data caches are used.
• Each cache is 16 KiB, or 4096 words, with 16-word blocks
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STEPS FOR A READ REQUEST
• 1. Send the address to the appropriate cache. The address comes either from the PC (for an instruction) or
from the ALU (for data).
• 2. If the cache signals hit, the requested word is available on the data lines. Since there are 16 words in the
desired block, we need to select the right one.
A block index field is used to control the multiplexor (shown at the bottom of the figure), which selects the
requested word from the 16 words in the indexed block.
• 3. If the cache signals miss, we send the address to the main memory. When the memory returns with the
data, we write it into the cache and then read it to fulfill the request.
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MEASURING AND IMPROVING CACHE PERFORMANCE
• CPU time can be divided into the clock cycles that the CPU spends executing the program and the clock
cycles that the CPU spends waiting for the memory system. Normally, we assume that the costs of cache
accesses that are hits are part of the normal CPU execution cycles.
• Memory-stall clock cycles can be defined as the sum of the stall cycles coming
from reads plus those coming from writes:
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READ-STALL CYCLES
• The read-stall cycles can be defined in terms of the number of read accesses per program, the miss penalty
in clock cycles for a read, and the read miss rate:
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WRITE-STALL CYCLES
• For a write-through scheme, we have two sources of stalls:
• write misses, which usually require that we fetch the block before continuing the write and write buffer
stalls, which occur when the write buffer is full when a write happens.
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WRITE BUFFER STALLS
• Fortunately, in systems with a reasonable write buffer depth (e.g., four or more words) and a memory
capable of accepting writes at a rate that significantly exceeds the average write frequency in programs
the write buffer stalls will be small, and we can safely ignore them. If a system did not meet these criteria,
it would not be well designed; instead, the designer should have used either a deeper write buffer or a
write-back organization.
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MEMORY-STALL CLOCK CYCLES
• In most write-through cache organizations, the read and write miss penalties
are the same.
• If we assume that the write buffer stalls are negligible, we can combine the reads and writes by using a
single miss rate and the miss penalty:
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AVERAGE MEMORY ACCESS TIME (AMAT)
• average time to access memory considering both hits and misses and the frequency of different
accesses
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DEFINING PERFORMANCE
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DEFINING PERFORMANCE
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AMDAHL’S LAW
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