Example 3. Implement a BCD-to-seven segment decoder with multiplexers. Solution.
A BCD-to-seven
segment decoder is already described by classical approach and realized with simple gates. The same
circuit can be realized with the help of multiplexers. The truth table of a BCD-to-seven segment decoder
(for common cathode type) is repeated here at Figure 5.90 for convenience. As there are four input
variables, 4-to-1 multiplexers are employed to develop the combinational logic circuit. Implementation
tables for each of the outputs a to g are shown in Figures 5.91(a)-(g). The logic diagram implementation
of a BCD-to-seven segment decoder with 4-to-1 multiplexers is shown in Figure 10. Note that don’t-
care (X) are judiciously considered as logic 1 or logic 0 in the implementation table.
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Demultiplexers Or Data Distributors
The term “demultiplex” means one into many. Demultiplexing is the process that receives
information from one channel and distributes the data over several channels. It is the reverse
operation of the multiplexer. A demultiplexer is the logic circuit that receives information
through a single input line and transmits the same information over one of the possible 2n
output lines. The selection of a specifi c output line is controlled by the bit combinations of the
selection lines.
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A 1-to-8 demultiplexer circuit is demonstrated in Figure 5.94. The selection input lines A, B,
and C activate an AND gate according to its bit combination. The input line I is common to
one of the inputs of all the AND gates. So, information of I passed to the output line is activated
by the particular AND gate. As an example, for the selection input combination 000, input I is
transmitted to Y0. A truth table is prepared in Figure 5.93 to illustrate the relation of selection
inputs and output lines. The demultiplexer is symbolized in Figure 5.95 where S2, S1, and S0
are the selection inputs. It may be noticed that demultiplexer circuits may be derived from a
decoder with the use of AND gates. As we have already seen, decoder outputs are equivalent
to the minterms, these minterms can be used as the selection of output lines, and when they are
ANDed with input line I, the data from input I is transmitted to output lines as activated
according to the enabled minterms. Figure 5.96 demonstrates the construction of a 1-to-4 with
a 2-to-4 decoder and four AND gates.
Like decoders and multiplexers, demultiplexers can also be cascaded to form higher order
demultiplexers. Figure 5.97 demonstrates how a 1-to-8 demultiplexer can be formed with two
1-to-4 demultiplexers. Here, the highest signifi cant bit A of the selection inputs is connected
to the ENABLE inputs, one directly and the other one is complemented. When A is logic 0,
one of the output lines D0 to D3 will be selected according to selection inputs B and C, and
when A is logic 1, one of the output lines D4 to D7 will be selected.
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Review Questions :
1- Design a combinational circuit for a BCD-to-gray code using (a) standard logic gates, (b) decoder,
(c) 8-to-1 multiplexer, and (d) 4-to-1 multiplexer.
2- Design a combinational circuit for a BCD-to-Excess-3 code using (a) standard logic gates, (b)
decoder, (c) 8-to-1 multiplexer, and (d) 4-to-1 multiplexer.
3- A certain multiplexer can switch one of 32 data inputs to output. How many different inputs does
this MUX have? Draw the circuit.
4- An 8-to-1 MUX has inputs A, B, and C connected to selection lines S2, S1, and S0 respectively. The
data inputs I0 to I7 are connected as I1 = I2 = I7 = 0, I3 = I5 = 1, I0 = I4 = D, and I6 = D'. Determine
the Boolean expression of the MUX output.
5- Implement the Boolean function F(A, B, C, D) = Σ ( 1, 3, 4, 11, 12, 13, 15) using (a) decoder and
external gates, and (b) 8-to-1 MUX and external gates.
6- Design an Excess-3-to-8421 code converter using (i) a 4-to-16 decoder with enable input E' and
associated gates, and (ii) 8-to-1 multiplexers.
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