5th sem BSc CS and BCA

Computer Organisaion Architecture

[Link] positive and negative logic.
a)When a circuit requires logic 1 to operate, it is known as positive logic.
.if a circuit requires a logic 0 to cause action, this type circuit is referred to as negative logic

[Link] gates.
Digital systems are said to be constructed by using logic gates. These gates are the AND,
OR, NOT, NAND, NOR, EXOR(XOR) and EXNOR(XNOR) gates
AND gate

The AND gate is an electronic circuit that gives a high output (1) only if all its
inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in
mind that this dot is sometimes omitted i.e. AB

OR gate

The OR gate is an electronic circuit that gives a high output (1) if one or
more of its inputs are high. A plus (+) is used to show the OR operation.

NOT gate

The NOT gate is an electronic circuit that produces an inverted version of the input at
its output. It is also known as an inverter. If the input variable is A, the inverted
output is known as NOT A. This is also shown as A', or A with a bar over the top, as
shown at the outputs. The diagrams below show two ways that the NAND logic gate
can be configured to produce a NOT gate. It can also be done using NOR logic gates
in the same way.
NAND gate

This is a NOT-AND gate which is equal to an AND gate followed by a NOT

gate. The outputs of all NAND gates are high if any of the inputs are low. The
symbol is an AND gate with a small circle on the output. The small circle
represents inversion.

NOR gate

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate.

The outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.

EXOR gate or XOR gate

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but
not both, of its two inputs are high. An encircled plus sign ( ) is used to show
the EOR operation.
EXNOR gate or XNOR gate

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low
output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with
a small circle on the output. The small circle represents inversion.
[Link] NAND and NOR are Called Universal gates?
a) The NAND and NOR gates are called universal gates since with either one the AND and
OR functions and NOT can be generated.

[Link] Half Adder

a)There are two inputs and two outputs in a Half Adder. Inputs are named as A and B, and
the outputs are named as Sum (S) and Carry (C). The Sum is X-OR of the input A and B.
Carry is AND of the input A and B. With the help of half adder, one can design a circuit that
is capable of performing simple addition with the help of logic gates.

The truth table of the half adder is

Inputs Outputs

A B Sum Carry

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
The Half Adder Circuit is shown below:

[Link] are the disadvantages of half adder?

a)Thedisadvantage of half adder is that it can only add two inputs and if there is any carry, it
is neglected. Thus, the process is incomplete.

6. Explain Full adder?

a)The full adder is a little more difficult to implement than a half adder. The main difference
between a half adder and a full adder is that the full-adder has three inputs and two outputs.
The two inputs are A and B, and the third input is a carry input CIN. The output carry is
designated as COUT, and the normal output is designated as S.

The Full adder circuit diagram is shown below:

The truth table of the Full Adder Circuit is shown below.

Inputs Outputs

A B CIN COUT S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

The schematic representation of a single bit Full Adder is shown below:

6. Explain the implementation of full adder adder?

a)The full adder circuit can be implemented with the help of two half adder circuits. The first
half adder circuit will be used to add A and B to produce a partial sum. The second half
adder logic can be used to add CIN to the sum produced by the first half adder circuit.
Finally, the output S is obtained.

If any of the half adder logic produces a carry, there will be an output carry. Thus,
COUT will be an OR function of the half adder CARRY outputs.

[Link] Carry Adder.

Ripple Carry Adder is a combinational logic circuit.
It is used for the purpose of adding two n-bit binary numbers.
It requires n full adders in its circuit for adding two n-bit binary numbers.
It is also known as n-bit parallel adder.

4-bit Ripple Carry Adder-

4-bit ripple carry adder is used for the purpose of adding two 4-bit binary numbers.
We have two 4-bit binary numbers A3A2A1A0 and B3B2B1B0 are added as shown below

Using ripple carry adder, this addition is carried out as shown by the following logic diagram-
• Each full adder takes the carry-in as input and produces carry-out and sum bit as output.
• The carry-out produced by a full adder serves as carry-in for its adjacent most significant full adder.
• When carry-in becomes available to the full adder, it activates the full adder.
• After full adder becomes activated, it comes into operation.
Working Of 4-bit Ripple Carry Adder-
• The two 4-bit numbers are 0101 (A3A2A1A0) and 1010 (B3B2B1B0).
• These numbers are to be added using a 4-bit ripple carry adder.

Stage-01:
• When Cin is fed as input to the full Adder A, it activates the full adder A.
• Then at full adder A, A0 = 1, B0 = 0, Cin = 0.

Full adder A computes the sum bit and carry bit as-
Calculation of S0 Calculation of C0
S0 = A0 ⊕ B0 ⊕ Cin C0 = A0B0 ⊕ B0Cin ⊕ CinA0
S0 = 1 ⊕ 0 ⊕ 0 C0 = 1.0 ⊕ 0.0 ⊕ 0.1
S0 = 1 C0 = 0 ⊕ 0 ⊕ 0
C0 = 0
Stage-02:
• When C0 is fed as input to the full adder B, it activates the full adder B.
• Then at full adder B, A1 = 0, B1 = 1, C0 = 0.

Full adder B computes the sum bit and carry bit as-
Calculation of S1 Calculation of C1
S1 = A1 ⊕ B1 ⊕ C0 C1 = A1B1 ⊕ B1C0 ⊕ C0A1
S1 = 0⊕1⊕ 0 C1 =0.1 ⊕ 1.0 ⊕ 0.0
S1 = 1 C1 = 0 ⊕ 0 ⊕ 0
C1 = 0
Stage-03:
• When C1 is fed as input to the full adder C, it activates the full adder C.
• Then at full adder C, A2 = 1, B2 = 0, C1 = 0.

Full adder C computes the sum bit and carry bit as-
Calculation of S2 Calculation of C2
S2 = A2 ⊕ B2 ⊕ C1 C2 = A2B2 ⊕ B2C1 ⊕ C1A2
S2 = 1 ⊕ 0 ⊕ 0 C2 = 1.0 ⊕ 0.0 ⊕ 0.1
S2 = 1 C2 = 0 ⊕ 0 ⊕ 0
 C2 = 0
Stage-04:
• When C2 is fed as input to the full adder D, it activates the full adder D.
• Then at full adder D, A3 = 0, B3 = 1, C2 = 0.

Full adder D computes the sum bit and carry bit as-
Calculation of S3 Calculation of C3
S3 = A3 ⊕ B3 ⊕ C2 C3 = A3B3 ⊕ B3C2 ⊕ C2A3
S3 = 0⊕ 1⊕ 0 C3 = 0.1 ⊕ 1.0 ⊕ 0.0
S3 = 1 C3 = 0 ⊕ 0 ⊕ 0
C3 = 0
Thus finally,
• Output Sum = S3S2S1S0 = 1111
• Output Carry = C3 = 0

[Link] Ripple Carry Adder is Called So?

• The carry out produced by each full adder serves as carry-in for its adjacent most significant full
adder.
• Each carry bit ripples or waves into the next stage.
• That’s why, it is called as “Ripple Carry Adder”.

[Link] are the Disadvantages of Ripple Carry Adder?

• Ripple Carry Adder does not allow to use all the full adders simultaneously.
• Each full adder has to necessarily wait until the carry bit becomes available from its adjacent full
adder.
• This increases the propagation time.
• Due to this reason, ripple carry adder becomes extremely slow.

[Link] encoder
a)An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has maximum
of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the input, which is
active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional to represent the
enable signal in encoders.
4 to 2 Encoder

Let 4 to 2 Encoder has four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. The block diagram of 4
to 2 Encoder is shown in the following figure.
At any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code at the
output.
The Truth table of 4 to 2 encoder is

Inputs Outputs

Y3 Y2 Y1 Y0 A1 A0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

From Truth table, we can write the Boolean functions for each output as
A1=Y3+Y2A1=Y3+Y2
A0=Y3+Y1A0=Y3+Y1
We can implement the above two Boolean functions by using two input OR gates. The circuit
diagram of 4 to 2 encoder is shown in the following figure.

The above circuit diagram contains two OR gates. These OR gates encode the four inputs with two bits

Octal to Binary Encoder

Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to binary
encoder is nothing but 8 to 3 encoder. The block diagram of octal to binary Encoder is shown in the
following figure.
At any time, only one of these eight inputs can be ‘1’ in order to get the respective binary code.
The Truth table of octal to binary encoder is shown below.

Inputs Outputs

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1

From Truth table, we can write the Boolean functions for each output as
A2=Y7+Y6+Y5+Y4 A2=Y7+Y6+Y5+Y4
 A1=Y7+Y6+Y3+Y2 A1=Y7+Y6+Y3+Y2
A0=Y7+Y5+Y3+Y1 A0=Y7+Y5+Y3+Y1
We can implement the above Boolean functions by using four input OR gates. The circuit diagram of
octal to binary encoder is shown in the following figure.

The above circuit diagram contains three 4-input OR gates. These OR gates encode the eight inputs
with three bits.
[Link]
a)Decoder is a combinational circuit that has ‘n’ input lines and maximum of 2n output lines. One of
these outputs will be active High based on the combination of inputs present, when the decoder is
enabled. That means decoder detects a particular code. The outputs of the decoder are nothing but
the min terms of ‘n’ input variables lines, when it is enabled.

2 to 4 Decoder

Let 2 to 4 Decoder has two inputs A1 & A0 and four outputs Y3, Y2, Y1 & Y0. The block diagram of
2 to 4 decoder is shown in the following figure.

One of these four outputs will be ‘1’ for each combination of inputs when enable, E is ‘1’. The Truth
table of 2 to 4 decoder is shown below.
Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 x x 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

1 1 0 0 1 0 0

1 1 1 1 0 0 0

From Truth table, we can write the Boolean functions for each output as
Y3=E.A1.A0 Y3=E.A1.A0

Y2=E.A1.A0′ Y2=E.A1.A0′

Y1=E.A1′.A0 Y1=E.A1′.A0

Y0=E.A1′.A0′ Y0=E.A1′.A0′

Each output is having one product term. So, there are four product terms in total. We can implement
these four product terms by using four AND gates having three inputs each & two inverters. The circuit
diagram of 2 to 4 decoder is shown in the following figure.
Therefore, the outputs of 2 to 4 decoder are nothing but the min terms of two input variables A1 & A0,
when enable, E is equal to one. If enable, E is zero, then all the outputs of decoder will be equal to zero.
Similarly, 3 to 8 decoder produces eight min terms of three input variables A2, A1 & A0 and 4 to 16
decoder produces sixteen min terms of four input variables A3, A2, A1 & A0.
6. Explain Multiplexer
Multiplexer is a combinational circuit that has maximum of 2n data inputs, ‘n’ selection lines and
single output line. One of these data inputs will be connected to the output based on the values of
selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination will select only one data input. Multiplexer is also called as Mux.

4x1 Multiplexer

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
The block diagram of 4x1 Multiplexer is shown in the following figure.

One of these 4 inputs will be connected to the output based on the combination of inputs present at
these two selection lines. Truth table of 4x1 Multiplexer is shown below.
 Selection Lines Output

S1 S0 Y

0 0 I0

0 1 I1

1 0 I2

1 1 I3

From Truth table, we can directly write the Boolean function for output, Y as
Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3Y=S1′S0′I0+S1′S0I1+S1S0′I2+S1S0I3

We can implement this Boolean function using Inverters, AND gates & OR gate. The circuit
diagram of 4x1 multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 8x1
Multiplexer and 16x1 multiplexer by following the same procedure.
6. Explain De-Multiplexer
De-Multiplexer is a combinational circuit that performs the reverse operation of Multiplexer. It has
single input, ‘n’ selection lines and maximum of 2n outputs. The input will be connected to one of
these outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination can select only one output. De-Multiplexer is also called as De-Mux.

1x4 De-Multiplexer

1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0.
The block diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of
selection lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Outputs
Inputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as
 Y3=s1s0I Y3=s1s0I

Y2=s1s0′I Y2=s1s0′I

Y1=s1′s0I Y1=s1′s0I

Y0=s1′s0′I Y0=s1′s0′I

We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit
diagram of 1x4 De-Multiplexer is shown in the following figure.

We can easily understand the operation of the above

circuit. Similarly, you can implement 1x8 De-
Multiplexer and 1x16 De-Multiplexer by following the
same procedure

[Link] Coded Decimal

Binary Coded Decimal (BCD or “8421” BCD) numbers are made up using just 4 data bits (a nibble or
half a byte) similar to the Hexadecimal numbers we saw in the binary tutorial, but unlike hexadecimal
numbers that range in full from 0 through to F, BCD numbers only range from 0 to 9, with the binary
number patterns of 1010 through to 1111 (A to F) being invalid inputs for this type of display and so are
not used as shown below.

Binary
Binary Pattern
Pattern
Decimal BCD Decimal BCD

8 4 2 1
8 4 2 1

0 0 0 0 0 0
8 1 0 0 0 8
 1 0 0 0 1 1 9 1 0 0 1 9

2 0 0 1 0 2 10 1 0 1 0 Invalid

3 0 0 1 1 3 11 1 0 1 1 Invalid

4 0 1 0 0 4 12 1 1 0 0 Invalid

5 0 1 0 1 5 13 1 1 0 1 Invalid

6 0 1 1 0 6 14 1 1 1 0 Invalid

7 0 1 1 1 7 15 1 1 1 1 Invalid

[Link] to 7-Segment Display Decoders

A binary coded decimal (BCD) to 7-segment display decoder such as the TTL 74LS47 or 74LS48, have
4 BCD inputs and 7 output lines, one for each LED segment. This allows a smaller 4-bit binary number
(half a byte) to be used to display all the denary numbers from 0 to 9 and by adding two displays
together, a full range of numbers from 00 to 99 can be displayed with just a single byte of eight data bits.
BCD to 7-Segment Decoder

Truth Table – For common cathode type BCD to seven segment decoder:

[Link] full subtractor

A)A full subtractor is a combinational circuit that performs subtraction of two bits, one is minuend and
other is subtrahend, taking into account borrow of the previous adjacent lower minuend bit. This
circuit has three inputs and two outputs. The three inputs A, B and Bin, denote the minuend,
subtrahend, and previous borrow, respectively. The two outputs, D and Bout represent the difference and
output borrow, respectively.
TRUTH TABLE LOGIC CIRCUIT

The SOP( standard operating procedure ) form of the Diff and Borrow is as follows:

Diff:
o Perform the XOR operation of input A and B.
o Perform the XOR operation of the outcome with 'Borrow'. So, the difference is (A XOR B) XOR
'Borrowin' which is also represented as:
(A ⊕ B) ⊕ 'Borrowin'

Borrow:
o Perform the 'AND' operation of the inverted input A and B.
o Perform the 'XOR' operation of input A and B.
o Perform the 'OR' operations of both the outputs that come from the previous two steps. So the
'Borrow' can be represented as:
A'.B + (A ⊕ B)'

[Link] Half Subtractor

a)The half subtractor is also a building block for subtracting two binary numbers. It has two
inputs and two outputs. This circuit is used to subtract two single bit binary numbers A and B.
The 'diff' and 'borrow' are two output states of the half subtractor.

Block diagram
Truth Table

The SOP( standard operating procedure ) form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B

The Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT' gates and provide
the Diff and Borrow.

The Boolean expression of the Half Adder circuit is given below:

Diff= A XORB (A⊕B)
Borrow= not-A AND B (A'.B)