Internal Organization of Memory Chips
Each memory cell can hold one bit of information.
Memory cells are organized in the form of an array.
One row is one memory word.
All cells of a row are connected to a common line, known as the word line.
Word line is connected to the address decoder.
The cells in each column are connected to a Sense/Write circuit by two
bit lines.
The Sense/Write circuits are connected to the data input/output lines of the
chip.
Figure 8.2 is an example of a very small memory circuit consisting of 16
words of 8 bits each.
This is referred to as a 16 × 8 organization.
The data input and the data output of each Sense/Write circuit are connected to
a single bidirectional data line that can be connected to the data lines of a
computer.
Two control lines, R/𝑊ഥ and CS, are provided.
ഥ
The R/𝑊(Read/Write ) input specifies the required operation, and the CS
(Chip Select) input selects a given chip in a multichip memory system.
The memory circuit in Figure 8.2 stores 128 bits and requires 14 external
connections for address, data, and control lines.
It also needs two lines for power supply and ground connections.
If the circuit has 1K (1024) memory cells, this circuit can be organized as a 128 × 8
memory, requiring a total of 19 external connections.
Alternatively, the same number of cells can be organized into a 1K×1 format.
In this case, a 10-bit address is needed, but there is only one data line, resulting in
15 external connections.
Figure 8.3 shows such an organization.
The required 10-bit address is divided into two groups of 5 bits each to form the
row and column addresses for the cell array.
A row address selects a row of 32 cells, all of which are accessed in parallel.
But, only one of these cells is connected to the external data line, based on the
column address.
Commercially available memory chips contain a much larger number of memory
cells than the examples shown in Figures 8.2 and 8.3
Large chips have essentially the same organization as Figure 8.3 but use a
larger memory cell array and have more external connections.
For example, a 1G-bit chip may have a 256M × 4 organization, in which case a 28-bit
address is needed and 4 bits are transferred to or from the chip.
Static Memories
Memories that consist of circuits capable of retaining their state as long as
power is applied are known as static memories.
Figure 8.4 illustrates how a static RAM (SRAM) cell may be implemented.
Two inverters are cross-connected to form a latch.
The latch is connected to two bit lines by transistors T1 and T2.
These transistors act as switches that can be opened or closed under
control of the word line.
When the word line is at ground level, the transistors are turned off and the
latch retains its state.
For example, if the logic value at point X is 1 and at point Y is 0, this state is
maintained as long as the signal on the word line is at ground level.
Assume that this state represents the value 1.
Read operation:
The word line is activated to close switches T1 and T2.
If the cell is in state 1, the signal on bit line 𝑏 is high and the signal on bit
line 𝑏′ is low.
The opposite is true if the cell is in state 0.
Thus, 𝑏 and 𝑏′ are always complements of each other.
The Sense/Write circuit at the end of the two bit lines monitors their
state and sets the corresponding output accordingly.
Write operation:
The Sense/Write circuit drives bit lines 𝑏 and 𝑏′, instead of sensing their
state.
It places the appropriate value on bit line 𝑏 and its complement on 𝑏′
and activates the word line.
This forces the cell into the corresponding state, which the cell retains
when the word line is deactivated.
CMOS cell:
A CMOS realization of the cell in Figure 8.4 is given in Figure 8.5
Transistor pairs (T3, T5) and (T4, T6) form the inverters in the latch.
The state of the cell is read or written as just explained.
For example, in state 1, the voltage at point X is maintained high by having transistors T3
and T6 on, while T4 and T5 are off.
If T1 and T2 are turned on, bit lines 𝑏 and 𝑏′ will have high and low signals, respectively.
SRAMs are said to be volatile memories because their contents are lost when power is
interrupted.
Advantage of CMOS SRAMs is their very low power consumption, because current flows
in the cell only when the cell is being accessed.
Otherwise, T1, T2, and one transistor in each inverter are turned off, ensuring that
there is no continuous electrical path between Vsupply and ground.
Static RAMs can be accessed very quickly.
Access times on the order of a few nanoseconds are found in commercially available
chips.
SRAMs are used in applications where speed is of critical concern.