VISVESVARAYA TECHNOLOGICAL UNIVERSITY

BELAGAVI, KARNATAKA

Report on
“DECENT WORK AND ECONOMIC GROWTH”
Submitted by
Sunidhi A S 1GA25CS105
Spoorthi B 1GA25CS123

Global Academy of Technology

BENGALURU – 560098
2024-2025
 GLOBAL ACADEMY OF TECHNOLOGY
An Autonomous Institute, Affiliated to VTU Belagavi, Approved by AICTE,
Accredited by NAAC, ‘A’ Grade
Department of Computer Science Engineering

CERTIFICATE
Certified that the project (21ECEP83) entitled
“Adaptive PLL for Dynamic voltage and Frequency scaling in Power-
Managed SoCs”
Carried out by,
Surabhi A S 1GA21EC150
Supreeth S 1GA21EC149
Ranjith Kumar R 1GA21EC150

Bonafide students of Global Academy of Technology in partial fulfillment for the award of
Bachelor of Engineering in Electronics and Communication Engineering of the Visvesvaraya
Technological University, Belagavi during the academic year 2024-25. It is certified that all
corrections/suggestions indicated for Internal Assessment have been incorporated in the Report
deposited in the Departmental library. The project report has been approved as it satisfies the
academic requirements in respect of project work prescribed for the said Degree.

Signature of the Guide Signature of the HOD Signature of the Principal

[ Dr. Madhavi M] [Dr. Madhavi M] [Dr. H B Balakrishna]

External Viva
Name of the examiners Signature with date
1.
2.
 GLOBAL ACADEMY OF TECHNOLOGY

Vision:

Become a premier institution imparting quality education in engineering and

management to meet the changing needs of society.

Mission:

● Create an environment conducive for continuous learning through quality

teaching and learning processes supported by modern infrastructure.
● Promote Research and Innovation through collaboration with industries.
● Inculcate ethical values and environmental consciousness through holistic
education programs.

Department of Electronics and Communication Engineering

Vision:

To Provide Quality Technical Education in Electronics and Communication

Engineering with a focus on global challenges and societal needs.

Mission:

● Comprehensive outcome-based education in the field of Electronics and

Communication Engineering through good practices of teaching – learning
with strong industry institute interaction.
● Create state-of- the-art infrastructure that enables system and subsystem level
development in hardware and software.
● Prepare students for development, research, innovation in emerging areas of
electronics and communication to become innovators, entrepreneurs and
leaders in the domain and interdisciplinary areas.
● Imbibe professional ethics and social values among the students with concern
for environment.

Program Educational Objectives (PEOs):

PEO1: Acquire technical knowledge of fundamentals of basic sciences, electronics and

communication engineering and applied mathematics for the rapid changes in
technology.
PEO2: Analyze, design, apply, evaluate and solve complex problems in technology
and management through engineering skills.
PEO3: Demonstrate team spirit by applying ethics and professional behavior.
PEO4: Involve in research and development in the field of electronics and
communication engineering and multi-disciplinary areas for lifelong learning.

Program Specific Outcomes (PSOs):

PSO1: Analyze, design and implement emerging electronics and communication

systems using devices, subsystems and networking.
PSO2: Exhibit technical skills necessary to choose careers in the design, implement
and testing, management and operation of Electronics and Communication circuits
and systems.

Course Outcomes (COs):

CO’s No. Course Outcomes

20ECP83 Select ideas from the current technology.
.1
20ECP83 Define problem statement based on appropriate literature survey.
.2
20ECP83 Design and implement the project by using suitable hardware and
.3 software.
20ECP83
.4 Draw suitable conclusion from the results.

Program Outcomes (POs):

1. Engineering knowledge: Apply the knowledge of mathematics, science,

engineering fundamentals, and an engineering specialization to the solution of
complex engineering problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze

complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering

problems and design system components or processes that meet the specified
needs with appropriate consideration for the public health and safety, and the
cultural, societal, and environmental considerations.

4. Conduct investigations of complex problems: Use research-based knowledge

and research methods including design of experiments, analysis and
interpretation of data, and synthesis of the information to provide valid
conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources,
and modern engineering and IT tools including prediction and modeling to
complex engineering activities with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual

knowledge to assess societal, health, safety, legal and cultural issues and the
consequent responsibilities relevant to the professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional

engineering solutions in societal and environmental contexts, and demonstrate
the knowledge of, and need for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and

responsibilities and norms of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a

member or leader in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities

with the engineering community and with society at large, such as, being able to
comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding

of the engineering and management principles and apply these to one’s own
work, as a member and leader in a team, to manage projects and in
multidisciplinary environments.

12. Lifelong learning: Recognize the need for, and have the preparation and ability
to engage in independent and life-long learning in the broadest context of
technological change
 ACKNOWLEDGEMENT
The satisfaction and the euphoria that accompany the successful completion of
any task would be incomplete without the mention of the people who made it
possible. The constant guidance of these persons and encouragement provided
crowned our efforts with success and glory. Although it is not possible to thank all the
members who helped with the completion of the major project work individually, I
take this opportunity to express my gratitude to one and all.

I am grateful to management and our institute, GLOBAL ACADEMY OF

TECHNOLOGY, with its very ideals and inspiration for having provided me with
the facilities which made this work a success.

I express my sincere gratitude to Dr. H. B. Balakrishna, Principal, Global

Academy of Technology, for the support and encouragement.

I wish to place on record my grateful thanks to Dr. Madhavi M, Head of the

Department, Department of ECE, Global Academy of Technology, for the constant
encouragement provided to me.

I am indebted with a deep sense of gratitude for the constant inspiration,

encouragement, timely guidance, and valid suggestions given to me by my guide, Dr.
Madhavi M, HOD, Department of ECE, Global Academy of Technology.

Students Name USN

Surabhi A S 1GA21EC150

Ranjith Kumar R 1GA21EC115

Supreeth S 1GA21EC149

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 ABSTRACT
As modern electronic systems continue to demand greater performance with lower
power consumption, Dynamic Voltage and Frequency Scaling (DVFS) has emerged
as a widely adopted technique for energy-efficient computing. DVFS enables a
system to adjust its operating voltage and clock frequency based on real-time
workload requirements, thereby reducing dynamic power consumption without
compromising performance during critical operations. A key component that
facilitates frequency adaptation in such systems is the Phase-Locked Loop (PLL).
However, conventional PLLs often suffer from long lock times and inefficient
transitions, making them suboptimal for rapid and frequent scaling events.
This project presents the design and implementation of an adaptive PLL specifically
optimized for DVFS applications in power-managed System-on-Chip (SoC)
environments. The proposed PLL architecture incorporates fast-locking mechanisms
and dynamic control capabilities to enable quick and stable frequency transitions,
which are crucial for real-time power management. Designed using 180nm CMOS
technology in Cadence, the circuit is simulated to analyze lock time, phase noise, and
power consumption under various operating conditions.
Through comparative analysis, the adaptive PLL demonstrates improved
responsiveness and energy efficiency compared to traditional fixed-frequency
designs. The integration of this adaptive PLL into a DVFS framework allows for
seamless and coordinated scaling of voltage and frequency, ensuring the system meets
performance demands while minimizing power usage. This work contributes to the
ongoing efforts in low-power VLSI design and serves as a building block for future
energy-aware SoC architectures, particularly in mobile, IoT, and embedded platforms
where power efficiency is paramount.

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 TABLE OF CONTENTS

Chapter Topic Page No.

No.

I Acknowledgment i

II Abstract ii

III Table of Contents iii

IV List of Figures iv

1 Introduction 1

2 Literature Survey 4

3 System Implementation 6

4 Results and Discussions 15

Advantages, Disadvantages 20

Applications 23

Conclusion 25

Future Scope 26

References 27

iii
 LIST OF FIGURES

Figure No. Name of The Figure Page No.

3.1 PLL block diagram 6

3.1.1 PFD Schematic 7

3.1.2 Charge Pump Schematic 8

3.1.4 VCO Schematic 9

3.1.5 Frequency Divider Schematic 10

3.1.6 Programmable Frequency Divider Schematic 11

3.2 DVFS Schematic 12

3.3 Overall Block Diagram 14

4.1(a) PFD output when reference clk leads 15

4.1(b) PFD output when feedback leads 15

4.2 Charge pump when down signal is high 16

4.3 VCO Output 17

4.4 PLL Output 27

4.5 Programmable FD Output 18

4.6 DFS Output 19

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 Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

CHAPTER 1

INTRODUCTION

1.1 Background of DVFS in SoCs

With the rapid advancement in semiconductor technology and the proliferation of

mobile and portable electronic devices, power efficiency has become a critical design
metric in modern System-on-Chip (SoC) architectures. The demand for high
performance coupled with low power consumption necessitates the adoption of
dynamic power management techniques. One widely used approach is Dynamic
Voltage and Frequency Scaling (DVFS), which adjusts the supply voltage and
operating frequency of a processor based on workload requirements. This allows the
system to save energy during low-demand periods while maintaining performance
under peak loads.

At the heart of DVFS lies the need for a precise and adaptable clock generation
system. Phase-Locked Loops (PLLs) are commonly employed in SoCs for clock
generation and synchronization. Traditional PLLs generate a fixed-frequency output,
but in a DVFS- enabled SoC, the PLL must dynamically adapt its output frequency in
real-time according to voltage and workload changes.

As devices become more compact and power-sensitive—especially in mobile,

wearable, and IoT applications—the ability to finely control performance and energy
usage becomes essential. In this context, the PLL is not just a frequency generator but
a dynamic control element that enables the processor to adapt to varying
computational loads. By facilitating rapid transitions between different clock
frequencies, a well- designed PLL enables the system to operate in high-performance
modes during peak demand and switch to low-power modes during idle or light
workloads. However, these transitions must occur with minimal delay and without
compromising signal stability. An adaptive PLL addresses these challenges by
incorporating feedback and control mechanisms that allow it to lock quickly, maintain
stability, and minimize power losses during frequency changes. Thus, the adaptive
PLL becomes a key enabler of energy- efficient SoC design, ensuring both
performance scalability and power savings under real-time operating conditions.

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1.2 Role of PLL in frequency scaling

The Phase-Locked Loop (PLL) is a fundamental building block in modern digital

systems used for generating stable and precise clock signals. In frequency scaling
applications, such as Dynamic Voltage and Frequency Scaling (DVFS), the PLL plays
a crucial role by providing a controllable clock frequency that can be adjusted
dynamically according to the system’s performance and power requirements.

A PLL locks onto a reference clock and generates an output clock whose frequency is
a multiple (or fraction) of the reference. By changing the division ratios or control
voltage within the PLL’s components—such as the voltage-controlled oscillator
(VCO)—the output frequency can be varied in real-time. This capability enables the
system to lower the operating frequency during periods of low workload, reducing
dynamic power consumption, or increase it when higher performance is needed.

In adaptive PLL designs, this frequency scaling is made more efficient and faster by
incorporating control mechanisms that quickly adjust the PLL parameters, ensuring
minimal lock time and stable operation during frequency transitions. Consequently,
the PLL is central to implementing effective DVFS schemes in power-managed SoCs,
balancing the trade-off between power savings and system responsiveness.

1.3 Problem Statement

Modern power-managed System-on-Chips (SoCs) require efficient clock generation

systems that can dynamically adjust operating frequency and voltage to optimize
power consumption without sacrificing performance. Traditional Phase-Locked Loop
(PLL) designs typically operate at fixed frequencies and lack the flexibility to quickly
respond to changes in workload or voltage scaling, resulting in longer lock times and
higher power dissipation. This limitation poses a significant challenge in
implementing effective Dynamic Voltage and Frequency Scaling (DVFS) strategies,
which are crucial for reducing energy usage in portable and battery-powered devices.
Therefore, the problem addressed in this project is how to design and implement an
adaptive PLL capable of fast, reliable frequency adjustments in response to voltage
changes within a 180nm CMOS technology framework, thereby enabling efficient
DVFS in power- managed SoCs while minimizing lock time and overall power
consumption.
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1.4 Objectives

The key objectives of this project are:

i. To study the fundamental concepts of PLL design and DVFS in SoCs.

ii. To design an adaptive PLL circuit that can dynamically adjust frequency in

response to voltage changes.

iii. To implement the PLL using Cadence Virtuoso in 180nm CMOS technology.

iv. To analyze the performance in terms of lock time, power consumption, and

frequency stability.

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CHAPTER 2 LITERATURE

SURVEY

Jasmin and Philomina, [1] have, discussed various power optimization techniques for
MPSoCs and highlighted the importance of reducing power consumption in Network-
on-Chip (NoC)-based architectures. The study emphasized that power dissipation
occurs primarily in logic elements, clocking circuits, and data communication links,
making runtime power optimization a key requirement.

Song et al., [2] have examined various low-power design techniques in semiconductor
chips. The paper discusses how DVFS allows dynamic adjustment of voltage and
frequency to reduce power consumption during low-demand periods, while
maintaining performance during peak loads.

Priyam Kumar et al., [3] in their presented paper introduces a design for a phase-locked
loop (PLL) that is utilized in frequency synthesis in VLSI applications. The CMOS
PLL is designed using 180 nm Fabrication Technology on Cadence Virtuoso Tool
with a supply voltage of 1.8 V.

Rao et al., [4] proposed a real-time dynamic voltage scaling method for embedded system
processors, which introduces pseudo-operating frequency levels between discrete
frequencies supported by the system. This technique addresses the inefficiency caused
by the inability to vary frequency continuously. The authors demonstrated that this
method, when combined with existing DVFS algorithms, can achieve up to 70%
energy savings, which is a 25% improvement over the best conventional approaches.

Sanjana Hokrani et al., [5] in their paper signifies the transient analysis of the PLL and is
implemented in cadence tool using 180nm technology node. Frequency is expected to
be in GHz range for present communication systems to increase the speed and
therefore PLL is designed to produce the frequency in GHz range. The designed PLL
consists of Phase frequency detector/Charge pump (PFD/CP), second order Low pass
filter (LPF) and Schmitt trigger based current starved voltage controlled oscillator
(CSVCO).

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Vimala Madala and Ganesh Kumar Chellamani, [6] in this research contributes novel
insights to the field of power management in real-time embedded systems,
specifically through the application of dynamic voltage frequency scaling (DVFS) for
CMOS-based devices. It advances beyond existing literature by critically analyzing
and offering innovative solutions in power-aware scheduling, a key yet underexplored
aspect in energy efficiency. The study challenges traditional approaches focused on
increasing battery capacity, proposing instead a more sustainable, efficiency-centric
strategy. A detailed examination of various DVFS techniques is conducted. Python-
based simulations facilitate a comparative analysis against traditional algorithms like
EDF and its derivatives.

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CHAPTER 3

SYSTEM IMPLEMENTATION

3.1 Phase-Locked Loop (PLL) Fundamentals

A Phase-Locked Loop (PLL) is a feedback control system that synchronizes an output

signal’s phase and frequency with that of a reference signal. It is widely used in clock
generation, frequency synthesis, and signal recovery in digital and analog systems.
The core components of PLL include:

 Phase-Frequency Detector (PFD)

 Charge Pump (CP)
 Loop Filter (LF)
 Voltage-Controlled Oscillator (VCO)
 Frequency Divider

Fig. 3.1(a) PLL block diagram

3.1.1 Phase-Frequency Detector (PFD)

The Phase-Frequency Detector (PFD) is responsible for comparing the phase and
frequency of two input signals—typically the reference clock and the feedback clock
from the VCO. Unlike simple XOR-based phase detectors, the PFD detects both
phase and frequency differences, which improves acquisition range and lock time.

 It produces two outputs: UP and DOWN.

 If the reference signal leads the feedback, the UP signal is asserted.
 If the feedback leads, the DOWN signal is asserted.
 If both signals are in phase, both outputs go low.

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PFDs are typically implemented using D flip-flops and logic gates, and they reset both
outputs when inputs are aligned, reducing phase jitter.

Fig. 3.1.1 PFD Schematic

The Fig. 3.1.1 shows a classic PFD architecture designed in Cadence using 180nm
technology. This standard PFD is implemented using two D flip flops and a reset
logic based on NAND gate.

The PFD designed in 180 CMOS technology, ensures fast detection and reliable phase
comparison making it highly suitable for adaptive PLL used in DVFS applications.

3.1.2 Charge Pump (CP)

The Charge Pump converts the digital UP and DOWN pulses from the PFD into current
signals. It sinks current into the loop filter based on the control inputs:

 If UP is high, the charge pump sources current into the loop filter, increasing
the control voltage.
 If DOWN is high, it sinks current, decreasing the control voltage.
 When both UP and DOWN are low, no current is transferred, and the control
voltage remains unchanged.

Charge pump linearity is critical to minimize phase noise and maintain PLL stability. Any
mismatch between source and sink currents can cause static phase error.

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Fig. 3.1.2 Charge Pump Schematic

The schematic represented in Fig. 3.1.2 is designed using matched PMOS and NMOS
transistor. The filter integrated serves to smooth voltage pulses from the charge pump,
effectively attenuation high frequencies and ripple, thereby generating clean DC
voltage for the VCO.

This integration improves loop stability and reduces phase noise, which is particularly
beneficial in adaptive PLLs used for DVFS in low power SoC applications.

3.1.3 Loop Filter (LF)

The Loop Filter smooths the pulsating current from the charge pump into a stable
voltage. It determines the dynamic response of the PLL, such as bandwidth, stability,
and settling time.

 Commonly implemented as a low-pass filter using capacitors and resistors.

 A second-order passive filter is typical, which provides good trade-offs
between response speed and noise rejection.

The loop filter output is the control voltage applied to the VCO. Its design must
carefully balance noise filtering with fast settling performance.

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3.1.4 Voltage-Controlled Oscillator (VCO)

The Voltage-Controlled Oscillator (VCO) is the frequency-generating element of the

PLL. It outputs a periodic waveform (usually square or sine wave) whose frequency is
a function of the input control voltage. The VCO must offer a wide tuning range, high
linearity, and low phase noise. In CMOS designs, ring oscillators are common due to
their simplicity and compatibility with digital logic.

Fig. 3.1.4 VCO Schematic

The schematic as shown in Fig. 3.1.4 illustrates that the design consists of a chain of
delay stages implemented using current-starved inverter pairs where each stage is
constructed using complementary PMOS and NMOS transistors.

This VCO is well suited for low power, high frequency applications and its
integration in adaptive PLL enables dynamic adjustments of the clock signal in
response to the workload as in DVFS for Socs.

3.1.5 Frequency Divider

The Frequency Divider scales down the VCO output frequency before it is fed back
into the PFD. It enables the PLL to lock the VCO frequency to a multiple of the
reference frequency.

Implemented using flip-flop-based counters. In adaptive PLLs, the divider may be

programmable to allow dynamic frequency changes. The divider ensures the PLL can

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support frequency synthesis across a range of frequencies using a single reference

clock.

Fig. 3.1.5 Frequency Divider Schematic

The above schematic shown in Fig. 3.1.5 represents the frequency divider
implemented using the CMOS logic is used to reduce the frequency of input signal
Vin typically by 2.

At the core of the circuit, pairs of NMOS and PMOS transistors operates as the
controlled switches, forming D flipflops that responds to rising and falling edges of
the clock signal. The control voltage Vin serves as the input clock and the output Vout
serves as the frequency divided output.

This frequency divider within the PLL system provides the reference frequency for
comparison with the output of the VCO, enabling the feedback.

3.1.6 Programmable Frequency Divider

As part of the Adaptive PLL for Dynamic Voltage and Frequency Scaling (DVFS), a
programmable frequency divider was implemented using a series of D flip-flops
(DFFs) and basic combinational logic gates in Cadence Virtuoso using 180nm
technology. The schematic consists of three D flip-flops configured sequentially,
where each flip-flop divides the clock frequency by two. The outputs of these flip-
flops are combined with an AND gate, which monitors specific output conditions to
trigger a reset or toggle action. A NOT gate is also used, likely to generate a reset
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signal or to invert a control

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signal for proper synchronization. The presence of a control input labeled mc

(possibly master control or mode control) suggests that the circuit is designed to be
programmable or configurable, allowing the division factor to be adjusted
dynamically. The main clock input (clk) drives all flip-flops, and the final output
(yout) provides the frequency- divided signal, which can be used as feedback in the
PLL loop. This output frequency is a function of the programmed division factor,
enabling real-time adjustment of the PLL output frequency. This design is particularly
useful in DVFS systems, where the system dynamically scales down the frequency
and voltage during low-load conditions to save power and scales up during
performance-intensive tasks. The combination of sequential and combinational logic
in this frequency divider provides both flexibility and precision, making it an essential
component in achieving adaptive frequency control in modern low-power SoC
applications.

Fig. 3.1.6 Programmable Frequency Divider Schematic

 The circuit takes a high-frequency clock input and divides it to produce a

slower clock output.
 Three D flip-flops are connected in sequence to count the incoming clock
pulses.
 The output of the flip-flops changes with each clock cycle, creating a binary
counting effect.
 An AND gate monitors the outputs of the flip-flops to detect when a specific
count is reached.
 When the desired count is detected, the output signal (yout) toggles, producing

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a divided clock.

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 A control signal (mc) is used to change the division factor, making the circuit
programmable.
 The circuit can switch between divide-by-4 and divide-by-5 modes depending
on the control input.
 This divided output is used in the PLL for dynamic frequency adjustment.

3.2 Dynamic Voltage and Frequency Scaling (DVFS) Mechanism

Dynamic Voltage and Frequency Scaling (DVFS) is a power management technique used
in modern processors and SoCs to reduce energy consumption by adjusting the
operating voltage and frequency according to the system’s workload. Since power
consumption in CMOS circuits is strongly dependent on supply voltage and operating
frequency, DVFS enables the system to run at high performance when needed and at
low power during idle or low activity periods.

Dynamic Voltage and Frequency Scaling (DVFS) works by intelligently adjusting the
processor’s supply voltage and operating frequency in real-time based on workload
demands. When the system is performing light tasks or is idle, the DVFS controller
reduces the clock frequency and corresponding supply voltage to minimize power
consumption. Conversely, during high-performance tasks, the controller increases the
frequency and voltage to meet computational requirements. This adjustment is done
through coordinated control of voltage regulators and clock-generating circuits, such
as Phase-Locked Loops (PLLs). The PLL dynamically changes the system clock
frequency while the voltage regulator adjusts the supply voltage, ensuring that the
device operates efficiently at each performance level. This mechanism allows the
system to balance power and performance dynamically, reducing overall energy usage
while maintaining system responsiveness.

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Fig. 3.2 DVFS Schematic

A power management method called dynamic frequency scaling (DFS) is

implemented as shown in Fig. 3.2 and it modifies a digital system's clock frequency in
real time according to workload demands.

The main goal of this design is to provide a stable and controllable clock signal whose
frequency can be dynamically adjusted based on system requirements. This dynamic
control enables the chip to operate at high performance when needed and at low
power during idle or low-load conditions, which is critical in energy-constrained
devices.

The loop begins by accepting an external reference clock, which is compared with a
feedback signal to align both phase and frequency. The result of this comparison is
used to generate a control voltage that adjusts the output frequency of the oscillator.
The output of the oscillator is then fed back into the loop, creating a self-correcting
mechanism that ensures the generated clock remains locked to the reference over
time.

To support DVFS, a programmable element allows the system to change the

frequency division ratio, enabling real-time adjustment of the output frequency. This
adaptability allows the frequency to be scaled depending on performance or power-
saving requirements.

This clock signal is then distributed to the rest of the system, which can include
various digital processing blocks. Since the output frequency directly impacts power
consumption and performance, this design is well-suited for integration into chips that
demand low-power operation with dynamic performance scaling.

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3.3 Block diagram of proposed system

Fig. 3.3 Overall Block Diagram

The overall block design as shown in Fig. 3.3 combines a Dynamic Voltage and
Frequency Scaling (DVFS) system for power-managed SoCs with an Adaptive PLL,
integrating the ideas from the first two models.

Clock accuracy is further enhanced with an adaptive loop filter and a jitter monitoring
device. Based on workload needs, the DVFS controller dynamically modifies power
and clock frequency in conjunction with the noise suppression circuit and voltage
regulator. A gating mechanism is then used to distribute the improved clock to the
CPU. This adaptive strategy is appropriate for sophisticated SoC architectures as it
guarantees power efficiency while preserving high performance.

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CHAPTER 4

RESULT ANALYSIS AND DISCUSSION

4.1 Phase Frequency Detector (PFD) Output

4.1.1 PFD output when reference clk leads

Fig. 4.1(a) PFD output when reference clk leads

The graphical representation in Fig. 4.1(a) shows the behavior of PFD when reference
signal leads.
Hence, the up signal goes high while the down signal stays low. This shows the
leading-edge condition of the PFD signal.

4.1.2 PFD Output when feedback leads

Fig. 4.1(b) PFD output when feedback leads

The graphical representation in Fig. 4.1(b) shows the behavior of PFD when feedback
signal leads. In the Fig 10(b) the feedback clock leads the reference signal. Here the

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down signal goes high whereas the up signal stays low. This shows the actual detection
of the pulse generation.
These transitions are crucial in correcting phase or frequency errors.

4.2 Charge Pump with LPF

F
ig. 4.2 Charge pump when down signal is high

The UP signal is activated (high) in the waveform shown in Fig 4.2. This happens
when the feedback clock (from the divider) is being led by the reference clock (REF).
The charge pump is instructed to source current to the loop filter by the UP pulse that
the PFD generates. This causes the VCO's control voltage (Vcont) to rise, which
accelerates the VCO output. This keeps on until the reference and the feedback match.
The clean and consistent UP signal indicates proper detection by PFD and correct
sourcing behavior of the charge pump.

The DOWN signal is activated (high) in this waveform shown in Fig 10(d). When the
feedback clock is ahead of the reference clock, this happens. The charge pump is told
to sink current from the loop filter by the PFD's DOWN pulse. This lowers the VCO

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frequency by lowering the control voltage (Vcont). The loop aims to synchronize the
reference and feedback.

4.3 VCO Output

Fig. 4.3 VCO Output

The VCO output frequency is plotted against the control voltage (Vcont) in Fig. 4.3.
Particularly in the operational voltage range, it is noted that the curve appears
monotonic and approximately linear. For consistent and seamless frequency
adjustment inside the loop, this is crucial. The slope of this graph can be used to
assess the tuning sensitivity (Hz/V). The PLL can retain stability and lock range with
a well-behaved tuning curve, which guarantees that the VCO output reacts
proportionately to the control voltage from the loop filter.

4.4 PLL Output

Fig. 4.4 PLL Output

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

The output of the frequency divider, which splits the high-speed VCO output to match
the reference frequency, is displayed in the waveform shown in Fig 4.4. As a result,
the output waveform is regarded as clean and periodic. It helps the PFD compare this
signal with the reference by acting as feedback. The locking time and loop gain are
directly impacted by the divider ratio.
This verifies that your division is operating properly and generating a clear signal,
both of which are necessary for steady PLL operation.

4.5 Programmable Frequency Divider

Fig. 4.5 Programmable FD Output

The Fig. 4.5 is the graphical representation of the programmable frequency divider
output. The waveform consists of input signal which is high frequency and periodic.
The middle waveform corresponds to mode input MI signal which dynamically
controls the division factor of the circuit.

This programmable divider helps in scaling the frequency dynamically with respect to
various workloads.

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4.6 Final DFS Output

Fig. 4.6 DFS Output

The waveform shown in figure Fig. 4.6 represents the transient simulation results of
the adaptive Phase-Locked Loop (PLL) circuit integrated within a Dynamic Voltage
and Frequency Scaling (DVFS) framework. The red trace (/net7) likely corresponds to
the reference clock input, which serves as the frequency standard for the PLL. The
blue trace (/vco) shows the output of the Voltage-Controlled Oscillator (VCO), which
varies its frequency dynamically based on control signals, indicating the system's
adaptive frequency response. The magenta signal (/net11) represents the control
voltage or a signal related to the DVFS control logic that initiates changes in
operating conditions. Notably, it shows distinct voltage levels, each held constant for
a period, reflecting different performance states (P-states). The green trace (/vout)
represents the final output clock or system response, clearly demonstrating changes in
output pulse width and frequency in response to the transitions in /net11. This
confirms that the adaptive PLL successfully tracks the frequency adjustments required
by the DVFS mechanism. The waveform illustrates smooth transitions between states
with stable locking behavior, highlighting the effectiveness of the PLL design in
supporting real-time voltage and frequency adjustments essential for energy-efficient
SoC operation.

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

ADVANTAGES

Adaptive Phase-Locked Loops (PLLs) are critical for enabling efficient Dynamic
Voltage and Frequency Scaling (DVFS) in power-managed Systems-on-Chip (SoCs).
Their advantages span energy efficiency, performance optimization, and adaptability
to dynamic operating conditions, making them indispensable for modern electronics.
Below is a detailed overview of their key benefits:

 Energy Efficiency:-

Adaptive PLLs reduce power consumption by 55% compared to static voltage scaling
through precise voltage-frequency alignment . By dynamically adjusting to workload
demands, they eliminate the need for worst-case voltage margins, minimizing energy
waste during idle or low-activity periods . For example, in mobile devices, this
enables prolonged battery life by scaling CPU/GPU voltages during background
tasks.

 Real-Time Adaptation:-

These systems compensate for process variations, temperature fluctuations, and load
changes in real time. Closed-loop architectures (e.g., AVS) continuously monitor
silicon performance, adjusting voltages to the minimum required for stable operation.
This eliminates the need for fixed voltage-frequency tables, which often
overcompensate for environmental uncertainties.

 Reduced Latency:-

Multi-PLL architectures (e.g., SysScale) enable simultaneous frequency switching

across SoC domains, cutting DVFS transition times to nanoseconds . Unlike
traditional PLLs, adaptive designs avoid lengthy relocking phases, ensuring seamless
performance during rapid workload shifts. This is particularly vital for real-time
systems like automotive ADAS, where delays could compromise safety.

 Performance Optimization:-

Adaptive PLLs maintain timing integrity during voltage scaling, preventing errors in
high-speed circuits like SerDes interfaces. By synchronizing clock signals with
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voltage

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

transitions, they mitigate skew and jitter, ensuring reliable operation even at sub-1V
levels. This capability is critical for data centers, where per-core DVFS optimizes
server performance without destabilizing adjacent domains.

 Scalability Across Domains:-

Fine-grained DVFS supports per-core or per-block voltage control, allowing

heterogeneous SoCs to balance power and performance dynamically. For instance,
IoT devices can scale sensor interfaces independently from processing cores,
optimizing energy use during sleep modes. This granularity also benefits AI
accelerators, where varying compute demands require localized adjustments.

 Thermal Management:-

By minimizing voltage margins, adaptive PLLs reduce heat generation, addressing

thermal bottlenecks in compact designs like wearables and servers . In 3D-ICs, they
manage interposer-based voltage domains, preventing hotspots in stacked memory-
processor configurations. This extends device longevity and enables sustained peak
performance without throttling.

 Compensation for Aging and Variability:-

Self-healing PLLs integrate aging sensors to counteract silicon degradation over time,
maintaining optimal voltage-frequency curves throughout a chip’s lifecycle. This is
particularly valuable for automotive and industrial systems, where reliability under
prolonged stress is paramount.

 Design Flexibility:-

Adaptive PLLs support mixed analog-digital implementations, enabling integration

with on-chip voltage regulators and performance monitors. Their modular architecture
simplifies scaling across process nodes, from legacy CMOS to advanced FinFET
technologies. This flexibility future-proofs SoC designs against evolving power
management standards.

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

DISADVANTAGES

Although adaptive Phase-Locked Loops (PLLs) offer many benefits for Dynamic
Voltage and Frequency Scaling (DVFS), they also have some drawbacks.
Firstly, adaptive PLLs increase the design complexity due to additional control
circuits and feedback loops needed to monitor voltage and frequency changes. This
makes the design, testing, and verification process more challenging.
Secondly, the extra circuitry adds to the chip’s area and power consumption, which
can partially reduce the overall energy savings. This is a concern, especially in cost-
sensitive or space-limited applications.
Thirdly, adaptive PLLs can be more sensitive to noise and clock jitter, affecting
timing accuracy and system stability, requiring careful design and noise mitigation.
Additionally, managing multiple voltage domains and clock synchronization across
these domains introduces implementation challenges that complicate the design
further. Finally, these complexities can increase development costs and extend time-
to-market, which may not be justified for simpler devices.

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

APPLICATIONS

Applications of Adaptive PLL for DVFS in Power-Managed SoCs are as follows:

 Mobile Devices and Smartphones :-

Adaptive PLLs enable dynamic voltage and frequency scaling in mobile processors,
allowing devices to lower power consumption during light workloads and ramp up
performance for demanding applications. This leads to significant battery life
extension and efficient thermal management, which is crucial for smartphones,
tablets, and wearable devices.

 Embedded and IoT Systems :-

In ultra-low-power embedded systems and IoT devices, adaptive PLLs are used to
optimize energy consumption by dynamically adjusting operating frequencies based
on workload requirements. This is essential for battery-powered sensors and edge
devices that require long operational lifetimes with minimal maintenance.

 Data Centers and Servers :-

Adaptive PLLs facilitate fine-grained DVFS in server processors, enabling per-core or

per-domain frequency and voltage adjustments. This helps data centers optimize
energy usage, reduce operational costs, and manage thermal loads, especially under
variable workloads.

 Automotive Electronics :-

Power-managed SoCs with adaptive PLLs are integral to automotive applications

such as advanced driver-assistance systems (ADAS) and infotainment, where real-
time performance and reliability are critical. Adaptive DVFS helps manage heat and
power budgets in these safety-critical systems.

 FPGA-Based Systems :-

In next-generation mobile and embedded devices using FPGAs, adaptive PLLs

support low-power design techniques by allowing dynamic frequency
adjustments. This

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enhances the flexibility and energy efficiency of FPGAs in applications ranging from
mobile computing to digital cameras and medical devices.

 Communication Systems :-

Adaptive PLLs are used in LTE/5G modem SoCs to manage power dynamically
during periods of low data transmission, enabling devices to enter low-power state
more frequently. This is especially beneficial in mobile broadband and wireless
communication devices where energy efficiency is a priority.

 Thermal Management in High-Performance Computing :-

Adaptive PLLs, combined with thermal monitoring, allow processors to reduce

frequency and voltage when high temperatures are detected, preventing overheating
and ensuring sustained performance in desktops, laptops, and high-performance
computing platforms

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

CONCLUSION

In this project, we successfully designed and analyzed an adaptive Phase-Locked

Loop (PLL) system tailored for Dynamic Voltage and Frequency Scaling (DVFS) in
power- managed Systems-on-Chip (SoCs). Through our work, we demonstrated how
adaptive PLLs can dynamically adjust clock frequencies in response to voltage
changes, enabling efficient power management without sacrificing system
performance or stability.
Our implementation showcased the advantages of adaptive PLLs, including reduced
power consumption, minimized latency during frequency transitions, and improved
resilience against process variations and environmental fluctuations. The project also
highlighted practical applications of this technology in mobile devices, data centers,
automotive electronics, and IoT systems, emphasizing its broad relevance in today’s
electronics landscape.
Furthermore, we explored the future potential of adaptive PLLs, identifying
opportunities for finer-grained control, integration with intelligent power management
units, and AI-driven predictive scaling techniques. These insights provide a roadmap
for further enhancements that can push the boundaries of energy efficiency and
performance optimization in SoCs.
Overall, this project not only deepened our understanding of adaptive PLL design and
DVFS mechanisms but also contributed valuable perspectives on their
implementation challenges and solutions. The successful completion of this work
underscores the critical role adaptive PLLs will play in advancing low-power, high-
performance integrated circuits for next-generation electronic devices.

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

FUTURE SCOPE

The future of adaptive PLLs in DVFS lies in enabling even finer-grained voltage and
frequency control, down to per-core or per-block levels within SoCs. This allows
independent and rapid adjustment of operating points for different functional units,
maximizing energy savings and performance across diverse workloads.

Future SoCs will increasingly integrate sophisticated power management units that
can coordinate adaptive PLLs, voltage regulators, and sensors. These PMUs will use
real- time data to optimize power delivery and frequency scaling, further reducing
energy waste and improving system responsiveness.

The development of integrated voltage regulators capable of rapid, simultaneous

voltage switching across multiple domains will be crucial. Such regulators, when
paired with adaptive PLLs, will enable nanosecond-scale DVFS transitions, unlocking
significant energy savings in high-performance and energy-constrained systems.

Incorporating AI and machine learning algorithms into power management

frameworks will allow predictive and workload-aware DVFS. Adaptive PLLs can
work in tandem with these algorithms to anticipate performance needs and
preemptively adjust voltage and frequency, minimizing latency and maximizing
efficiency.

As the demand for ultra-low-power embedded and IoT systems grows, adaptive PLLs
will be tailored for these applications, supporting aggressive energy optimization
while maintaining reliable operation in diverse and unpredictable environments.

Future adaptive PLLs will integrate more advanced sensors for real-time thermal
monitoring and aging compensation, ensuring long-term reliability and consistent
performance as devices operate in harsh or variable conditions.

While fine-grained adaptive voltage scaling offers substantial theoretical benefits,

future research will focus on overcoming challenges such as area overhead, clock
synchronization, and efficient communication between asynchronous voltage
domains. Advances in circuit design and packaging will be key to making these
solutions commercially viable.
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REFERENCES
1. Jasmin, M., and S. Philomina. Runtime adaptive Dynamic Voltage Frequency
Scaling technique for reducing the power consumption in Multi-Processor System
On Chip.
2. Song, Cen, Gang Zhao, and Binghan Wu. "Applications of Low-Power Design in
Semiconductor Chips." Journal of Industrial Engineering and Applied Science 2,
no. 4 (2024): 54-59.
3. Kumar, Priyam, Akshada Khele, and Aditee C. Joshi. "Design of Phase Locked
Loop in 180 nm Technology." arXiv preprint arXiv:2406.13462 (2024).
4. Rao, Venkat, Gaurav Singhal, and Anshul Kumar. "Real time dynamic voltage
scaling for embedded systems." In 17th International Conference on VLSI Design.
Proceedings., pp. 650-653. IEEE, 2004.
5. Hokrani, Sanjana, T. C. Thanuja, and K. V. Kumaraswamy. "Design and
implementation of Phase Locked Loop on 180nm Technology node." In 2018 4th
International Conference for Convergence in Technology (I2CT), pp. 1-6. IEEE,
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6. Madala, Vimala, and Ganesh Kumar Chellamani. "Energy efficiency of embedded
controllers through DVFS." In 2024 Fourth International Conference on
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Technologies (ICAECT), pp. 1-5. IEEE, 2024.
7. David, Howard, Chris Fallin, Eugene Gorbatov, Ulf R. Hanebutte, and Onur
Mutlu. "Memory power management via dynamic voltage/frequency scaling." In
Proceedings of the 8th ACM international conference on Autonomic computing,
pp. 31-40. 2011.
8. Yang, Jian, Tailong Xu, Xi Meng, Zhenghao Li, Jun Yin, Rui P. Martins, Pui-In
Mak, and Quan Pan. "Design and Analysis of a Type-II Sampling PLL With
Automatic Frequency and Phase Calibrations Achieving 0.62-$\mu $ s Locking
Time." IEEE Transactions on Circuits and Systems I: Regular Papers (2025).
9. Basehore, Derek, Nick Sanders, Stephen Boyd, Sonny Rao, and Alex Levin. "Fast
Adaptive Voltage and Boost Frequencies for Central Processing Units." (2019).
10. Barraj, I., Mestiri, H. and Masmoudi, M., 2024. Overview of Memristor-Based
Design for Analog Applications. Micromachines, 15(4), p.505.

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CERTIFICATES

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Adaptive PLL for Dynamic voltage and Frequency scaling in Power-Managed SoCs

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