NEHRU INSTITUTE OF TECHNOLOGY
(Autonomous)
Approved by AICTE, New Delhi & Affiliated to Anna University, Chennai
Accredited by NAAC with A+, Recognized by UGC with Section 2(f)
Kaliapuram, Coimbatore-641105.
Department of Artificial Intelligence and Machine Learning
Question Bank
U23AL303 Digital principles and Computer Organization
Class : II AIML Semester : III
(Regulation 2023)
MCQ Questions
UNIT I
1. The output of a 2-input AND gate is high when: CO1 L2
a) Both inputs are low b) Both inputs are high
c) Any input is high d) Any input is low
2. A 4-to-1 multiplexer has: CO1 L2
a) 2 select lines b) 4 inputs
c) 1 input d) 8 outputs
3. The function of a decoder is to: CO1 L1
a) Encode data b) Convert n inputs to 2ⁿ outputs
c) Add numbers d) Store data
4. A full-adder has: CO1 L1
a) 1 input b) 2 outputs
c) 3 inputs and 2 outputs d) 4 inputs and 1 output
5. The complement of a binary number can be generated by: CO1 L1
a) AND gate b) OR gate
c) NOT gate d) XOR gate
6. A BCD adder is used for: CO1 L1
a) Binary addition b) Hexadecimal addition
c) Decimal addition d) Subtraction
7. A magnitude comparator compares: CO1 L1
a) Two AND gates b) Two OR gates
c) Two numbers d) Two flip-flops
8. An encoder performs the function of: CO1 L1
a) Converting decimal to binary b) Converting 2ⁿ inputs to n outputs
c) Shifting data d) Multiplying numbers
9. The truth table of a 2-input OR gate has how many rows? CO1 L2
a) 1 b) 2
c) 4 d) 8
10. Demultiplexers are used to: CO1 L1
a) Encode data b) Route a single input to multiple outputs
c) Compare numbers d) Generate clock
UNIT II
1. A flip-flop is used to: CO2 L2
a) Perform addition b) Compare numbers
1 | Page
c) Store 1 bit of data d) Simplify Boolean expressions
2. A clocked flip-flop changes its state: CO2 L2
a) Any time b) On clock edge
c) Only on reset d) Only on input high
3. A JK flip-flop avoids: CO2 L1
a) Input b) Race condition
c) Output d) Clock
4. A D flip-flop stores: CO2 L1
a) Multiple bits b) 1 bit at a time
c) 2 bits d) 4 bits
5. The excitation table of T flip-flop shows: CO2 L1
a) Output function b) Required inputs for state change
c) Clock function d) Timing diagram
6. Moore machine output depends on: CO2 L1
a) Current state only b) Input only
c) Both input and current state d) Clock
7. Mealy machine output depends on: CO2 L1
a) Current state only b) Input and current state
c) Clock only d) Previous state only
8. State minimization reduces: CO2 L1
a) Inputs b) Outputs
c) Number of states d) Flip-flops
9. A register is used to: CO2 L2
a) Generate clock b) Store multiple bits
c) Compare numbers d) Add numbers
10. Asynchronous counters are triggered by: CO2 L1
a) Input signals b) Control signals
c) Previous flip-flop output d) Clock only
UNIT III
1. The main memory in a Von Neumann machine stores: CO3 L2
a) Only instructions b) Only data
c) Both instructions and data d) Only addresses
2. The CPU consists of: CO3 L2
a) ALU, Control Unit, and Registers b) Only ALU
c) Only Control Unit d) Input/output devices
3. Instruction sequencing is handled by: CO3 L1
a) ALU b) Control Unit
c) Registers d) Cache
4. In Von Neumann architecture, program and data share: CO3 L1
a) Same memory b) Different memory
c) Same ALU d) None
5. Operand is: CO3 L1
a) A control signal b) Data on which operation is performed
c) Clock signal d) Instruction
6. An instruction set defines: CO3 L1
a) Operations that CPU can perform b) Clock cycles
2 | Page
c) Memory size d) Input/output devices
7. Immediate addressing mode uses: CO3 L1
a) Operand is part of the instruction b) Operand is in memory
c) Operand in register d) None
8. Register addressing mode accesses: CO3 L1
a) Main memory b) CPU register
c) Cache only d) ALU only
9. Direct addressing uses: CO3 L2
a) Indirect pointer b) Explicit memory address
c) Register value d) ALU output
10. Encoding of machine instruction is necessary for: CO3 L1
a) Logic simplification b) CPU understanding
c) Register design d) Input/output control
UNIT IV
1. Instruction execution begins with: CO4 L2
a) Fetching the instruction b) Decoding the instruction
c) Executing operation d) Writing back
2. Data path consists of: CO4 L2
a) ALU only b) Registers, ALU, and buses
c) Control Unit only d) Memory only
3. Control unit generates: CO4 L1
a) Operand b) Control signals
c) Registers d) Clock
4. Hardwired control is: CO4 L1
a) Fixed logic using combinational b) Software-based
circuits
c) Flexible control d) Microprogrammed
5. Microprogrammed control uses: CO4 L1
a) Logic gates b) Stored sequences of microinstructions
c) Only registers d) Only ALU
6. Pipelining improves: CO4 L1
a) CPU throughput b) Memory size
c) Instruction set d) Register count
7. Data hazard occurs when: CO4 L1
a) Control signals are delayed b) Instruction depends on previous instruction result
c) Memory fails d) Clock is low
8. Control hazard arises due to: CO4 L1
a) Register conflict b) Branch instructions
c) ALU delay d) Cache miss
9. Stalling in pipeline is used to: CO4 L2
a) Resolve hazards b) Increase memory
c) Reduce ALU operations d) Simplify control
10. Forwarding in pipeline avoids: CO4 L1
a) Control hazard b) Data hazard
c) Clock hazard d) None
3 | Page
UNIT V
1. Memory hierarchy places which memory closest to CPU? CO5 L2
a) Hard disk b) Main memory
c) Cache d) Registers
2. Cache memory improves: CO5 L2
a) Access time b) CPU size
c) Instruction set d) Bus width
3. Direct mapping in cache uses: CO5 L1
a) Multiple locations b) Single location for each block
c) Fully associative d) Random
4. Replacement policy “LRU” stands for: CO5 L1
a) Least Recently Used b) Last Register Update
c) Logical RAM Unit d) Low Register Usage
5. Virtual memory allows: CO5 L1
a) Faster CPU b) Larger apparent memory using disk
c) Reduced ALU operations d) Only cache access
6. Parallel I/O transfers: CO5 L1
a) Multiple bits simultaneously b) One bit at a time
c) Only instructions d) Only control signals
7. Serial I/O transfers: CO5 L1
a) Multiple bits b) One bit at a time
c) Registers only d) Cache only
8. Interrupt I/O allows CPU to: CO5 L1
a) Poll devices continuously b) Respond only when device signals
c) Ignore devices d) Only fetch memory
9. USB is an example of: CO5 L2
a) Serial interface b) Parallel interface
c) Memory d) Cache
10. SATA is used for: CO5 L1
a) CPU control b) Storage interface
c) Memory mapping d) ALU operations
2 Marks Questions
UNIT I
[Link] Questions CO BTL
1. How many bits are required to represent the decimal numbers in the range 0 CO1 L1
to 999 using straight binary code? Using BCD codes?
2. Given 2 binary numbers. X = 1010100 and Y = 1000011. Find X –Y and Y – CO1 L1
X using 2’s compliments
3. Design the combinational circuit with 3 inputs and 1 output. The output is 1 CO1 L2
when the binary value of the input is less than 3
4. What is magnitude comparator? CO1 L1
5. What is a priority encoder CO1 L1
6. Define Combinational circuit CO1 L2
4 | Page
UNIT II
1. What is meant by triggering of Flip flop? CO2 L1
2. Define race around condition. CO2 L2
3. Mention the different types of shift register. CO2 L1
4. Differentiate between Moore and Mealy models with one example. CO2 L1
5. How to minimize the states for a sequential circuit. CO2 L2
6. Draw the block diagram of a 4-bit shift register and mention its applications. CO2 L1
UNIT III
1. Define the basic functional units of a digital computer. CO3 L1
2. Draw and explain Von Neumann architecture. CO3 L1
3. Differentiate between instruction and operand with example. CO3 L2
4. List various addressing modes. CO3 L1
5. A computer uses 16-bit addresses. How many memory locations are CO3 L1
possible?
6. Compare assembly language and high-level language instructions. CO3 L2
UNIT IV
1. Differentiate between hardwired and microprogrammed control. CO4 L1
2. Draw a simple data path for a processor and explain. CO4 L1
3. Compare hardwired and microprogrammed control. CO4 L2
4. Define pipelining. CO4 L1
5. What is a data hazard? CO4 L1
6. Define control hazards and pipeline stalling. CO4 L2
UNIT V
1. What is memory hierarchy? CO5 L1
2. Define cache memory. CO5 L1
3. What is virtual memory? CO5 L2
4. Compare parallel and serial I/O. CO5 L1
5. What is DMA? CO5 L1
6. Differentiate interrupt-driven I/O and polling. CO5 L1
14 Marks Questions
UNIT I
[Link] Questions CO BTL
1. Design a combinational circuit that takes two 2-bit numbers and outputs their CO1 L2
sum and difference.
2. Explain the steps for designing a combinational circuit using K-map CO1 L2
simplification with an example.
5 | Page
3. Design a 3-to-8 decoder and explain how it can be used in memory selection. CO1 L3
4. Implement a BCD adder circuit and explain its operation using logic gates. CO1 L3
UNIT II
1. Design a clocked sequential circuit using JK flip-flops for a given sequence. CO2 L2
2. Compare synchronous and asynchronous counters with timing diagrams. CO2 L2
3. Design a Moore machine for a given sequence detector problem. CO2 L2
4. Explain the design steps of a Mealy machine with an example. CO2 L2
UNIT III
1. Explain the operation of a digital computer with functional units and instruction CO3 L2
flow.
2. Describe memory locations, addressing modes, and encoding of machine CO3 L3
instructions.
3. Explain the interaction between assembly language and high-level language CO3 L2
with examples.
4. Analyze a sample program and illustrate instruction execution in a Von CO3 L3
Neumann machine.
UNIT IV
1. Design a data path for a simple processor and explain its operation. CO4 L2
2. Explain the steps for designing a control unit (hardwired vs microprogrammed). CO4 L3
3. Illustrate pipelining, hazards, and techniques to improve throughput. CO4 L2
4. Analyze a sequence of instructions in a pipelined processor and explain hazard CO4 L3
handling.
UNIT V
1. Explain memory management, hierarchy, and cache replacement techniques. CO5 L2
2. Design an I/O system using parallel and serial interfaces. CO5 L3
3. Describe virtual memory implementation and address translation. CO5 L2
4. Explain DMA operation and interrupt I/O with examples. CO5 L3
Course Instructor Dept IQAC HOD
6 | Page