MAHARASHTRA STATE BOARD OF

TECHNICAL EDUCATION

NAVJEEVAN EDUCATION SOCIETY’S

POLYTECHNIC

MICRO PROJECT

Academic year: 2021-22

TITLE OF MICRO PROJECT

FULL ADDER .

Program: Computer Engineering.

Program code: CO3I
Course: Digital Techniques.
Course code: 22320.
 MAHARASHTRA STATE
BOARD OF TECHNICAL EDUCATION
Certificate
This is to certify that 1. Chaitanya Shivram Mestry (1204) .
2. Mohit Anil Jangale (1205).

of 3rd Semester of Diploma in Computer Engineering of Institute,

Navjeevan Education Society’s Polytechnic(Code: 0144) has
completed the Micro Project satisfactorily in Subject: Digital
Techniques (22320) for the academic year 2021- 2022 as prescribed in
the curriculum.

Place: Bhandup. Enrollment no:-1. 2001440084.

2. 2001440085.

Date:-……………………….. Exam Seat no:- 1. 108979 .

2. 108980 .

Subject Teacher Head of the Department Principal

 FULL ADDER
REPORT BOOKLET

NAVJEEVAN POLYTECHNIC

BHANDUP [W]
 GROUP DETAILS
SR. Name of Group Roll Enrollment
Seat no
NO Members no No
1. Chaitanya S. Mestry 1204 2001440084 108979

2. Mohit A. Jangale 1205 2001440085 108980

HELPED AND GUIDED BY

MR. HARSHAD AWATE .

  Weekly Progress Report(Action Plan) Micro-Project:-
Topic: Full Adder .
Academic Year: 2021-2022 Name of Faculty: Mr. Harshad Awate.
Program Code: Computer Engineering (CO3I).
Course & Course Code: Digital Techniques (22320).
RollNo: 1204, 1205 EnrollmentNo: 2001440084, 2001440085 .
Semester: III Name of Candidate: Chaitanya S Mestry, Mohit A Jangale.

SR Week Activity of Performed Planned Planned Name of Responsible

.N start Date Finish Date Team member
O

1. Discussion and finalization

1st All Team Members
of topic
2. Preparation and
2nd All Team Members
submission of Abstract
3.
3th Collection of Data All Team Members
4.
4th Implementation
All Team Members
5. Check, Validation and
5th All Team Members
Execution of code
6.
Compilation of Report
6th All Team Members
And Presentation
7. 7th Actual Presentation &
Final submission of All Team Members
Micro Project

Sign of the Student:-

1) 2)

Sign of the Faculty

 INDEX

Topic: Full Adder .

Academic Year: 2021-2022 Name of Faculty: Mr. Harshad Awate.
Program Code: Computer Engineering (CO3I).
Course & Course Code: Digital Techniques (22320).
Roll No: 1204, 1205 Enrollment No: 2001440084, 2001440085 .
Semester: III
Name of Candidate: Chaitanya S Mestry, Mohit A Jangale.

[Link] CONTENT PAGE NO

1. Brief Description 1

2. Course Outcomes Integrated 1

3. Concept of Full Adder 1

4. Circuit Diagram and Block Diagram 2-3

5. Truth Table 4-14

6. Example of Full Adder 15-23

7. Micro-Project Evaluation Sheet /Annexure IV 24-25

 Full Adder
1. Brief Description:-
A full adder is a digital circuit that performs addition. Full adders are implemented
with logic gates in hardware. A full adder adds three one-bit binary numbers, two
operands and a carry bit. The adder outputs two numbers, a sum and a carry bit. The term
is contrasted with a half adder, which adds two binary digits.

2. Course Outcomes Integrated:-

a) Use Number System and codes for interpreting working of digital system .
b) Use boolean expressions to realize logic circuits .
c) Build simple combinational circuits .
d) Built simple sequential circuits.
e) Test data converters and PLDs in digital electronics systems.

3. Concept of Full Adder :-

A full adder takes two binary numbers plus a carry or overflow bit. The output is a
sum and another carry bit. Full adders are made from XOR, AND and OR gates in
hardware. Full adders are commonly connected to each other to add bits to an arbitrary
length of bits, such as 32 or 64 bits. A full adder is effectively two half adders, an XOR
and an AND gate, connected by an OR gate.

1
 Block Diagram :-

The actual logic circuit of the full adder is shown in the above diagram.

The full adder circuit construction can also be represented in a Boolean expression.

SUM:
o Perform the XOR operation of input A and B.
o Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B) XOR
Cin which is also represented as:
(A ⊕ B) ⊕ Cin

Carry:

1. Perform the 'AND' operation of input A and B.

2. Perform the 'XOR' operation of input A and B.
3. Perform the 'OR' operations of both the outputs that come from the previous two steps. So the
'Carry' can be represented as:
A.B + (A ⊕ B)

2
 Circuit Diagram :-

The above Circuit diagram describes the construction of the Full adder
circuit.

In the above circuit, there are two half adder circuits that are combined
using the OR gate. The first half adder has two single-bit binary inputs A and B.
As we know that, the half adder produces two outputs, i.e., Sum and Carry. The
'Sum' output of the first adder will be the first input of the second half adder,
and the 'Carry' output of the first adder will be the second input of the second
half adder. The second half adder will again provide 'Sum' and 'Carry'.

The final outcome of the Full adder circuit is the 'Sum' bit. In order to
find the final output of the 'Carry', we provide the 'Carry' output of the first and
the second adder into the OR gate. The outcome of the OR gate will be the final
carry out of the full adder circuit. The MSB is represented by the final 'Carry'
bit. The full adder logic circuit can be constructed using the 'AND' and the
'XOR' gate with an OR gate

3
 Truth Table :-

In the above table,

1. A' and' B' are the input variables. These variables represent the two significant bits
which are going to be added
2. 'Cin' is the third input which represents the carry. From the previous lower significant
position, the carry bit is fetched.
3. The 'Sum' and 'Carry' are the output variables that define the output values.
4. The eight rows under the input variable designate all possible combinations of 0 and 1
that can occur in these variables.

4
 The difference between a half-adder and a full-adder is that the full-adder has
three inputs and two outputs, whereas half adder has only two inputs and two outputs.
The first two inputs are A and B and the third input is an input carry as C-IN. When a
full-adder logic is designed, you string eight of them together to create a byte-wide
adder and cascade the carry bit from one adder to the next.

The output carry is designated as C-OUT and the normal output is represented
as S which is ‘SUM’.

With the above full adder truth-table, the implementation of a full adder circuit
can be understood easily. The SUM ‘S’ is produced in two steps:

By XORing the provided inputs ‘A’ and ‘B’

The result of A XOR B is then XORed with the C-IN

This generates SUM and C-OUT is true only when either two of three inputs
are HIGH, then the C-OUT will be HIGH. So, we can implement a full adder circuit
with the help of two half adder circuits. Initially, the half adder will be used to add A
and B to produce a partial Sum and a second-half adder logic can be used to add C-IN
to the Sum produced by the first half adder to get the final S output.

If any of the half adder logic produces a carry, there will be an output carry.
So, C-OUT will be an OR function of the half-adder Carry outputs. Take a look at the
implementation of the full adder circuit shown below.

5
 Full Adder Logical Diagram

The implementation of larger logic diagrams is possible with the above

full adder logic a simpler symbol is mostly used to represent the operation.
Given below is a simpler schematic representation of a one-bit full adder.

With this type of symbol, we can add two bits together, taking a carry
from the next lower order of magnitude, and sending a carry to the next higher
order of magnitude. In a computer, for a multi-bit operation, each bit must be
represented by a full adder and must be added simultaneously. Thus, to add two
8-bit numbers, you will need 8 full adders which can be formed by cascading
two of the 4-bit blocks.

6
 The full adder K-Map is

FA K-Map

Logical Expression of SUM and Carry

The logical expression of sum (S) can be determined based on the inputs
mentioned in the table.

= A’B’Cin + A’ B CCin’ + A B’Cin’+ AB Cin

= Cin (A’B’+ AB) + Cin’ (A’B +A B’)
= Cin EX-OR (A EX-OR B)
= (1,2,4,7)

7
 The logical expression of the carry (Cout) can be determined based on
the inputs mentioned in the table.

= A’B Cin + AB’Cin + AB Cin’ + ABCin

= AB + BCin + ACin
= (3, 5, 6, 7)

With the above-mentioned truth tables, the results can be obtained and
the procedure is :

A combinational circuit combines the different gates in the circuit where

those can be an encoder, decoder, multiplexer and demultiplexer. The
characteristics of combinational circuits are as follows.

The output at any instant of time is based only on the levels that are
present at input terminals.

It does not use any memory. The previous state of input does not have
any effect on the present state of the circuit.

It can have any number of inputs and m number of outputs.

VHDL Coding

VHDL coding for full adder include the following.

entity full_add is

Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC);
end full_add;

8
 Architecture Behavioral of full_add is

component ha is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
sha : out STD_LOGIC;
cha : out STD_LOGIC);
end component;
signal s_s,c1,c2: STD_LOGIC ;
begin
HA1:ha port map(a,b,s_s,c1);
HA2:ha port map (s_s,cin,sum,c2);
cout<=c1 or c2 ;
end Behavioral;

The difference between half adder and full adder is that half adder produces
results and full adder uses half adder to produce some other result. Similarly, while the
Full-Adder is of two Half-Adders, the Full-Adder is the actual block that we use to
create the arithmetic circuits.

Carry Lookahead Adders

In the concept of ripple carry adder circuits, the bits that are necessary for
addition are immediately available. Whereas every adder section needs to hold its time
for the arrival of carry from the previous adder block. Because of this, it takes more
time to produce SUM and CARRY as each section in the circuit waits for the arrival
of input.

For instance, to deliver output for the nth block, it needs to receive input from
(n-1)th block. And this delay is correspondingly termed as propagation delay.

To overcome the delay in ripple carries adder, a carry-lookahead adder was

introduced. Here, by using complicated hardware, the propagation delay can be
minimized. The below diagram shows a carry-lookahead adder using full adders.

9
 The Half-Adder is a basic building block of adding two numbers as two
inputs and produce out two outputs. The adder is used to perform OR operation
of two single bit binary numbers. The augent and addent bits are two input
states, and 'carry' and 'sum 'are two output states of the half adder.

Block diagram

Truth Table

In the above table,

'A' and' B' are the input states, and 'sum' and 'carry' are the output states.

10
 The carry output is 0 in case where both the inputs are not 1.

The least significant bit of the sum is defined by the 'sum' bit.

The SOP form of the sum and carry are as follows:

Sum = x'y+xy'
Carry = xy

Construction of Half Adder Circuit:

In the block diagram, we have seen that it contains two inputs and two
outputs. The augent and addent bits are the input states, and carry and sum are
the output states of the half adder. The half adder is designed with the help of
the following two logic gates:

2-input AND Gate.

2-input Exclusive-OR Gate or Ex-OR Gate

1. 2-input Exclusive-OR Gate or Ex-OR Gate

The Sum bit is generated with the help of the Exclusive-OR or Ex-
OR Gate.

11
 The above is the symbol of the EX-OR gate. In the above diagram, 'A' and
'B' are the inputs, and the 'SUMOUT' is the final outcome after performing the
XOR operation of both numbers.

The truth table of the EX-OR gate is as follows:

From the above table, it is clear that the XOR gate gives the result 1 when both
of the inputs are different. When both of the inputs are the same, the XOR gives the
result 0.

12
 2. 2-input AND Gate:

The XOR gate is unable to generate the carry bit. For this purpose, we use
another gate called AND Gate. The AND gate gives the correct result of the
carry.

The above is the symbol of the AND gate. In the above diagram, 'A' and
'B' are the inputs, and 'OUT' is the final outcome after performing AND
operation of both numbers.

There is the following truth table of AND Gate:

From the above table, it is clear that the AND gate gives the result 1 when
both of the inputs are 1. When both of the inputs are different and 0, the AND
gates gives the result 0. To learn more about the AND gate, click here.

13
 Half-Adder logical circuit:

So, the Half Adder is designed by combining the 'XOR' and 'AND' gates
and provide the sum and carry.

There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B (A+B)

Carry= A AND B (A.B)

14
 Example of Full Adder :-

1. 74LS83 4-bit Full Adder IC

The 74LS83 is a high speed 4-bit fuller Adder IC with carry out feature. The
IC has four independent stages of full adder circuits in a single package. It is
commonly used in applications where arithmetic operations are involved.

15
 74LS83 Pin Configuration

Pin Number Pin Name Description

10,8,3,1 A1,A2,A3,A4 First Input for the adder circuit (Four pin for four
stages)
11,7,4,16 B1,B2,B3,B4 Second Input for the adder circuit (Four pin for
four stages)
13 C0 Carry Input - from previous stage if present.
9,6,2,15 S1,S2,S3,S4 Output pin for the Adder circuit (Four pin for
four stages)
14 C4 Carry Out pin to cascade with other ICs.

Specifications – 74LS83

 4-bit Full Adder with Carry Out

 Nominal Operating Voltage: 5V
 Maximum Operating Voltage: 5.5V
 Output Propagation delay: 16nS
 Maximum Input Low Voltage: 0.8V
 Minimum Input High Voltage: 2V
 Available in 16-pin PDIP, CDIP,SOIC, TSSOP packages

Where to use 74LS83 IC

Although today we have cheap microcontrollers that could perform all arithmetic

operations required for our application, in early days the ICs like Adder, Counter, flip-

flops etc were used for same. This way the complexity and the BOM cost of the circuit

design will greatly go low.

The 74LS83 is a Full Adder with Carry in and Carry out feature. It is a four stage 4-bit

counter, meaning it has four individual Full adder circuits each of 4-bit inside a single

package. It can also be easily cascaded if more than four stages are required.

16
How to use a 74LS83 Full Adder IC

Using the Full Adder IC is pretty much straight forward. The IC has four different

stages and each stage has two normal inputs Ax and Bx with an additional carry input

called C1. Based on the values provided to these pins the output Sx will either be high

(logic 1) or low (logic 0). The IC also has a Carry Out (CO) pin which will go high if the

result has an carry. The block diagram below represents the same.

Each Full adder stage will obey the truth table below. Where Ai, Bi and Ci are the input

and SUM, Co are the outputs.

17
 Let’s understand a bit more about this IC by using a simulation. The below image and
video shows the IC being simulated for all four stages by clubbing in the four input pins
of both A and B. This way we can verify the truth table.

Applications

 High Speed Arithmetic operations

 Miniature calculators
 Counters
 Simple logic control designs

2D Model of 74LS83 (PDIP)

18
 2. CD4008 4-Bit Full ADDER IC

CD4008 4-bit full adder integrated circuit used for binary addition. Binary
addition is the base of every function performed in most of the smart machines.
It is easy to make a two-bit adder using two simple logic gates. A two-bit adder
circuit can be made just by using XOR and AND gate. It comes up with two
inputs and two outputs. The two bits are only applicable to add two bits, to make
full adder we can use two half adders but after simplifies the combination of
half adder circuit a full adder circuit was designed.

Full Adder is made of one OR, two XOR and one AND gate. It has three
inputs and two outputs. The First two inputs use as two input data bits and the
third input is used as carrying bit, which we have no further use in half adder
circuit. The output carries a bit on full adder circuit transfer the carry bit to the
next adder and it performs the addition by considering three input values.

19
Introduction to CD4008 4-Bit Full ADDER CIRCUIT

The multiple full adders could be used as a multiple bit adder

circuits. CD4008 IC is a full 4-bit adder circuit which comes up with a
combination for four full bit adders. It could add four multiple bits without any
error. It carries a bit from state to stage and perform the addition. CD4008 is one
the fastest and high voltage adder circuit with carrying out feature.
Pinout of CD4008

The pin configuration and details of all input outputs pins are
listed below:

20
PIN CONFIGURATION CD4008 4-Bit Full ADDER

PIN
DETAILS
S

Pin 1 will be used by the

first bit of 4-bits input data
A4 Pin 1
A of full adder. It could
either be 1 or 0.

Pin 2 will be used by the

B3 Pin 2 2nd bit of 4-bits input data
B.

Pin 3 will be used by the

A3 Pin 3
2nd bit of 4-bits input data.

The third bit of 4-bits input

B2 Pin 4 data B will be given as
input on Pin 4.

The third bit of 4-bits input

A2 Pin 5 data A will be given as
input on Pin 5.

The last bit of 4-bit data B

B1 Pin 6
will be input at pin 6.

The last bit of 4-bit input

A1 Pin 7 data A will be input at Pin
7.

VSS Pin 8 CD4008 is a logic-based

device. It will be required
power to turn on or we can
say to it will require
Ground to operate with
other devices. VSS pin will
be used as Common

21
 Ground.

C1 will be the carry input

bit of the first adder in IC,
C1 Pin 9
which will be given on pin
9.

The last bit of the added

S1 Pin 10
value will be out at Pin 10.

Pin 11 will represent the

S2 Pin 11 3rd output bit of the added
value.

Pin 12 will be used for

S3 Pin 12
2nd output bit.

First output bit will be

S4 Pin 13
received at Pin 13.

Last carryout bit will be at

CO Pin 14
Pin 14.

Pin 15 will be used by the

B4 Pin 15 first bit of 4-bit input data
B

VD VDD will be used as power

Pin 16
D input.

22
FEATURES of CD4008 4-Bit Full ADDER IC

1. 4-bit full adder with carrying out features

2. Parallel input and output method
3. High operating speed without any interruptions
4. Available with 16-pins in PDIP, CDIP, SOIC, and TSSOP Package
5. Meets all the requirements of all CMOS devices.
6. It has HIGH operating voltage as compared to most of the other CMOS
devices.

SPECIFICATIONS of CD4008

1. The total time required for values from input to output is 160ns.
2. It has a noise margin at different voltages
3. 5V margin will be about 1V.
4. 10-volt margin will be about 2V.
5. 15 Volt margins will be about 2.5V
6. CD4008 normal operating voltage rages are 5- 15V, it could operate also
maximum at 20V
7. Maximum input current should be 1uA at 18V.
8. The temperature should be 25 degrees at 18V and 1uA
9. Most of the specifications and features only work when IC is operation at
exact 5V.

23
 Micro Project Evaluation Sheet

Name of Student: Chaitanya S. Mestry Enrollment No : 2001440084

Name of Programme : Computer Engineering Semester : III.

Course Title: Digital Techniques. Code : 22320.

Title of Micro Project : Full Adder.
Course Outcomes Achieved:
a) Use Number System and codes for interpreting working of digital system .
b) Use boolean expressions to realize logic circuits .
c) Build simple combinational circuits .
d) Built simple sequential circuits.
e) Test data converters and PLDs in digital electronics systems.

Sr.n Characteristic Poor(Mar Average(Ma Good(Mar Excellent(Ma Sub

o to be ks 1-3) rks 4 - 5) ks 6-8 ) rks 9-10) Total
assessed
(A)Process and Product Assessment(Convert above total marks out of 6 marks.)
1. Relevance to the
Course
2. Literature
Review/information
collection
3. Completion of the
target as per project
proposal
4. Analysis of data and
representation
5. Quality of
Prototype/Model
6. Report Preparation.
(B) Individual Presentation/Viva (Convert above marks Total Marks out of 4)
7. Presentation
8. Viva

(A) (B) Total Marks 10

Process and Product Individual
Assessment (6 marks) Presentation/Viva(4
marks)

Comments/Suggestions about team [Link]/inter-personal communication

……………………………………………………………………………………
Name and designation of the Teacher …………………………………………….

24
 Dated Signature …………………………………………….

Micro Project Evaluation Sheet

Name of Student: Mohit A. Jangale Enrollment No : 2001440085

Name of Programme : Computer Engineering Semester : III.

Course Title: Digital Techniques. Code : 22320.

Title of Micro Project : Full Adder.
Course Outcomes Achieved:
a) Use Number System and codes for interpreting working of digital system .
b) Use boolean expressions to realize logic circuits .
c) Build simple combinational circuits .
d) Built simple sequential circuits.
e) Test data converters and PLDs in digital electronics systems.

Sr.n Characteristic Poor(Mar Average(Ma Good(Mar Excellent(Ma Sub

o to be ks 1-3) rks 4 - 5) ks 6-8 ) rks 9-10) Total
assessed
(A)Process and Product Assessment(Convert above total marks out of 6 marks.)
1. Relevance to the
Course
2. Literature
Review/information
collection
3. Completion of the
target as per project
proposal
4. Analysis of data and
representation
5. Quality of
Prototype/Model
6. Report Preparation.
(B) Individual Presentation/Viva (Convert above marks Total Marks out of 4)
7. Presentation
8. Viva

(A) (B) Total Marks 10

Process and Product Individual
Assessment (6 marks) Presentation/Viva(4
marks)

Comments/Suggestions about team [Link]/inter-personal communication

……………………………………………………………………………………

25
Name and designation of the Teacher …………………………………………… .
Dated Signature …………………………………………….

26