2016 Online International Conference on Green Engineering and Technologies (IC-GET)

Design of Comparator Using Domino Logic and

CMOS Logic

Abhishek V. Rangari Yashika A. Gaidhani

Yeshwantrao Chavan College of Engineering Yeshwantrao Chavan College of Engineering
Nagpur, India Nagpur, India
abhirangari007@[Link] shweta29gaidhani@[Link]

Abstract— This paper presents implementation of 4 bit

comparator circuit using Domino Logic (High speed Domino)
and CMOS Logic. In CMOS Logic during inverter circuit
operation when voltage level shifts from high to low and vice
versa short circuit current occurs which leads to power loss. So
Domino Logic is one of the power saving technique which helps
to avoid this short circuit current and saves power consumption.
So in this paper we have made a comparative analysis between
the Domino logic and the CMOS logic for which we have used
comparator as our reference circuit. As Domino Logic is well
known for its power saving technique so the main parameter
which we have considered in this paper is power. We also tried to
fetch power consumption at different voltage level (voltage
scaling) and at least 55% of power is saved by Domino Logic as
compared to that of CMOS circuits. In this paper Generic 0.25u
technology is used and EDA (Tanner tool version 16) is used to
implement the circuit and for simulation purpose.

Index Terms— Domino Logic, CMOS comparator, HSD Fig. 1. VI characteristics of CMOS inverter
comparator, Voltage scaling, Power saving mechanism.
Precharge transistor is PMOS which connects pull down
network to the main supply Vdd and evaluation transistor is
I. INTRODUCTION NMOS which connects pull down network to the ground. In
precharge phase circuit makes itself ready for the operation
The major problem with CMOS circuits is power loss and in evaluation phase the evaluation of final results will be
during its operation. This power loss is mostly because of the there which will generate appropriate outputs. So in Domino
short circuit current occurs during the switching of voltage logic there is no chance that the Vdd and ground can create
level rom high to low and vice versa. This short circuit current short circuit even for small amount of time because they are
occurs for small amount of time and when the supply voltage working in two different phases [2] [10].
Vs or Vdd meets the Ground during switching period of
voltage. As this switching state is not able to specify any logic
level and hence the current which flows through the circuit is
not of any use. So because of unnecessary flow of current
leads to power loss and this is unwanted. Hence the current
which is generated during short circuit is called as short circuit
current. From Fig.1 we can analyze this situation. That is the
main drawback of circuits which are implemented using
CMOS logic. So to get rid of this short circuit current and
power loss we can use such logic which is capable of saving
power by removing the short circuit current effect. So we can
go for Domino Logic which can fulfill the criteria of power
saving. In this paper we have used high speed domino
Fig. 2. Block diagram of basic Domino Logic
technology which is one of the types of Domino technology
[1]. Domino logic works in two phases as we can see in Fig. 2 Domino logic is a type of Dynamic logic which requires
i.e. precharge phase and evaluation phase. For this precharge clock for its proper functioning. During negative clock cycle
transistor and evaluation transistors are used. precharge phase comes into consideration where pull down

978-1-5090-4556-3/16/$31.00 ©2016 IEEE

 2016 Online International Conference on Green Engineering and Technologies (IC-GET)

network will get connected to Vdd and capacitor will get will be of 4 bits and hence A will vary from 0 to 15 which will
charged to the same level to that of Vdd or Vs. Then at get compared to B and for simplicity purpose we have
positive clock the time of evaluation phase comes where pull assigned a fix value to B i.e. 8(1000) as shown in Table I.
down network will get connected to ground and when
functionality of circuit will gets satisfied at that time the
capacitor will get discharged through ground. This is how
proper output will be generated without any short circuit
current and hence the power loss will be much more less than
that of CMOS logic circuit. In our case the pull down network
is 4 bit Comparator circuit [3].

II. COMPARATOR DESIGN AND ITS SIMULATION

Comparator plays an important role in many central

processing units and microprocessors and its main function is
to find the logical relationship between two input signals i.e. Fig. 4. 4 bit CMOS comparator
whether first signal is equal or greater or smaller than the
second input signal. Another function of comparator is to find Table I also shows truth table for our designed 4 bit
out OOO (out of order) execution. As our main reference comparator and the expected outputs. Now we have used
circuit is comparator and we have designed the 4 bit Tanner tools version 16 to verify the truth table. Fig.6 show
comparator using Domino Logic and CMOS logic as well so input waveforms A and B and then Fig. 7 shows the final
to implement 4 bit comparator we stared with 1 bit comparator output waveform where for first eight combinations of A i.e.
as in 4 bit comparator circuit 1 bit comparator is also required. from 0-7 A is less than B(8). For next sequence A will be
Fig.3 shows circuit of 1 bit comparator. At the output side we equal to B and then for remaining combinations A will be
have A=B (A equals to B), A<B (A less than B), A>B (A greater than B. From Fig. 7 we verified those results and it is
greater than B). After designing and understanding this one bit satisfying the truth table.
comparator in a proper manner we can go for 4 bit comparator
directly where four 1 bit comparators will be required to run
the circuit in an ideal way [4].

Fig. 3. 1 bit comparator circuit

A. 4 bit CMOS comparator

As we are implementing this 4 bit comparator circuit
using CMOS logic hence there is no need to provide clock to
the circuitry. Fig. 4 shows CMOS 4 bit comparator. Here we
are keeping the W/L ratio 10 which is fixed and number of
transistors required are 238. As we can see in the Fig.4 both
the inputs A and B are of 4 bits i.e. A3-A0 and B3-B0. The Fig. 5. Internal architecture of 4 bit comparator
internal architecture of 4 bit comparator circuit is shown in
Fig. 5. As we knows it is an 4 bit comparator hence each input
 2016 Online International Conference on Green Engineering and Technologies (IC-GET)

As we can see in Fig.6 A is varying from 0 to 15 and B

remains constant which is 8. From Fig.7 we can verify the
truth table. As we can see from Fig.7 the results are exactly
according to that of truth table which shows that our circuit is
working properly.

Table I. Truth table for 4 bit comparator

A3 A2 A1 A0 B3 B2 B1 B0 AEB ALB AGB

0 0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 0 1 0
0 0 1 0 1 0 0 0 0 1 0
0 0 1 1 1 0 0 0 0 1 0
0 1 0 0 1 0 0 0 0 1 0
0 1 0 1 1 0 0 0 0 1 0
0 1 1 0 1 0 0 0 0 1 0
0 1 1 1 1 0 0 0 0 1 0
1 0 0 0 1 0 0 0 1 0 0
1 0 0 1 1 0 0 0 0 0 1
1 0 1 0 1 0 0 0 0 0 1
1 0 1 1 1 0 0 0 0 0 1
1 1 0 0 1 0 0 0 0 0 1
1 1 0 1 1 0 0 0 0 0 1
1 1 1 0 1 0 0 0 0 0 1
1 1 1 1 1 0 0 0 0 0 1 Fig. 7. CMOS 4 bit comparator results

B. 4 bit HSD Comparator

As we are using Domino logic as the second method with
which we are going to design the 4 bit comparator circuit and
there are several types of Domino Logic from which we are
using High Speed Domino for our operation and the
comparative analysis will also in between CMOS comparator
and HSD comparator. Here also the W/L ratio will remain
same i.e. 10 as in CMOS comparator and number of
transistors required are 551. Here we will follow the same
truth table given in Table I. Here Fig.8 shows the basic HSD
model and Fig. 9 shows the 4 bit HSD comparator [5] [6] [7].

Fig. 6. Input waveforms of CMOS comparator

Fig. 8. Basic HSD model
 2016 Online International Conference on Green Engineering and Technologies (IC-GET)

This is the basic circuit arrangement of High Speed

Domino technique which we have used to implement the 4 bit
comparator circuit.

Fig. 11. Clock waveform required for HSD comparator

Fig. 9. 4 bit HSD comparator

As we knows that Domino logic generates output only at
evaluation phase and hence we can observe the output for only
As we can see in Fig.9 to drive a 4 bit comparator half clock cycle which will be for evaluation phase and for
circuit using Domino logic we need a clock generator circuit precharge phase circuit will not indicate any output pulse. So
and n number of clocks where n is number of cascaded stages. we can verify the truth table given in Table I from the output
Fig.10 shows the internal structure of 4 bit HSD comparator. waveform.
Here numbers of cascaded stages are 5 hence total clocks Fig.12 shows the output waveform for 4 bit HSD comparator
required will be 5. Again the input waveform will remain circuit and output waveforms are satisfying the truth table of
same as in CMOS 4 bit comparator shown by Fig.6. As we are comparator circuit.
dealing with Domino logic and hence to show the clock
waveform is necessary. Fig.11 shows the clock waveform
required in HSD comparator circuit. Here the proper
synchronization of clock is required so that the circuit can
work properly and can generate the required output.

Fig. 12. Output waveform for 4 bit HSD comparator

As from figure we can say that circuit is working fine and

satisfying the comparator characteristics. Here both CMOS
comparator and HSD comparator worked fine on 1V, 3V and
5V and for each level of voltage supply we find power
required and frequency supported by both the CMOS
comparator and Domino comparator.

III. COMPARATIVE ANALYSIS

Here in this paper we have considered several parameters

which we will use for a comparative analysis between the
Fig. 10. Internal structure of 4 bit HSD comparator
CMOS comparator and the HSD comparator and those
 2016 Online International Conference on Green Engineering and Technologies (IC-GET)

parameters are power, frequency, transistors required, voltage respectively. So we can say that Domino logic is better for
scaling and technology [8] [9]. Here the technology is fixed power saving and CMOS logic is better for high speed
which is L=250nm and number of transistors are also fixed operations.
which is 238 for CMOS comparator and 551 for HSD
comparator. That means now we have to consider the
remaining parameters with which we can do the comparative
analysis and those parameters are power frequency and
voltage scaling. We can better understand this with Table II,
Table III and Table IV.

Table II. Power and frequency rating at Vdd=5V

Vdd=5V
L=250nm Reference Power Maximum Power
frequency (mW) frequency (mW)
4bit CMOS 5MHz 15.2571 1GHz 69.9545
comparator
4bit HSD 5MHz 6.83533 100MHz 10.3746
comparator

Table III. Power and frequency rating at Vdd=3V

Vdd=3V
L=250nm Reference Power Maximum Power
frequency (mW) frequency (mW) Fig. 13. Power consumption at 5MHz
4bit CMOS 5MHz 3.5957 1GHz 12.0008
comparator Then Fig.14 shows that CMOS comparators are much
4bit HSD 5MHz 1.5986 50MHz 1.2981 faster than that of Domino comparators and here in this paper
comparator
maximum frequency supported by CMOS comparator is
1GHz whereas it’s 100MHZ in Domino comparator and this is
Table IV. Power and frequency rating at Vdd=1V the maximum frequency of comparator circuit for CMOS and
Domino logic respectively. So we can say that Domino logic
Vdd=1V is better for power saving and CMOS logic is better for high
L=250nm Reference Power Maximum Power
frequency (nW) frequency (uW)
speed operations.
4bit CMOS 5MHz 99.3080 250MHz 268.100
comparator
4bit HSD 5MHz 26.9506 10MHz 40.4430
comparator

From Table II, Table III and Table IV we can say that
near about 55% of power is less consumed in Domino logic
comparators than that of CMOS comparators and maximum
frequency with which circuit can run easily is more in CMOS
comparators than that of in Domino comparators. We also
observed that after voltage scaling the power saving increases
and hence more power saving is there because of voltage
scaling. This can be better understand with the charts shown
below which shows power consumption in both techniques,
maximum frequency support by each technique and power
consumption at maximum speed and power comparison at
maximum voltage scaling. Fig.13 shows power comparison at
5MHz. From Fig.13 we can easily see that amount of power
required by Domino logic comparator is half to that of power
required in CMOS comparators. Then Fig.14 shows that
CMOS comparators are much faster than that of Domino Fig. 14. Maximum frequency support
comparators and here in this paper maximum frequency
supported by CMOS comparator is 1GHz whereas it’s As shown in Fig.13 and Fig.14 we can see different
100MHZ in Domino comparator and this is the maximum power and frequency ratings which are different for changing
frequency of comparator circuit for CMOS and Domino logic voltage supplies. As we reduced the voltage supply Vdd the
 2016 Online International Conference on Green Engineering and Technologies (IC-GET)

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