Total No. of Questions: 4 Roll No.
Total No. of Pages: 2
Unit-Test-I (INSEM)
S.E.(Computer Engg.)
Digital Electronics & Logic Design
(2024 Pattern) (Semester – 3rd) (MDM-230-COM)
Time: 1 Hour [Max. Marks: 30]
Instructions to the candidate:
1) Attempt Q1 or Q2, Q3 or Q4
2) Neat diagrams must be drawn whenever necessary
3) Figures to the right indicate the full marks.
4) Assume suitable data, if necessary.
Q1.
a) What is Multiplexer? Design 16:1 multiplexer by 4:1 multiplexer. [5 marks]
b) Simplify the following function using K-map minimization technique
Y(A, B, C, D) = ∑m (0, 1, 2, 3, 5, 7, 8, 9, 11, 14) [5 marks]
c) Simplify the expression F = π M(2, 5, 7, 11, 15) + d ( 9, 13) using the
K-map method. [5 marks]
OR
Q2.
a) Minimize the following logic function using K-map and realize using NAND gates only.
F(A,B,C,D) = π M(0, 1, 3, 4, 5, 6, 9, 12, 14) [7 Marks]
b) Minimize the following logic function using K-map and realize using basic gates &
NAND gates . F(A,B,C,D) = π M(0, 1, 3, 4, 5, 6, 9, 12, 14). [8 Marks]
Q3.
a) State and prove DeMorgan’s theorem. [5 Marks]
b) Perform (16)10 – (29)10 using 1’s and 2’s complement methods. [5 Marks]
c) What do you mean by half adder and full adder? How will you implement
full adder using half adder? Draw the circuit diagram. [5 Marks]
OR
Q4.
a) Design 2 bit comparator with logic diagram. [5 Marks]
b) Express the function Y= AB+AC+ACD in canonical sum of product form and
Y= (A+B).(A+C).(A+C+D) in canonical product of sum form. [5 Marks]
c) Design 4 bit binary to gray code converter circuit using logic gates. [5 Marks]
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