NATIONAL INSTITUTE OF TECHNOLOGY, TIRUCHIRAPPALLI
Department of Electrical and Electronics Engineering
EE LR 10 Circuits and Digital Laboratory
Roll No. 1 0 7 1 2 4 0 9 1
Expt. No. 11 Date:9/10/2025
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10. Implementation of 2-Bit Synchronous Down Counter using JK Flip Flop
Aim:
To Implement 2-Bit Synchronous Down Counter using JK Flip Flop (IC 7476)
Apparatus Required:
[Link] Name of Apparatus Range Quantity
2 IC 7476 (JK Flip Flop) - 1
3 Digital IC trainer - 1
4 Breadboard - 1
5 Connecting wires -
6 Waveform generator 1
(clock) - 1
Circuit Diagram:
STATE DIAGRAM OF JK FLIP FLOP
X1
0X
X0
1X
STATE TRANSITION DIAGRAM
Table:
FUNCTION TABLE
Q(n) Q(n+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
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STATE TRANSITION TABLE
Q1(n) Q0(n) Q1(n+1) Q0(n+1)
1 1 1 0
1 0 0 1
0 1 0 0
0 0 1 1
STATE EXCITATION TABLE
Q1(n) Q0(n) J1 K1 J0 K0
1 1 X 0 X 1
1 0 X 1 1 X
0 1 0 X X 1
0 0 1 X 1 X
Calculations:
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Inference:
The State Transition table contains all possible transitions of Q and the excitation table
gives us the required values of J and K to obtain certain transition .Then a 2 variable K
Map is used to find expression of J and K in terms of Q1(n) and Q0(n).
Results:
Hence the 2 bit synchronous down counter was constructed and implemented using JK
Flip Flop (IC-7476)
Content Max. marks Marks
Awarded
Observation 35
Record 05
Total 40
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