A CISC Architecture RISC Architecture
Larger instructions with LOAD- STORE Architecture
variable formats
Fewer Addressing Modes
(16-64 bits/ instruction)
Fixed Length Instructions
Larger Addressing Modes More Registers
(12- 24)
Designed for Pipeline
Few Registers Efficiency
Hardwired Control Unit
Most Microcoded with
control Memory
• Universal architecture with full functional flexibility and
functional expandability (requires no change to
implement any function):
Universal architecture that can
sequentially realize any function
without requiring any change In any
Data
ALU part of hardware because the control
Memory
is also flexible (programmable
through the contents of control
memory e.g. the sequence of control
words stored in the control memory
Control Control
Memory sequencer
that are sequentially fetched and
applied by the control sequencer)
Topics in this course …..
➢ Specific Instruction set architecture
➢ Arithmetic unit and how to build an ALU
➢ Constructing a Processor: Datapath & Control
➢ Performance Indices
➢ Pipelining to improve performance
➢ Instruction Level Parallelism
➢ Cache memory Design and performance metrics
Text Book:
Patterson, David A & J L Hennessy, Computer
Organization& Design, Elsevier, 6th Ed., 2021.
Ref:
Samir Palnitkar, Verilog HDL: A Guide to Digital
Design and Synthesis, Pearson Education Asia, 2nd
Ed. 2006.
Tool: Vivado from Xilinx ( Verilog Simulator)
Components
Mid Sem Test :60
Lab (Reg + Test)/Assignment/Project :60
Comprehensive :80
BITS Pilani, Pilani Campus
The Role of Performance
Performance is the key to understanding underlying
motivation for the hardware and its organization
▪ Why is some hardware better than others for different
programs?
▪ What factors of system performance are hardware
related? (e.g., do we need a new machine, or a new
operating system?)
▪ How does the machine's instruction set affect
performance?
Computer Performance:
(Function of time)
• Response Time (elapsed time, latency):
– how long does it take to execute (start to Individual user
concerns…
finish) my job?
– Ex: how long must I wait for the database query?
• Throughput:
– how many jobs can the machine run at once?
Systems manager
– what is the average execution rate? concerns…
Execution Time
• Elapsed Time
– counts everything (disk and memory accesses, waiting for I/O, running
other programs, etc.) from start to finish
– a useful number, but often not good for comparison purposes
elapsed time = CPU time + wait time (I/O, other programs, etc.)
• CPU time
– doesn't count waiting for I/O or time spent running other programs
– can be divided into user CPU time and system CPU time (OS calls)
CPU time = user CPU time + system CPU time
elapsed time = user CPU time + system CPU time + wait time
• Our focus: user CPU time (CPU execution time or, simply, execution time)
– time spent executing the lines of code that are in our program
Clock Cycles
▪ Instead of reporting execution time in seconds, we often use cycles. In
computer hardware events progress cycle by cycle: in other words, each
event, e.g., multiplication, addition, etc., is a sequence of cycles
seconds cycles seconds
=
program program cycle
▪ Clock ticks indicate start and end of cycles:
cycle time
tick
tick
▪ cycle time = time between ticks
▪ clock rate (frequency) = cycles per second
(1 Hz. = 1 cycle/sec, 1 MHz. = 106 cycles/sec)
Performance Equation I
seconds cycles seconds
=
program program cycle
equivalently
CPU execution time CPU clock cycles Clock cycle time
for a program for a program
• So, to improve performance one can either:
– reduce the number of cycles for a program, or
– reduce the clock cycle time, or, equivalently, increase the clock rate
How many cycles are required for a
program?
time
Multiplication takes more time than addition
Floating point operations take longer than integer ones
Accessing memory takes more time than accessing registers
Important point: changing the cycle time often changes the number
of cycles required for various instructions because it means changing
the hardware design.
Example
• A program runs in 10 seconds on computer A, which has a 4GHz.
clock.
• We are trying to help a computer designer build a new machine B, that
will run this program in 6 seconds. The designer can use new (or
perhaps more expensive) technology to substantially increase the clock
rate, but has informed us that this increase will affect the rest of the
CPU design, causing machine B to require 1.2 times as many clock
cycles as machine A for the same program.
• What clock rate should we tell the designer to target?
Clock cycles(A)=40x109
6=1.2x 40x109/Clock rate(B)
➔Clock rate (B)=8GHz
CPU execution time CPU clock cycles x Clock cycle time
for a program = for a program
Performance Measure
• Performance is determined by execution time
• Do any of these other variables equal performance?
– # of cycles to execute program?
– # of instructions in program?
– average # of cycles per instruction?
– average # of instructions per second?
• Common pitfall : thinking one of the variables is indicative of
performance when it really isn’t
Performance Equation II
CPU execution time = Instruction count X average CPI x
for a program Clock cycle time
CPI Example
◼ Computer A: Cycle Time = 250ps, CPI = 2.0
◼ Computer B: Cycle Time = 500ps, CPI = 1.2
◼ Same ISA
◼ Which is faster, and by how much?
CPU Time = Instructio n Count CPI Cycle Time
A A A
= I 2.0 250ps = I 500ps A is faster…
CPU Time = Instructio n Count CPI Cycle Time
B B B
= I 1.2 500ps = I 600ps
CPU Time
B = I 600ps = 1.2
CPU Time I 500ps …by this much
A
CPI Example
Alternative compiled code sequences using instructions
in classes A, B, C
Class A B C
CPI for class 1 2 3
IC in sequence 1 2 1 2
IC in sequence 2 4 1 1
◼ Sequence 1: IC = 5 ◼ Sequence 2: IC = 6
◼ Clock Cycles ◼ Clock Cycles
= 2×1 + 1×2 + 2×3 = 4×1 + 1×2 + 1×3
= 10 =9
◼ Avg. CPI = 10/5 = ◼ Avg. CPI = 9/6 = 1.5
2.0
Performance Summary
Instructions Clock cycles Seconds
CPU Time =
Program Instruction Clock cycle
◼ Performance depends on
◼ Algorithm: affects IC, possibly CPI
◼ Programming language: affects IC, CPI
◼ Compiler: affects IC, CPI
◼ Instruction set architecture: affects IC, CPI, Tc
T = CPI x Instruction count x clock time
Performance determined by
Instruction set N T
Architecture CPI T
Hardware f T
CISC aims to reduce N at the expense of CPI
RISC aims to reduce CPI at the expense of N
➢ The simplest method of addition of two binary numbers is the
carry- propagate addition.
➢ This is like hand-addition where two binary numbers are
added bit-by-bit, starting from the least significant bit, and
carries are propagated from a bit-stage to the adjoining more
significant bit-stage
➢ Delay of a N-bit adder architected this way will be N * Tadd ;
where Tadd is the delay of one-bit adder.
➢ Multiplier: 16x16: 16bit * 16 bit multiplication . How much
time it takes?