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FSM Vending Machine Simulation Project

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0% found this document useful (0 votes)
5 views12 pages

FSM Vending Machine Simulation Project

Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

PES UNIVERSITY, Bangalore

Established under Karnataka Act No. 16 of 2013)


Department of Computer Science & Engineering
UE24CS251A: DIGITAL DESIGN AND COMPUTER ORGANIZATION

Student 1:

Name: CHANDANA O N

SRN: PES1UG24AM353

Student 2:

Name: BHUMIKA PATIL

SRN: PES1UG24AM352

Problem statement:

FSM-based Vending Machine with Python Simulation

Solution:

1. Code

2. Screen shot of output

3. Individual Contribution of team members


Contribution of Team Members :
1. CHANDANA O N – PES1UG24AM353
Role : Python Scripting and Simulation Automation
 Developed Python scripts for generating random coin
input sequences.
 Automated the running of Verilog simulations using
subprocess calls.
 Parsed simulation outputs and validated results
against expected behaviour.
 Logged mismatches to ensure robustness
and accuracy of verification.
 Implemented the FSM design in Verilog following
the project specifications.
 Developed the Verilog testbench to simulate the
vending machine with various coin inputs.

2. BHUMIKA PATIL – PES1UG24AM352


Role : FSM Design and Documentation
 Designed the FSM state diagram and state transition
table.
 Documented design decisions and prepared clear
diagrams for team clarity.
 Provided in-depth explanations and specifications for
the overall machine behavior.
 Assisted debugging Python scripts during simulation.

Validated the output dispense signal and state


transitions through simulation.
 Debugging and fixing of Verilog Code and
Testbench.
Overall Team Contribution and Coordination
 Agreed on common interfaces (coin encoding,
dispense signal) to ensure smooth integration.
 Maintained frequent communication to exchange
documentation and code updates.
 Collaboratively debugged issues found during initial
testing phases in both Verilog and Python.
 Conducted joint testing sessions combining Python
automation and Verilog simulation to validate the full
system.

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