DUAL PORT

Random Access
Memory
DPRAM
LIKITHA
MANOGNA DEVI
RITHRISHA REDDY
Objectives presented

01 Abstract 05 Software Explanation

02 Introduction 06 Results of project

03 Single port RAM 07 Advantages and Disadvantages

04 Dual port RAM 08 Summary

 Abstract for Dual port RAM
.This project explores the design and implementation of a dual-port RAM (Random
Access Memory) using Verilog in a digital design environment. Dual-port RAM allows
concurrent access from two independent data ports, which is essential for applications
requiring simultaneous read and write operations, such as in high-speed data processing
and communication systems. The project focuses on developing a versatile and efficient
memory structure, emphasizing Verilog’s role in enabling precise control over data flow,
timing, and resource management. Through simulation and testing, showcasing its
potential for enhancing parallel data processing in digital systems. This implementation
highlights Verilog’s capability in creating scalable and reliable digital memory
architectures that meet modern computational demands.
INTRODUCTION
Random Access Memory(RAM)
A memory unit stores binary information in groups of bits called [Link] data
consists of n lines(for n bit words).Data input lines provide the information to be
stored into the [Link] data output lines carry the information out(read)
from the [Link] address consists of k lines which specify which
word(among the words available ) to be selected for reading or [Link]
control lines Read and write(usually combined into a single control line Read/
Write) specifies the direction of transfer of the data.
The Write operation
Transfers the address of the desired word to the address lines.
Transfers the data bits(the word) to be stored in memory to the data input lines
Activates the write control line (set Read/Write to 0)
The Read operation :
Transfers the address of the desired word to address lines
Activates the Read control line (set Read/Write to 1)
Block Diagram of a Memory unit
Single Port RAM
Single-port RAM is a type of memory architecture that has a single access port
for reading or writing data. This means that at any given moment, only one
operation—either a read or a write—can be performed. Due to this restriction,
single-port RAM is relatively simple in design and resource-efficient, making it
suitable for applications that do not require concurrent data access. Single-port
RAM is widely used where low complexity and cost are priorities over parallel data
access.
In digital design, single-port RAM is often implemented using a single clock signal,
enabling synchronous operation and easy integration in systems where only one
data access at a time is needed.
Block Diagram of a Single Port RAM
Solving the Exception
Single-port RAM is limited by its single access point, allowing only one read or
write operation at a time. This restricts its use in applications that require
concurrent data access, such as high-speed data processing. To address this
limitation, dual-port RAM is used, which provides two independent ports,
enabling simultaneous read and write operations. This capability makes dual-
port RAM ideal for systems needing parallel data handling and improved
performance.
Defintion of Dual Port RAM
Dual-port RAM is a type of memory that allows two independent ports to access the memory
simultaneously, enabling concurrent read and write operations. Unlike single-port RAM, which can
handle only one operation at a time, dual-port RAM can perform both a read and a write
operation at the same time, or even two reads or two writes if required. Each port has its own
address, data, and control signals, allowing independent access to different memory locations.
This parallelism makes dual-port RAM ideal for high-speed applications where simultaneous data
access is essential, such as in graphics processing, network processors, and shared-memory
architectures.
Implementation of Read and Write Operations
In dual-port RAM, each port can be configured for either reading or writing
independently, allowing simultaneous operations without interference. When both
ports access different addresses, they function completely independently, with one
port possibly reading data while the other writes to a different location. If both ports
access the same address, conflict resolution logic is applied to determine priority and
avoid data corruption. Typically, one port is given precedence, or specific arbitration
logic is used. This setup in Verilog or other hardware description languages involves
defining the control signals and address lines for each port, ensuring that simultaneous
read and write operations are correctly managed and data integrity is maintained.
Block diagram of Double port RAM
Defintion of Dual Port RAM
This block diagram represents a dual-port RAM architecture with two independent ports, labeled
portA and portB, which enable simultaneous read and write operations.
Port A: On the left side, signals for portA include:
dina: Data input for writing (8 bits).
addra: Address input (3 bits), selecting the memory location for reading or writing.
clka: Clock input for synchronizing operations on this port.
ena: Enable signal to activate port A.
wea: Write enable signal, which allows data to be written to memory when active.
douta: Data output for reading (8 bits).
 Port B: Similarly, on the right side, signals for portB include:
dimb: Data input for writing (8 bits).
addrb: Address input (3 bits).
clkb: Clock input for synchronizing operations on port B.
enb: Enable signal for activating port B.
web: Write enable for writing data on this port.
doutb: Data output for reading (8 bits).
This configuration allows both ports to operate independently, reading or writing data at
different addresses simultaneously. Each port has its own clock, address, enable, and write
enable signals, providing flexibility and parallelism in accessing memory locations.
Software Explanation
We used Vivado Xilinx, a powerful software suite for FPGA design, to develop and test our dual-
port RAM project. Vivado provides tools for writing, synthesizing, simulating, and analyzing
Verilog-based hardware designs. It supports a wide range of FPGA devices, making it well-suited
for complex digital designs like dual-port RAM.
In this project, we used Vivado’s design, synthesis, and simulation features to build and test our
dual-port RAM module. The RAM was coded in Verilog with two independent ports, enabling
simultaneous read and write operations. Using Vivado’s simulation tools, we verified that both
ports could access different memory locations concurrently without conflicts. Finally, we
synthesized the design, converting it into a hardware-optimized format that could be
implemented on an FPGA for real-world testing.
 Results of the project
At 10ns , port A writes 0x55 to address 0x01
At 30ns , port B writes 0x66 to address 0x02
Port A reads from address 0x01 and should output 0x55
Advanatges of DPRAM
Simultaneous Access: Allows two independent read and/or write operations to occur
simultaneously, improving data throughput.
Enhanced Performance: Ideal for high-speed applications like graphics processing and
network data handling, where parallel access is required.
Independent Control: Each port operates independently with separate address, data, and
control lines, enabling flexible usage.
Reduced Latency: Minimizes wait time for read and write operations in systems requiring
frequent data access.
Supports Parallel Processing: Enables efficient memory sharing between processors, making it
suitable for multi-core and multi-processor systems.
DisAdvanatges of DPRAM
Increased Complexity: Requires more complex control logic to handle simultaneous
operations and avoid data conflicts.
Higher Cost: Dual-port RAM is more expensive than single-port RAM due to its additional
circuitry and resource requirements.
Larger Area Requirement: Consumes more silicon area on an FPGA or chip, which may limit its
use in space-constrained designs.
Potential for Data Conflicts: Needs conflict resolution mechanisms when both ports access
the same memory location simultaneously.
Higher Power Consumption: The added circuitry and ability to access data in parallel often
result in increased power usage.
Project Summary
This project focuses on the design and implementation of a dual-port RAM
using Verilog in Vivado Xilinx software. Dual-port RAM allows simultaneous
read and write operations through two independent ports, making it ideal for
high-performance applications requiring concurrent data access. In this
project, we utilized Vivado’s design, simulation, and synthesis tools to create,
test, and verify the functionality of the dual-port RAM. Behavioral simulations
ensured that both ports could access memory locations concurrently without
conflicts. The final synthesized design can be implemented on an FPGA,
demonstrating the practical application of dual-port RAM in digital systems.
Thank You