OPA596

SBOSA42A – JUNE 2024 – REVISED FEBRUARY 2025

OPAx596 High-Voltage (85V), Low-Power (420μA), High-Slew Rate (100V/μs)

Power Amplifier With Mux-Friendly Inputs
1 Features The OPAx596 enable the next generation of high-
voltage systems, such as output load drivers in
• High slew rate: 100V/µs
semiconductor test and digital power supplies by
• Low power consumption: 420μA
increasing the output voltage of the system though
• Wide power-supply range:
high-gain configurations. Low power consumption and
– ±4V to ±42.5V
industry-standard small packages allow the device
– 8V to 85V
to be used in high-density systems that are size
• Mux-friendly inputs
constrained, while reducing the thermal management
• Input below the negative rail
requirements for the system.
• Rail-to-rail output
• Gain bandwidth: 3.75MHz Through proprietary design techniques, the OPAx596
• Low noise: 12.8nV/√Hz are capable of a very high slew rate with
• Low input bias current: 5pA minimal power consumption to improve large-signal
• Low input offset voltage: ±1mV settling time and maximize the effective large-signal
• Output current drive: ±30mA bandwidth. These devices also offers mux-friendly
• Wide temperature range: –40°C to +125°C inputs that enable large differential voltage (up to 85V)
• Industry-standard small packages: and help improve settling behavior when compared to
– D (8-pin SOIC) traditional inputs in multiplexed applications.
– DBV (5-pin SOT-23) The OPAx596 are available in industry-standard
– DGK (8-pin VSSOP) packages and operates across the temperature range
2 Applications of –40°C to +125°C.

• Semiconductor test Device Information

PART NUMBER CHANNELS PACKAGE(1)
• LCD test
• Programmable dc power supply OPA596 Single DBV (SOT-23, 5)
• CT and PET scanner D (SOIC, 8)
OPA2596 (2) Dual
• Source measurement unit (SMU) DGK (VSSOP, 8)
• Optical module
• Lab and field Instrumentation (1) For more information, see Section 10.
(2) Preview information (not Production Data).
3 Description Related 85V Products
PART NUMBER OUTPUT CURRENT INPUT OFFSET
The OPA596 and OPA2596 (OPAx596) are high-
OPAx596 ±30mA 1mV
voltage (85V), high slew rate (100V/μs), micro-power
OPAx593 ±250mA 100µV
(420μA), unity-gain stable operational amplifiers.

VREF = 5V
42.5V
DAC + OPA596
Output Voltage (10V/div)

VOUT
29.8k –
42.5V

62pF

255k

VIN 34k
VOUT

Time (250ns/div)
DAC Output Buffer With Gain
Large-Signal Step Response

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
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Table of Contents
1 Features............................................................................1 6.4 Device Functional Modes..........................................17
2 Applications..................................................................... 1 7 Application and Implementation.................................. 18
3 Description.......................................................................1 7.1 Application Information............................................. 18
4 Pin Configuration and Functions...................................3 7.2 Typical Applications.................................................. 18
5 Specifications.................................................................. 4 7.3 Power Supply Recommendations.............................23
5.1 Absolute Maximum Ratings........................................ 4 7.4 Layout....................................................................... 23
5.2 ESD Ratings .............................................................. 4 8 Device and Documentation Support............................26
5.3 Recommended Operating Conditions.........................4 8.1 Receiving Notification of Documentation Updates....26
5.4 Thermal Information....................................................4 8.2 Support Resources................................................... 26
5.5 Electrical Characteristics.............................................5 8.3 Trademarks............................................................... 26
5.6 Typical Characteristics................................................ 7 8.4 Electrostatic Discharge Caution................................26
6 Detailed Description......................................................14 8.5 Glossary....................................................................26
6.1 Overview................................................................... 14 9 Revision History............................................................ 26
6.2 Functional Block Diagram......................................... 14 10 Mechanical, Packaging, and Orderable
6.3 Feature Description...................................................15 Information.................................................................... 26

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4 Pin Configuration and Functions

OUT 1 5 V+

V± 2

±
+IN 3 4 ±IN

Not to scale

Figure 4-1. OPA596 DBV Package, 5-Pin SOT-23 (Top View)

Table 4-1. Pin Functions: OPA596

PIN
TYPE DESCRIPTION
NAME NO.
+IN 3 Input Noninverting input
–IN 4 Input Inverting input
OUT 1 Output Output
V+ 5 Power Positive (highest) power supply
V– 2 Power Negative (lowest) power supply

OUT A 1 8 V+

±IN A 2 7 OUT B

+IN A 3 6 ±IN B

V± 4 5 +IN B

Not to scale

Figure 4-2. OPA2596 D (Preview) Package, 8-Pin SOIC and DGK (Preview) Package, 8-Pin VSSOP
(Top View)

Table 4-2. Pin Functions: OPA2596

PIN
TYPE DESCRIPTION
NAME NO.
+IN A 3 Input Noninverting input, channel A
+IN B 5 Input Noninverting input, channel B
–IN A 2 Input Inverting input, channel A
–IN B 6 Input Inverting input, channel B
OUT A 1 Output Output, channel A
OUT B 7 Output Output, channel B
V+ 8 Power Positive (highest) power supply
V– 4 Power Negative (lowest) power supply

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5 Specifications
5.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage, VS = (V+) – (V–) 93 V
Common-mode (V–) – 0.3 (V+) + 0.3
Signal input pin voltage(2) V
Differential (V+) – (V–)
Input current, all input pins(2) ±10 mA
ISC Output short circuit(3) Continuous
TJ Junction temperature 150 °C
Tstg Storage temperature –65 150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.3V beyond the supply rails must
be current-limited to 10mA or less.
(3) Short-circuit to ground.

5.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±500

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Dual supply ±4 ±42.5
VS Supply voltage V
Single supply 8 85
TA Ambient temperature –40 125 °C

5.4 Thermal Information

OPA596
THERMAL METRIC(1) DBV (SOT-23) UNIT
5 PINS
RθJA Junction-to-ambient thermal resistance 165.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 99.1 °C/W
RθJB Junction-to-board thermal resistance 64.5 °C/W
ψJT Junction-to-top characterization parameter 42.6 °C/W
ψJB Junction-to-board characterization parameter 64.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.5 Electrical Characteristics

at VS = 85V (±42.5V), TA = 25°C, RL = 10kΩ to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.2 ±1 mV
dVOS/dT Input offset voltage drift TA = –40°C to +125°C ±1 ±6 µV/°C
Power supply rejection
PSRR 8V ≤ VS ≤ 85V ±1 ±5 µV/V
ratio
INPUT BIAS CURRENT
±5 ±15
pA
IB Input bias current TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
±5 ±15
pA
IOS Input offset current TA = –40°C to +85°C ±50
TA = –40°C to +125°C ±1 nA
NOISE
Input voltage noise f = 0.1Hz to 10Hz 1.4 µVPP
f = 100Hz 17.8
en Input voltage noise density f = 1kHz 12.9 nV/√Hz
f = 10kHz 12.8
in Current noise density f = 1kHz 7 fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage Linear operation (V–) – 0.1 (V+) – 3.5 V
120 140
CMRR Common-mode rejection (V–) ≤ VCM ≤ (V+) – 3.5V dB
TA = –40°C to +125°C 120 140
INPUT IMPEDANCE
Differential 100 || 2.5 MΩ || pF
Common-mode 10 || 5.5 GΩ || pF
OPEN-LOOP GAIN

(V–) + 1V < VO < (V+) – 1.5V, 134 140

RL = 10kΩ to mid-supply TA = –40°C to +125°C 120 140
AOL Open-loop voltage gain dB
(V–) + 3V < VO < (V+) – 3.5V, 116 126
RL = 2kΩ to mid-supply TA = –40°C to +125°C 116 126
FREQUENCY RESPONSE
G=1 2.25
GBW Gain-bandwidth product G = 10 3 MHz
G = 100 3.75
SR Slew rate G = ±1, VO = 70V step 100 V/µs
tS Settling time To ±0.01%, G = 1, VO = 70V step, CL = 20pF 3 µs
Overload recovery G = –10 115 ns

Total harmonic distortion + RL = 10kΩ –102

THD+N G = +1, VO = 70VPP, f = 1kHz dB
noise RL = 2kΩ –95

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5.5 Electrical Characteristics (continued)

at VS = 85V (±42.5V), TA = 25°C, RL = 10kΩ to mid-supply, and VCM = VOUT = mid-supply (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT
No load 12 50
Voltage output swing from mV
VO RL = 10kΩ to mid-supply 100 435
rail
RL = 2kΩ to mid-supply 500 2.05 V
ISC Output current ±30 mA
CLOAD Capacitive load drive 1 nF
Open-loop output
ZO f = 1MHz 550 Ω
impedance
POWER SUPPLY
420 490
IQ Quiescent current IO = 0mA µA
TA = –40°C to +125°C 500
TEMPERATURE

Overtemperature Shutdown temperature, TJ 170

°C
shutdown Thermal hysteresis 20

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5.6 Typical Characteristics

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

30 30

25 25

20 20
Amplifiers (%)

Amplifiers (%)
15 15

10 10

5 5

0 0
-2 -1.5 -1 -0.5 0 0.5 1 1.5 2 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2
Input Offset Voltage (mV) Input Offset Voltage (mV)

Figure 5-1. Offset Voltage Production Distribution at 25°C Figure 5-2. Offset Voltage Production Distribution at 125°C
1

VCM = 39V
Input Offset Voltage (mV)

0.5

-0.5

-1
-45 -30 -15 0 15 30 45
Common-Mode Voltage (V)

Figure 5-3. Offset Voltage Production Distribution at −40°C Figure 5-4. Input Offset Voltage vs Common-Mode Voltage
1 1

VCM = 39V
Input Offset Voltage (mV)

Input Offset Voltage (mV)

0.5 0.5 VCM = 39V

0 0

-0.5 -0.5

-1 -1
-45 -30 -15 0 15 30 45 -45 -30 -15 0 15 30 45
Common-Mode Voltage (V) Common-Mode Voltage (V)
TA = 125°C TA = −40°C
Figure 5-5. Input Offset Voltage vs Common-Mode Voltage Figure 5-6. Input Offset Voltage vs Common-Mode Voltage

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

25 1

20

Input Offset Voltage (mV)

0.5
Amplifiers (%)

15
0
10

-0.5
5

0 -1
-5 -4 -3 -2 -1 0 1 2 3 4 5 -50 -25 0 25 50 75 100 125 150
Input Offset Voltage Drift ( V/ C) Temperature ( C)

Figure 5-7. Offset Voltage Drift Distribution Figure 5-8. Input Offset Voltage vs Temperature
1 20

15
VCM = −42.5V
Input Offset Voltage (mV)

0.5 10
Input Bias Current (pA)

0 0

-5
VCM = 42.5V
-0.5 -10
IBN
VS = 8V IBP
-15 IBOS
-1 -20
5 15 25 35 45 55 65 75 85 -45 -30 -15 0 15 30 45
Supply Voltage (V) Common-Mode Voltage (V)

Figure 5-9. Offset Voltage vs Power Supply Voltage Figure 5-10. Input Bias vs Common-Mode Voltage
1000 180
CMRR
800 160 PSRR−
600 PSRR
140
Input Bias Current (pA)

Rejection Ratio (dB)

400
120
200
100
0
80
-200
60
-400
-600 IBN 40
IBP
-800 IBOS 20

-1000 0
-50 -25 0 25 50 75 100 125 150 10m 100m 1 10 100 1k 10k 100k 1M 10M
Temperature ( C) Frequency (Hz)

Figure 5-11. Input Bias and Input Offset Current vs Temperature Figure 5-12. Power-Supply and Common-Mode Rejection Ratio
vs Frequency

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

180

Common-Mode Rejection Ratio (dB)

160

140

120

100
-50 -25 0 25 50 75 100 125 150
Temperature ( C)

Figure 5-13. Power-Supply Rejection Ratio vs Temperature Figure 5-14. Common-Mode Rejection Ratio vs Temperature

Figure 5-15. Open-Loop Gain and Phase vs Frequency Figure 5-16. Open-Loop Gain vs Temperature
60 1000
Voltage Noise Spectral Density (nV Hz)

500
40 300
200
20 100
Gain (dB)

50
0 30
20
-20 10
G = −1 5
-40 G= 1 3
G = 10 2
G = 100
-60 1
100 1k 10k 100k 1M 10M 100m 1 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 5-17. Closed-Loop Gain vs Frequency Figure 5-18. Voltage Noise Density vs Frequency

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

500

Current Noise Spectral Density (fA Hz)

300
200
Output Voltage (500nV/div)

100
50
30
20
10
5
3
2
1
0.5
1 10 100 1k 10k 100k
Time (1s/div) Frequency (Hz)

Figure 5-19. 0.1Hz to 10Hz Noise Figure 5-20. Current Noise Density vs Frequency
0.1 -60 1 -40

Noise (dB)
0.05 0.5 G = −1, 1M Load
Total Harmonic Distortion + Noise (dB)
Noise (%)

Noise ( )

0.2 G = −1, 10k Load

0.02 0.1 G = −1, 2k Load -60
0.01 -80 0.05 G = 1, 1M Load
G = 1, 10k Load
0.005 0.02 G = 1, 2k Load

Total Harmonic Distortion

Total Harmonic Distortion
Total Harmonic Distortion

0.002 0.01 -80

0.005
0.001 -100
0.002
0.0005 0.001 -100
G = −1, 1M Load 0.0005
0.0002
G = −1, 10k Load
0.0001 G = −1, 2k Load -120 0.0002
5E-5 G = 1, 1M Load 0.0001 -120
G = 1, 10k Load 5E-5
2E-5 G = 1, 2k Load 2E-5
1E-5 -140 1E-5 -140
100m 1 10 100 20 200 2k 20k
Output Amplitude (VPP) Frequency (Hz)
f = 1kHz 24.75VRMS (70VPP)
Figure 5-21. Total Harmonic Distortion + Noise Ratio vs Output Figure 5-22. Total Harmonic Distortion + Noise Ratio vs
Amplitude Frequency
45 -30
TA = −40 C
TA = 25 C
TA = 85 C
TA = 125 C
Output Voltage (V)
Output Voltage (V)

40 -35

35 -40
TA = −40 C
TA = 25 C
TA = 85 C
TA = 125 C
30 -45
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40 45 50 55
Output Current (mA) Output Current (mA)

Figure 5-23. Output Voltage Swing vs Output Sourcing Current Figure 5-24. Output Voltage Swing vs Output Sinking Current

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

VIN VIN
VOUT VOUT
Output Voltage (15V/div)

Voltage (10V/div)
Time (2ms/div) Time (250ns/div)
Gain = −10
Figure 5-25. No Phase Reversal Figure 5-26. Positive Overload Recovery
10000
Voltage (10V/div)

1000
Z

VIN
VOUT
100
1 10 100 1k 10k 100k 1M 10M 100M
Time (250ns/div) Frequency (Hz)
Gain = –10
Figure 5-27. Negative Overload Recovery Figure 5-28. Open-Loop Output Impedance vs Frequency
80 80
Riso = 0 Riso = 0
Riso = 25 Riso = 25
Riso = 50 Riso = 50
60 60
Overshoot (%)

Overshoot (%)

40 40

20 20

0 0
10 100 1k 10 100 1k
Capacitance (pF) Capacitance (pF)
Gain = −1 Gain = +1
Figure 5-29. Small-Signal Overshoot vs Capacitive Load Figure 5-30. Small-Signal Overshoot vs Capacitive Load

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

Falling VIN
Rising VOUT

Output Voltage (2mV/div)

Voltage (10mV/div)

Time (1µs/div) Time (2 s/div)

To 0.01% Gain = +1
Figure 5-31. Settling Time Figure 5-32. Small-Signal Step Response

VIN
VOUT
Output Voltage (10V/div)

Time (25µs/div)
Gain = −1 Gain = +1
Figure 5-33. Small-Signal Step Response Figure 5-34. Large-Signal Step Response

VIN
VOUT
Output Voltage (10V/div)

Time (25 s/div)

Gain = −1
Figure 5-35. Large-Signal Step Response Figure 5-36. Short-Circuit Current vs Temperature

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5.6 Typical Characteristics (continued)

at TA = 25°C, VS = 85V, VCM = VOUT = mid-supply, and RL = 10kΩ (unless otherwise noted)

500 500

450 450
Quiescent Current ( A)

Quiescent Current ( A)
VS = 8V

400 400

350 350

300 300
5 15 25 35 45 55 65 75 85 -50 -25 0 25 50 75 100 125 150
Supply Voltage (V) Temperature ( C)

Figure 5-37. Quiescent Current vs Supply Voltage Figure 5-38. Quiescent Current vs Temperature
180
165
150
135
120
EMIRR (dB)

105
90
75
60
45
30
15
0
10M 100M 1G 10G
Frequency (Hz)

Figure 5-39. Electromagnetic Interference Rejection

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6 Detailed Description
6.1 Overview
The OPAx596 are low power (420μA), high-slew rate (100V/μs), 85V operational amplifiers (op amps). These
op amps uses a proprietary design technique to achieve a very high slew capability with minimal power
consumption. The OPAx596 is capable of driving ±30mA of output current and can swing to within 100mV
of either power supply rail.
The amplifiers feature state-of-the-art CMOS technology and advanced design features that help achieve
outstanding ac performance and enable small package options. The OPAx596 strengths also include 3.75MHz
bandwidth, 12.8nV/√Hz noise spectral density, and low input bias current. These features make the OPAx596 an
exceptional choice to gain or buffer the output of a digital-to-analog converter (DAC) in digitally programmable
power supplies.
6.2 Functional Block Diagram
V+

OPAx596

–
NCH Input
Stage
+

IN+
High
85V Differential Advanced Output
Capacitive Load OUT
Mux-Friendly Input Slew Boost Stage
Compensation

IN–

+
PCH Input
Stage
–

V

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6.3 Feature Description

6.3.1 Mux-Friendly Inputs
The OPAx596 use a unique input architecture to eliminate the need for input protection diodes but still provide
robust input protection under transient conditions. Conventional input diode protection schemes shown in Figure
6-1 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays because of alternate current paths, as shown in Figure 6-2. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes that cause an increase in input current and result in extended settling
time.
V+ V+

VIN+ VIN+

VOUT VOUT
~0.7V 85V OPA596

VIN VIN

V V

Conventional Input Protection Limits Differential Input Range OPA596 Provides Full 85V Differential Input Range

Figure 6-1. OPA596 Input Protection Does Not Limit Differential Input Capability

Ron_mux 1
Vn = 10V RFILT 10V Sn 1 2
D
10V ~–9.3V
CFILT CS
CD

2 VIN–
Vn+1 = –10V RFILT –10V Sn+1 Ron_mux

~0.7V
CFILT CS Idiode_transient VOUT

VIN+
–10V

Input Low-Pass Filter Simplified Mux Model Buffer Amplifier

Figure 6-2. Back-to-Back Diodes Create Settling Issues

The OPAx596 feature a true high-impedance differential input capability for high-voltage applications. This
patented input protection architecture does not introduce additional signal distortion or delayed settling time,
making these devices an excellent choice for multichannel, high-switched, input applications. The OPAx596
tolerate a maximum differential swing (voltage between inverting and noninverting pins of the op amp) of up
to 85V, making these devices a great choice for use as a comparator or in applications with fast-ramping or
switched input signals.

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6.3.2 Thermal Protection

The OPAx596 has a thermal protection feature that prevents damage from self heating. When the junction
temperature (TJ) reaches approximately 170ºC, the op amp output stage disables. This thermal protection works
by monitoring the temperature of the output stage and turning off the op amp output drive. Thermal protection
forces the output to a high-impedance state. The OPAx596 is designed with approximately 20°C of thermal
hysteresis and returns to normal operation when the output stage temperature becomes less than approximately
150°C.
This thermal protection is not designed to prevent this device from exceeding absolute maximum ratings, but
rather from excessive thermal overload.
6.3.3 Advanced Slew Boost
Slew rate is the maximum rate of change of output voltage change with respect to time and is typically specified
in units of volts per microsecond, V/µs. Op amps can enter a slew condition when a large, rapid moving signal
is applied at the input. While slewing, the op amp enters an open loop condition and significant slew induced
distortion can be seen on the output signal.
Equation 1 shows that the slew rate, SR, of an op amp is typically determined by the saturation current of the
input stage, ITAIL, and the compensation capacitor, CC.

I
SR = TAIL
C (1)
C

Slew rate usually scales with the quiescent current, IQ, of the op amp. There are several ways that designers
have overcome slew rate limitation. For example, lowering CC, commonly known as decompensation, improves
slew rate at the expense of stability. Decompensated op amps require a minimum gain and are not stable at
unity gain. More commonly, modern op amps are equipped with slew boost technology that increases ISAT to
improve slew rate. Slew boost circuits can vary in implementation, but designers can typically expect about a 4
fold improvement over comparable unboosted op amps.
The OPAx596 uses a proprietary design to achieve an unprecedented slew rate to IQ ratio. The novel slew boost
technology in OPAx596 provides a nearly 100 × slew rate improvement over comparable unboosted op amps.
The op amp is unity gain stable and can be used configured as a buffer if desired.
Table 6-1 shows a comparison of slew rates and quiescent currents of different op amps.
Table 6-1. Op Amp Slew Rates and Quiescent
Current
QUIESCENT
PART NUMBER SLEW RATE
CURRENT
OPAx596 100V/µs 420µA
OPAx188 0.8V/µs 425µA
OPAx202 0.35V/µs 580µA
OPAx192 20V/µs 1mA
OPA454 13V/µs 3.2mA

6.3.4 Overload Recovery

Overload recovery is defined as the time required for the op amp output to recover from a saturated state to
a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds
the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the
propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time.

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6.3.5 Full-Power Bandwidth Improved

The full-power bandwidth curve has been a staple in data sheets for decades. The full-power bandwidth of an op
amp provides some indication about where designers can expect slew-induced distortion on a signal of a given
amplitude and frequency. The full-power bandwidth curve is generated using Equation 2.

FPBW = 2πV SR (2)

OUT_MAX

Figure 6-3 shows the full-power bandwidth of the OPAx596. The curve is a good reference for designers
that need to achieve high-voltage, high-frequency output swings with little concern for distortion performance.
Unfortunately, the curve provides little indication of the true distortion at any given point on the curve. The
full-power bandwidth curve is, after all, only a theoretical value and slew-induced distortion appears gradually
as the output nears the maximum rate of change. Furthermore, slew-induced distortion is only one of several
sources of op-amp distortion. Therefore, the curve is a decent starting point, but not a reliable source for
distortion performance.
Figure 6-4 shows the full power bandwidth in terms of total harmonic distortion (THD) performance for the
OPAx596. This curve provides a better indication of the level of distortion that a designer can expect for a signal
of a given amplitude and frequency. For example, the OPAx596 can achieve approximately −100dB or better
of THD at 70VPP up to approximately 1kHz. As a second example, the OPAx596 can achieve approximately
−130dB or better of THD at 10VPP up to about 1kHz. As a result of limitations in measurement bandwidth, only
20kHz data are recorded.

110
VS= 42.5V
100
VS= 4V
90
80
Output Voltage (VPP)

70
60
50
40
30
20
10
0
1 10 100 1k 10k 100k 1M 10M
Frequency (Hz)

Figure 6-3. Full-Power Bandwidth Figure 6-4. Full-Power Bandwidth Improved

6.4 Device Functional Modes

The OPAx596 has a single functional mode and is operational when the power-supply voltage is between 8V
(±4V) and 85V (±42.5V).

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7 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

7.1 Application Information

The OPAx596 are low power (420μA), high-slew rate (100V/μs), 85V power operational amplifiers (op amps).
These op amps use a proprietary design technique to achieve a very high slewing capability while consuming
minimal power. The low power consumption helps reduce heat generation on the board while the output swings
near the supply rail. The high slew reduces slew related distortion at the output when dealing with large peak,
high frequency signals.
7.2 Typical Applications
7.2.1 Bridge-Connected Piezoelectric Driver
AVDD

10k 100k
5VPP
PDAC
1nF

AVSS

60V
– 10
3.79k OPAx596
+

5V
95.3k 100k

100k
60V
100VPP
1nF

5V
– 10
OPAx596
VBIAS +
60V
Figure 7-1. 100VPP Piezoelectric Driver With Bridge Connected Load

[Link] Design Requirements

The OPAx596 is used to drive a piezoelectric actuator with a 100V operating range at a relatively low frequency
of 100Hz. The large capacitance inherent to the piezoelectric actuator can cause undesired ringing of the driver
amplifier. An inaccurate response of the actuator is possible due in part to amplifier instability. Adequate phase
margin for a 500nF equivalent load and wide output swing capability is necessary for a robust driver circuit for
the piezoelectric actuator presented here. Table 7-1 shows the design parameters.
Table 7-1. Design Parameters
PARAMETER VALUE
Power supply voltage 65V
Piezoelectric actuator capacitance (1kHz) 500nF
Piezoelectric operating voltage range 0V to 100V
Operating frequency 100Hz
DAC output voltage 5VPP

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[Link] Detailed Design Procedure

Piezoelectric actuators offer many benefits over traditional solenoid counterparts. Piezoelectric actuators are
more precise, power efficient, and smaller in general when compared to solenoid actuators. One challenge
with piezoelectric actuators is that the piezoelectric actuators operate over a very wide voltage range. Driving
voltages of more than 60V are not uncommon, and can easily reach hundreds of volts. The OPAx596 operate
with a supply voltage of up to 85V.
In this design example, the OPAx596 are used to provide a 100VPP signal to control a high-voltage piezoelectric
actuator (see also Figure 7-1). The piezoelectric actuator can be modeled as a large capacitor when operated at
less than the resonant frequency. The piezoelectric actuator is treated as a floating load driven by two op amps
of the OPAx596. The outputs of the op amps are set to be 180° out-of-phase to essentially double the voltage
seen by the actuator load. The signal voltage of the digital-to-analog converter is applied a −10V/V gain by the
OPAx596. A simple voltage divider provides a dc reference to level shift the output to get a unipolar driving
voltage. Figure 7-2 shows the output voltage of both amplifiers and the voltage seen by the piezoelectric load.
The large capacitive load seen by the amplifiers can lead to instability and proper compensation is required. A
straight forward method to improve phase margin and stability is to add isolation resistors and compensation
capacitors in the feedback. A small 10Ω RISO at the output of each of the OPAx596 and a 1nF compensation
capacitor is effective. Keep the isolation resistors as small as possible to minimize the voltage drop across them.
Choose the compensation capacitors according to the frequency of operation. For this example, 1nF capacitors
leave enough bandwidth to accommodate a 100Hz signal. Use simulation tools, such as PSPICE or TINA-TI, to
confirm stability.
Understanding the limitations of this circuit are important. As with any capacitive load, the impedance can
significantly decrease at higher frequencies. This behavior greatly increases the current output capability
requirements of the driver amplifier at high frequencies. If high frequency operation is required, consider other
amplifiers with higher current drive capability. At 100Hz, the OPAx596 is capable of supplying the necessary
current. Figure 7-3 shows the current output of the OPAx596 in this example.
[Link] Application Curves

30
25
20
15
10
Current (mA)

5
0
-5
-10
-15
-20
-25 Piezoelectric Drive Current
-30
0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
Time (ms)

Figure 7-2. Piezoelectric Driver Output Voltage Figure 7-3. Piezoelectric Driver Output Current

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7.2.2 DAC Output Gain and Buffer

VREF = 5V
42.5V
DAC + OPA596
VOUT
29.8k –
42.5V

62pF

255k

34k

[Link] Design Requirements

The OPAx596 is designed for use as an output driver stage with gain and provides a wide, bipolar supply
voltage. Combined with the small size of the SOT23-5 package and the low power consumption, these
features make this device a great choice for high-channel density systems, such as semiconductor test and
manufacturing platforms where many channels are present. In this design example, the OPAx596 is configured
for a gain of approximately 17V/V.
Table 7-2. Design Parameters
PARAMETER VALUE
Supply voltage −42.5V to +42.5V
Input voltage 0V to 5V
Output voltage −42.5V to +42.5V
Gain 17V/V

[Link] Detailed Design Procedure

In this design example, the OPAx596 is configured as both a gain stage and output driver. The input signal to the
amplifier is 0V to 5V, and the device is configured with a noninverting gain of 17V/V. The DAC reference voltage
of 5V is used as a reference to enable a bipolar output swing. This configuration results in an output voltage of
about −42.5V to +42.5V. This design example is common in many systems that use a DAC to provide the input
signal and require a wide output signal with low output current requirements. The OPAx596 can swing to either
rail while remaining within the thermally specified limits. Such systems include test and measurement platforms
and power supplies.

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7.2.3 Single-Supply Piezoelectric Driver

Some piezoelectric transducers can be referenced to ground as shown in Figure 7-4. The wide supply voltage
of the OPAx596 enables designers to drive a high voltage transducer up to 85V, without having to use the
more complicated bridge tied load configuration. The piezoelectric load presents a large capacitance at the
output of the amplifier and proper compensation is required to avoid instability. Also consider the output current
drive requirement. The current drive requirement is determined by the frequency of operation and the effective
capacitance of the load. High frequency and large capacitance reduce the effective impedance of the load and
thereby increase the current drive requirement. The OPAx596 are an excellent choice to drive piezoelectric loads
at dc and low frequency.
5k
75k

5V 85V
–
+
DAC + OPA596
80V
−

Figure 7-4. 80V Single-Supply Piezoelectric Driver

7.2.4 High-Side Current Sense

The OPAx596 enables high voltage current sense measurements. High-side voltage measurements of ±100V
or more can be easily implemented using the OPAx596. The voltage capability is proportional to the gain of the
sense circuit and the input common-mode range of the amplifier. Figure 7-5 shows the OPA596 configured for
a ±500V high side current measurement and a gain of 2. A high precision amplifier is used as a gain stage to
amplify the signal further.
Make the input resistors large enough to avoid any loading related errors. The low input bias current of the
OPAx596 allows for the use of larger resistors when compared to other power amplifiers and is not a major
contribution to the total error in this application. Special consideration of input bias current, thermal noise, and
input common-mode range is warranted when choosing resistors for this design.

DAC + Rshunt = 100m

PA
–
1M

51.1k

RG RF
42.5V DUT
+
1M
OPA596
OPA189 +
ADC
–

 42.5V
–

49.9k 49.9k

99k 1k
1.3k

Figure 7-5. ±500V High-Side Current Sense

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7.2.5 High-Voltage Instrumentation Amplifier

Differential measurements are common in a wide variety of applications. When high input impedance is
needed in a differential measurement, an instrumentation amplifier can be employed. The challenge is that
readily available, monolithic instrumentation amplifiers offer a limited input common-mode voltage range. Figure
7-6 shows a discrete instrumentation amplifier featuring the OPAx596. The circuit is valuable when a high
impedance, differential measurement is required in the presence of very high common-mode.
50V

+
–
VIN+ +60V
+ OPA596

10m +60V –
VIN
+ OPA596 25V
– 1k
499k
1A 25V
VREF
499k 1k

Load

Figure 7-6. High-Voltage Instrumentation Amplifier

7.2.6 Composite Amplifier

The OPAx596 offers low input offset voltage and input offset drift. In some applications, however, even higher
precision is required. Figure 7-7 shows how to greatly improve the dc precision of the OPAx596. The OPA186
is a 24V, zero-drift op amps offered at a competitive cost and can be paired with the OPAx596 in a composite
amplifier configuration to create a high precision amplifier with high voltage output capability.
The first amplifier, OPA186, corrects the offset of the second amplifier, OPAx596. The gain of the composite
amplifier is set by RF and RG, such that the gain is equal to RF / RG + 1. In this application, the overall gain
of the circuit is 100V/V. Adding gain to the OPAx596 through R1 and R2 improves the overall bandwidth of
the composite amplifier by reducing the gain burden on the OPA186. Increasing the gain too much on the
second amplifier, however, reduces the closed loop bandwidth and can negatively affect phase margin. Special
considerations for stability are warranted when building composite amplifiers.
1k 99k

1nF

AVDD 12V
– 100 42.5V
100 + OPA596
PDAC + OPA186 VOUT

12V –
42.5V
AVSS
1k 14k

Figure 7-7. High-Precision, High-Voltage Output Composite Amplifier

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7.3 Power Supply Recommendations

The OPAx596 operates from power supplies up to ±42.5V (85V), and as little as ±4V (8V) with excellent
performance. Most behavior remains unchanged throughout the full operating voltage range, but Section 5.6
shows parameters that vary with operating voltage. A power-supply bypass capacitor of at least 0.1µF is
required for proper operation. Ensure that the capacitor voltage is rated for high voltage across the full operating
temperature range. The OPAx596 can be powered with asymmetrical supplies to optimize power dissipation in
applications that do not require an equal positive and negative output voltage swing.
7.4 Layout
7.4.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including
the following guidelines:
• Noise can propagate into analog circuitry through the power pins of the op amp and the circuit as a
whole. Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground. Place
the capacitors as close to the device as possible. A single bypass capacitor from V+ to ground is sufficient for
single supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Physically separate digital and analog
grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Clean the PCB following board assembly for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, bake the PCB assembly to remove moisture
introduced into the device packaging during the cleaning process. A low temperature, post cleaning bake
at 85°C for 30 minutes is sufficient for most circumstances.
[Link] Thermal Considerations
Through normal operation, the op amps can self-heat. Self-heating is a natural increase in the die junction
temperature that occurs in every amplifier. This self-heating is a result of several factors, including quiescent
power consumption, package thermal resistance, PCB layout, and device operating conditions.
Operate the OPAx596 within the rated junction temperature, TJ, range to avoid thermal shutdown. Use the
Equation 3 to determine the estimated TJ

TJ = PD × RθJA + TA (3)

In a quiescent state, PD is given by the product of the power supply and the quiescent current of the op
amp. Equation 4 shows the calculation of TJ for the OPAx596 assuming an 85V power supply is used and an
operating temperature of 25°C.

C
TJ = 85V × 490μA × 165.4° W + 25°C (4)

TJ = 31.89°C (5)

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The low power consumption of the OPAx596 causes minimal self-heating even in a small SOT23-5 package as
given by Equation 5. In a loaded condition, PD is equal to addition of the quiescent power, PDQ and the power
dissipated by the output stage, PDL. The worst-case condition is given when the output voltage is equal to ½
of either supply rail (assuming symmetrical supplies, V+ and V-). In a worst-case condition, PDL is given by
Equation 6.

2
V+
PDL = 4 × R (6)
L

For example, assume the OPAx596 is powered with bipolar ±42.5V power supplies and drives a 5kΩ load, RL, to
ground. The maximum increase in TJ is expected to be about 22°C as given by Equation 7. In this example, to
keep the op amp within the Absolute Maximum Ratings, operate in TA well under 128°C to account for different
factors. The calculation for a 5kΩ load is depicted visually in Figure 7-8.

∆ TJ = 41.7mW + 90.3mW × 165.4 °C

W (7)

For high-voltage amplifiers such as the OPAx596, the junction temperature can easily be tens of degrees
higher than the ambient temperature in a quiescent (unloaded) condition. As shown by Equation 3, the junction
temperature depends on the thermal properties of the package, as expressed by the junction-to-ambient thermal
resistance (RϴJA). If the device then begins to drive a heavy load, the junction temperature can rise and trip
the thermal-shutdown circuit. Figure 7-8 shows the maximum output voltage versus ambient temperature to
avoid exceeding the Absolute Maximum Ratings in both loaded and unloaded conditions for the SOT23-5
package version of the OPA596. The curve assumes a typical quiescent current and does not account for any
temperature variation of quiescent current.
100
90
80
70
Supply Voltage (V)

60
50
40
30
20 Unloaded
10 Loaded (2k )
Loaded (10k )
0
85 95 105 115 125 135 145
Ambient Temperature ( C)

Figure 7-8. OPA596 (SOT23-5) Thermal Safe Operating Area

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7.4.2 Layout Example

RF

RG V+
–
VOUT
VIN + OPA596
V−

Figure 7-9. Schematic Representation of Noninverting Configuration

V+

0.1µF

OUT V+
0.1µF
VOUT
V V

RF

VIN IN+ IN

RG

Figure 7-10. Board Layout for Noninverting Configuration of the SOT23-5 Package

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
8.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
8.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

8.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (June 2024) to Revision A (February 2025) Page
• Changed data sheet status from advanced information (preview) to production mix (active and preview)........1
• Added OP2596 preview D (SOIC, 8) package to the Device Information table ................................................ 1

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

[Link] 7-Oct-2025

PACKAGING INFORMATION

Orderable part number Status Material type Package | Pins Package qty | Carrier RoHS Lead finish/ MSL rating/ Op temp (°C) Part marking
(1) (2) (3) Ball material Peak reflow (6)
(4) (5)

OPA596DBVR Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 O596
OPA596DBVR.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 O596
OPA596DBVT Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 O596
OPA596DBVT.A Active Production SOT-23 (DBV) | 5 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -40 to 125 O596

(1)
Status: For more details on status, see our product life cycle.

(2)
Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance,
reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional
waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind.

(3)
RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition.

(4)
Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum
column width.

(5)
MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown.
Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board.

(6)
Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part.

Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two
combined represent the entire part marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and
makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative
and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers
and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 31-Mar-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA596DBVR SOT-23 DBV 5 3000 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
OPA596DBVT SOT-23 DBV 5 250 180.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 31-Mar-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA596DBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
OPA596DBVT SOT-23 DBV 5 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

3.0 C
2.6
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1 5

2X 0.95 (0.1)
3.05
2.75
1.9 1.9
2
(0.15)

4
3
0.5
5X
0.3
0.15
0.2 C A B NOTE 5 4X 0 -15 (1.1) TYP
0.00
1.45
0.90
4X 4 -15

0.25
GAGE PLANE 0.22
TYP
0.08

8
TYP 0.6
0 TYP SEATING PLANE
0.3

4214839/K 08/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.

[Link]
 EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
(1.9)
2
2X (0.95)

3 4

(R0.05) TYP (2.6)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4214839/K 08/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR

PKG
5X (1.1)
1
5
5X (0.6)

SYMM
2 (1.9)
2X(0.95)

3 4

(R0.05) TYP
(2.6)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X

4214839/K 08/2024

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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