HT46R53A/HT46R54A

A/D Type 8-Bit OTP MCU

Technical Document
· Tools Information
· FAQs
· Application Note
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0084E NiMH Battery Charger Demo Board - Using the HT46R52

Features
· Low-power fully static CMOS design · On-chip crystal and RC oscillator
· Operating voltage: · 6-level subroutine nesting
fSYS=4MHz: 2.2V~5.5V · Watchdog Timer
fSYS=8MHz: 3.3V~5.5V · Low voltage reset function
· Program Memory:
· HALT function
2K´15 OTP (HT46R53A)
· Up to 0.5ms instruction cycle with 8MHz system clock
4K´15 OTP (HT46R54A)
at VDD=5V
· Data memory:
· 1-channel 8-bit PWM output shared with an I/O line
192´8 RAM (HT46R53A)
· PFD function
280´8 RAM (HT46R54A)
· Bit manipulation instruction
· A/D converter: 12bits´8Ch
· Table read instruction
External A/D converter reference voltage input pin
· 22 bidirectional I/O lines · 63 powerful instructions

· 1 interrupt input shared with an I/O line · All instructions in one or two machine cycles

· 8-bit programmable timer/event counter with over- · 28-pin SKDIP/SOP package

flow interrupt and 7-stage prescaler

General Description
The HT46R53A/HT46R54A are 8-bit high performance, verter, Pulse Width Modulation function, HALT and
RISC architecture microcontroller devices specifically wake-up functions, watchdog timer, as well as low cost,
designed for A/D applications that interface directly to enhance the versatility of these devices to suit a wide
analog signals, such as those from sensors. The advan- range of A/D application possibilities such as sensor
tages of low power consumption, I/O flexibility, timer signal processing, chargers, motor driving, industrial
functions, oscillator options, multi-channel A/D con- control, consumer products, subsystem controllers, etc.

Rev. 1.00 1 August 24, 2006

 HT46R53A/HT46R54A

Block Diagram

IN T

M P r e s c a le r fS Y S
T M R C
In te rru p t U
S T A C K T M R X T M R
C ir c u it
P ro g ra m P ro g ra m
R O M C o u n te r E N /D IS
IN T C W D T S
M fS Y S /4
W D T
P r e s c a le r W D T U
X W D T O S C
In s tr u c tio n
R e g is te r B P M P M P A P A 0 ~ P A 2 , P A 3 /P F D
D A T A P o rt A
U P A 4 /T M R , P A 5 /IN T
X M e m o ry P A C P A 6 ~ P A 7

M V D D
A /D C o n v e rte r U
X V R E F
M U X P B P o rt B
In s tr u c tio n P B 0 /A N 0 ~ P B 7 /A N 7
D e c o d e r P B C

A L U S T A T U S
P C P o rt C
T im in g S h ifte r P C 0 ~ P C 4
G e n e ra to r P C C

O S C 2 O S C 1 P D P o rt D
A C C P D 0 /P W M
R E S O p tio n R O M P D C
V D D O T P O n ly
V S S

Pin Assignment

P A 3 /P F D 1 2 8 P A 4 /T M R
P A 2 2 2 7 P A 5 /IN T
P A 1 3 2 6 P A 6
P A 0 4 2 5 P A 7
P D 0 /P W M 5 2 4 O S C 2
V R E F 6 2 3 O S C 1
V S S 7 2 2 V D D
P B 0 /A N 0 8 2 1 R E S
P B 1 /A N 1 9 2 0 P B 7 /A N 7
P B 2 /A N 2 1 0 1 9 P B 6 /A N 6
P B 3 /A N 3 1 1 1 8 P B 5 /A N 5
P C 0 1 2 1 7 P B 4 /A N 4
P C 1 1 3 1 6 P C 4
P C 2 1 4 1 5 P C 3

H T 4 6 R 5 3 A /H T 4 R 5 4 A
2 8 S K D IP -A /S O P -A

Rev. 1.00 2 August 24, 2006

 HT46R53A/HT46R54A

Pin Description
Pin Name I/O Options Description
Bidirectional 8-bit input/output port. Each individual bit on this port can be
PA0~PA2
configured as a wake-up input by configuration option. Software instruc-
PA3/PFD Pull-high
tions determine if the pin is a CMOS output or Schmitt trigger input. Config-
PA4/TMR I/O Wake-up
uration options determine which pin on this port have pull-high resistors.
PA5/INT PA3 or PFD
The PFD, TMR and external interrupt input are pin-shared with PA3, PA4,
PA6~PA7
and PA5 respectively.
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with or without pull-high resistor.
PB0/AN0~ Configuration options determine which pin on this port have pull-high resis-
I/O Pull-high
PB7/AN7 tors. PB is pin-shared with the A/D input pins. The A/D inputs are selected
via software instructions Once selected as an A/D input, the I/O function
and pull-high resistor functions are disabled automatically.
Bidirectional 5-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with or without pull-high resistor.
PC0~PC4 I/O Pull-high
Configuration options determine which pin on this port have pull-high resis-
tors.
Bidirectional 1-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with or without pull-high resistor. One
Pull-high
PD0/PWM I/O configuration option determines which pin on this port has pull-high resis-
PD0 or PWM
tor. PD0 is pin-shared with the PWM output selected via configuration op-
tion.
OSC1, OSC2 are connected to an external RC network or external crystal
OSC1 I (determined by configuration option) for the internal system clock. For ex-
Crystal or RC
OSC2 O ternal RC system clock operation, OSC2 is an output pin for 1/4 system
clock.
RES I ¾ Schmitt trigger reset input, active low.

VDD ¾ ¾ Positive power supply

VSS ¾ ¾ Negative power supply, ground

A/D Converter Reference Input voltage pins. Connect this pin to the de-
VREF I ¾
sired A/D reference voltage.

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW

Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

Rev. 1.00 3 August 24, 2006

 HT46R53A/HT46R54A

D.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions
fSYS=4MHz 2.2 ¾ 5.5 V
VDD Operating Voltage ¾
fSYS=8MHz 3.3 ¾ 5.5 V
3V No load, fSYS=4MHz ¾ 0.6 1.5 mA
IDD1 Operating Current (Crystal OSC)
5V ADC disabled ¾ 2 4 mA
3V No load, fSYS=4MHz ¾ 0.8 1.5 mA
IDD2 Operating Current (RC OSC)
5V ADC disabled ¾ 2.5 4 mA
No load, fSYS=8MHz
IDD3 Operating Current 5V ¾ 4 8 mA
ADC disabled
3V ¾ ¾ 5 mA
ISTB1 Standby Current (WDT Enabled) No load, system HALT
5V ¾ ¾ 10 mA

Standby Current 3V ¾ ¾ 1 mA
ISTB2 No load, system HALT
(WDT & AD Disabled) 5V ¾ ¾ 2 mA
Input Low Voltage for I/O Ports,
VIL1 ¾ ¾ 0 ¾ 0.3VDD V
TMR and INT
Input High Voltage for I/O Ports,
VIH1 ¾ ¾ 0.7VDD ¾ VDD V
TMR and INT
VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V
VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V
VLVR Low Voltage Reset Voltage ¾ Configuration option: 3V 2.7 3 3.3 V
3V 4 8 ¾ mA
IOL I/O Port Sink Current VOL=0.1VDD
5V 10 20 ¾ mA
3V -2 -4 ¾ mA
IOH I/O Port Source Current VOH=0.9VDD
5V -5 -10 ¾ mA
3V 20 60 100 kW
RPH Pull-high Resistance of I/O Ports ¾
5V 10 30 50 kW
VAD A/D Input Voltage ¾ ¾ 0 ¾ VREF V
ADC Input Reference Voltage
VREF ¾ ¾ 1.2 ¾ VDD V
Range
DNL ADC Differential Non-Linear ¾ ¾ ¾ ¾ ±2 LSB
INL ADC Integral Non-Linear ¾ ¾ ¾ ±2.5 ±4 LSB
RESOLU Resolution ¾ ¾ ¾ ¾ 12 Bits

Additional Power Consumption 3V ¾ 0.5 1 mA

IADC ¾
if A/D Converter is Used 5V ¾ 1.5 3 mA

Rev. 1.00 4 August 24, 2006

 HT46R53A/HT46R54A

A.C. Characteristics Ta=25°C

Test Conditions
Symbol Parameter Min. Typ. Max. Unit
VDD Conditions

¾ 2.2V~5.5V 400 ¾ 4000 kHz

fSYS System Clock (Crystal OSC)
¾ 3.3V~5.5V 400 ¾ 8000 kHz

¾ 2.2V~5.5V 0 ¾ 4000 kHz

fTIMER Timer I/P Frequency (TMR)
¾ 3.3V~5.5V 0 ¾ 8000 kHz

3V ¾ 45 90 180 ms
tWDTOSC Watchdog Oscillator Period
5V ¾ 32 65 130 ms
tRES External Reset Low Pulse Width ¾ ¾ 1 ¾ ¾ ms
tSST System Start-up Timer Period ¾ Wake-up from HALT ¾ 1024 ¾ tSYS

tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms

tAD A/D Clock Period ¾ ¾ 1 ¾ ¾ ms
tADC A/D Conversion Time ¾ ¾ ¾ 80 ¾ tAD

tADCS A/D Sampling Time ¾ ¾ ¾ 32 ¾ tAD

Note: tSYS=1/fSYS

Rev. 1.00 5 August 24, 2006

 HT46R53A/HT46R54A

Functional Description
Execution Flow wide and controls the sequence in which the instructions
The system clock for the microcontroller is derived from stored in the program ROM are executed. The contents
either a crystal or an RC oscillator. The system clock is of the PC can specify a maximum of 4096 addresses.
internally divided into four non-overlapping clocks. One After accessing a program memory word to fetch an in-
instruction cycle consists of 4 system clock cycles. struction code, the contents of the program counter are
Instruction fetching and execution are pipelined in such incremented by one. The program counter then points to
a way that a fetch and decoding takes an instruction cy- the memory word containing the next instruction code.
cle while execution take the next instruction cycle. The When executing a jump instruction, conditional skip ex-
pipelining scheme causes each instruction to effectively ecution, loading register, subroutine call or return from
execute in a cycle. If an instruction changes the program subroutine, initial reset, internal interrupt, external inter-
counter, two cycles are required to complete the instruc- rupt or return from interrupts, the PC manipulates the
tion. program transfer by loading the address corresponding
to each instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
For HT46R53A, the program counter (PC) is 11 bits the condition is met, the next instruction, fetched during
wide and controls the sequence in which the instructions the current instruction execution, is discarded and a
stored in the program ROM are executed. The contents dummy cycle replaces it to get the proper instruction.
of the PC can specify a maximum of 2048 addresses. Otherwise proceed to the next instruction.
For HT46R54A, the program counter (PC) is 12 bits

T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4
S y s te m C lo c k

O S C 2 ( R C o n ly )

P C P C P C + 1 P C + 2

F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 ) F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )

Execution Flow

Program Counter
Mode
*b11 *b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0
Initial Reset 0 0 0 0 0 0 0 0 0 0 0 0
External Interrupt 0 0 0 0 0 0 0 0 0 1 0 0
Timer/Event Counter Overflow 0 0 0 0 0 0 0 0 1 0 0 0
A/D Converter Interrupt 0 0 0 0 0 0 0 0 1 1 0 0
Skip Program Counter+2
Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0

Program Counter

Note: *b11~*b0: Program counter bits

S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits, PC11~PC8: Original PC counter, remain unchanged
For the HT46R53A, the program counter is 11 bits wide (b0~b10), the b11 column in the table are not applica-
ble.

Rev. 1.00 6 August 24, 2006

 HT46R53A/HT46R54A

The lower byte of the PC (PCL) is a readable and · Location 004H

writeable register (06H). Moving data into the PCL per- This location is reserved for the external interrupt ser-
forms a short jump. The destination is within 256 loca- vice program. If the INT input pin is activated, the in-
tions. terrupt is enabled and the stack is not full, the program
begins execution at this location.
When a control transfer takes place, an additional
· Location 008H
dummy cycle is required.
This location is reserved for the timer/event counter
interrupt service program. If a timer interrupt results
Program Memory - EPROM
from a timer/event counter overflow, and the interrupt
The program memory is used to store the program in- is enabled and the stack is not full, the program begins
structions which are to be executed. It also contains execution at location 008H.
data, table, and interrupt entries, and is organized into · Location 00CH
2048´15 (HT46R53A), or 4096´15 (HT46R54A) bits, Location 00CH is reserved for the A/D converter inter-
addressed by the Program Counter and table pointer. rupt service program. If an A/D converter interrupt re-
Certain locations in the ROM are reserved for special sults from an end of A/D conversion, and if the
interrupt is enabled and the stack is not full, the pro-
usage:
gram begins execution at location 00CH.
· Location 000H
· Table location
This location is reserved for program initialization. Af-
Any location in the program memory can be used as
ter a chip reset, the program always begins execution
at location 000H. look-up tables. The instructions ²TABRDC [m]² (the
current page) and ²TABRDL [m]² (the last page) trans-
0 0 0 H 0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m D e v ic e In itia liz a tio n P r o g r a m

0 0 4 H 0 0 4 H
E x te r n a l In te r r u p t S u b r o u tin e E x te r n a l In te r r u p t S u b r o u tin e
0 0 8 H 0 0 8 H
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e

0 0 C H 0 0 C H
A /D C o n v e r te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e
0 1 0 H 0 1 0 H
0 1 4 H P ro g ra m 0 1 4 H P ro g ra m
M e m o ry M e m o ry
0 1 8 H 0 1 8 H

n 0 0 H n 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s ) L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H n F F H

7 0 0 H F 0 0 H

L o o k - u p T a b le ( 2 5 6 w o r d s ) L o o k - u p T a b le ( 2 5 6 w o r d s )
7 F F H F F F H
1 5 b its 1 5 b its
H T 4 6 R 5 3 A H T 4 6 R 5 4 A
N o te : n = 0 ~ 7 N o te : n = 0 ~ F

Program Memory

Table Location
Instruction
b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
TABRDC [m] P11 P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
TABRDL [m] 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0

Table Location

Note: b11~b0: Table location bits

P11~P8: Current program counter bits
@7~@0: Table pointer bits
For the HT46R53A, since the program counter is 11 bits wide (b0~b10), the b11 columns in the table are not
applicable
For the HT46R54A, the TABRDC program counter is 12 bits wide. From b0~b11

Rev. 1.00 7 August 24, 2006

 HT46R53A/HT46R54A

fer the contents of the lower-order byte to the speci- for data and control information under instruction com-
fied data memory, and the higher-order byte to TBLH mands. All of the data memory areas can handle arith-
(08H). The lower-order byte table pointer TBLP (07H) metic, logic, increment, decrement and rotate
are read/write registers, which indicate the table loca- operations directly. Except for some dedicated bits,
tions. Before accessing the table, the location has to
each bit in the data memory can be set and reset by
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (interrupt ²SET [m].i² and ²CLR [m].i². They are also indirectly ac-
service routine) both employ the table read instruc- cessible through memory pointer registers (MP0;01H or
tion, the contents of the TBLH in the main routine are MP1;03H).
likely to be changed by the table read instruction used In case of HT46R54A, the unused space before 28H is
in the ISR. Errors can occur. Given this, using the ta-
reserved for future expanded usage and reading these
ble read instruction in the main routine and the ISR si-
multaneously should be avoided. However, if the table locations will return the result ²00H². The space before
read instruction has to be applied in both main routine 40H is overlapping in each bank. The general purpose
and the ISR, the interrupt should be disabled prior to data memory, addressed from 28H to FFH (Bank0;
the table read instruction. It will not be enabled until BP=00H) and from 40H to 7FH (Bank1; BP=01H), are
the TBLH in the main routine has been backed-up. All used for data and control information under instruction
table related instructions require 2 cycles to complete commands. All of the data memory areas can handle
the operation. arithmetic, logic, increment, decrement and rotate oper-
ations directly. Except for some dedicated bits, each bit
Stack Register - STACK
in the data memory can be set and reset by ²SET [m].i²
This is a special part of the memory which is used to and ²CLR [m].i². They are also indirectly accessible
save the contents of the program counter only. The through memory pointer registers (MP0;01H or
stack is organized into 6 levels and is neither part of the MP1;03H). After first setting up BP to the value of ²01H²
data nor part of the program space, and is neither read- to access Bank1, this bank must then be accessed indi-
able nor writeable. The activated level is indexed by the rectly using the memory pointer MP1. With BP set to a
stack pointer (SP) and is neither readable nor writeable.
value of ²01H², using MP1 to indirectly read or write to
At the state of a subroutine call or an interrupt acknowl-
the data memory areas with addresses at 40H will result
edgment, the contents of the program counter are
in operations to Bank1. Directly addressing the data
pushed onto the stack. At the end of the subroutine or an
memory will always result in Bank0 being accessed irre-
interrupt routine, signaled by a return instruction (RET or
spective of the value of BP.
RETI), the program counter is restored to its previous
value from the stack. After a chip reset, the SP will point
Indirect Addressing Register
to the top of the stack.
Location 00H and 02H are indirect addressing registers
If the stack is full and a non-masked interrupt takes
that are not physically implemented. Any read/write op-
place, the interrupt request flag will be recorded but the
eration of [00H] ([02H]) will access the data memory
acknowledge signal will be inhibited. When the stack
pointed to by MP0 (MP1). Reading location 00H (02H)
pointer is decremented (by RET or RETI), the interrupt is
itself indirectly will return the result ²00H². Writing indi-
serviced. This feature prevents stack overflow, allowing
rectly results in no operation. The memory pointer regis-
the programmer to use the structure more easily. If the
ters (MP0 and MP1) are 8-bit registers.
stack is full and a ²CALL² is subsequently executed,
stack overflow occurs and the first entry will be lost (only
Accumulator - ACC
the most recent 6 return addresses are stored).
The accumulator closely relates to ALU operations. It is
Data Memory - RAM also mapped to location ²05H² of the data memory
which can operate with immediate data. The data move-
The data memory (RAM) is designed with 217´8 bits
ment between two data memories has to pass through
(HT46R53A), 306´8 bits (HT46R54A), and is divided
the accumulator.
into two functional groups, namely; special function reg-
isters (25´8 bits for HT46R53A, 26´8 bits for Arithmetic and Logic Unit - ALU
HT46R54A) and general purpose data memory
(192´8bit for HT46R53A, 280´8bit (Bank0 216´8 bits This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
and Bank1 64´8 bits) for HT46R54A) most of which are
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
readable/writable, although some are read only.
· Logic operations (AND, OR, XOR, CPL)
In case of HT46R53A, the unused space before 28H is
· Rotation (RL, RR, RLC, RRC)
reserved for future expanded usage and reading these
locations will return the result ²00H². The general pur- · Increment and Decrement (INC, DEC)
pose data memory, addressed from 28H to E7H, is used · Branch decision (SZ, SNZ, SIZ, SDZ ....)

Rev. 1.00 8 August 24, 2006

 HT46R53A/HT46R54A

H T 4 6 R 5 3 A H T 4 6 R 5 4 A
0 0 H In d ir e c t A d d r e s s in g R e g is te r 0 0 0 H In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H M P 0 0 1 H M P 0
0 2 H In d ir e c t A d d r e s s in g R e g is te r 1 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H M P 1 0 3 H M P 1
0 4 H 0 4 H B P
0 5 H A C C 0 5 H A C C
0 6 H P C L 0 6 H P C L
0 7 H T B L P 0 7 H T B L P
0 8 H T B L H 0 8 H T B L H
0 9 H 0 9 H
0 A H S T A T U S 0 A H S T A T U S
0 B H IN T C 0 B H IN T C
0 C H 0 C H
0 D H T M R 0 D H T M R
0 E H T M R C 0 E H T M R C
0 F H 0 F H
1 0 H 1 0 H
1 1 H S p e c ia l P u r p o s e 1 1 H S p e c ia l P u r p o s e
1 2 H P A D a ta M e m o ry 1 2 H P A D a ta M e m o ry
1 3 H P A C 1 3 H P A C
1 4 H P B 1 4 H P B
1 5 H P B C 1 5 H P B C
1 6 H P C 1 6 H P C
1 7 H P C C 1 7 H P C C
1 8 H P D 1 8 H P D
1 9 H P D C 1 9 H P D C
1 A H P W M 1 A H P W M
1 B H 1 B H
1 C H 1 C H
1 D H 1 D H
1 E H 1 E H
1 F H 1 F H
2 0 H A D R L 2 0 H A D R L
2 1 H A D R H 2 1 H A D R H
2 2 H A D C R 2 2 H A D C R
2 3 H A C S R 2 3 H A C S R
2 4 H 2 4 H
: U n u s e d : U n u s e d

2 7 H R e a d a s "0 0 " 2 7 H R e a d a s "0 0 "

2 8 H 2 8 H
G e n e ra l P u rp o s e G e n e ra l P u rp o s e
4 0 H G e n e r a l P u rp o s e
D a ta M e m o ry D a ta M e m o ry
(1 9 2 B y te s ) (2 1 6 B y te s ) D a ta M e m o ry
E 7 H F F H 7 F H (6 4 B y te s )
B a n k 1

RAM Mapping

The ALU not only saves the results of a data operation tions related to the status register may give different re-
but also changes the status register. sults from those intended. The TO flag can be affected
only by system power-up, a WDT time-out or executing
Status Register - STATUS the ²HALT² or ²CLR WDT² instruction. The PDF flag can
This 8-bit register (0AH) contains the zero flag (Z), carry be affected only by executing the ²HALT² or ²CLR
flag (C), auxiliary carry flag (AC), overflow flag (OV), WDT² instruction or a system power-up.
power down flag (PDF), and watchdog time-out flag The Z, OV, AC, and C flags reflect the status of the latest
(TO). It also records the status information and controls operations. On entering the interrupt sequence or exe-
the operation sequence. cuting the subroutine call, the status register will not be
With the exception of the TO and PDF flags, bits in the automatically pushed onto the stack. If the contents of
status register can be altered by instructions like most the status is important, and if the subroutine is likely to
other registers. Any data written into the status register corrupt the status register, the programmer should take
will not change the TO and PDF flags. Addition opera- precautions and save it properly.

Rev. 1.00 9 August 24, 2006

 HT46R53A/HT46R54A

Bit No. Label Function

C is set if an operation results in a carry during an addition operation or if a borrow does not
0 C take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
1 AC
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
3 OV
highest-order bit, or vice versa; otherwise OV is cleared.

PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by
4 PDF
executing the ²HALT² instruction.

TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is

5 TO
set by a WDT time-out.
6~7 ¾ Unused bit, read as ²0²

Status (0AH) Register

Interrupts a branch to a subroutine at specified location in the pro-

gram memory. Only the program counter is pushed onto
The device provides an external interrupt, an internal
the stack. If the contents of the register or status register
timer/event counter interrupt, and an A/D converter in-
(STATUS) are altered by the interrupt service program
terrupt. The interrupt control register (INTC;0BH) con-
which corrupts the desired control sequence, the con-
tains the interrupt control bits to set the enable/disable
tents should be saved in advance.
and the interrupt request flags.
External interrupts are triggered by a high to low transi-
Once an interrupt subroutine is serviced, all the other in-
tion of INT and the related interrupt request flag (EIF; bit
terrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other 4 of the INTC) will be set. When the interrupt is enabled,
interrupt requests may occur during this interval but only the stack is not full and the external interrupt is active, a
the interrupt request flag is recorded. If a certain inter- subroutine call to location ²04H² will occur. The interrupt
rupt requires servicing within the service routine, the request flag (EIF) and EMI bits will be cleared to disable
EMI bit and the corresponding bit of the INTC may be other interrupts.
set to allow interrupt nesting. If the stack is full, the inter- The internal Timer/Event Counter interrupt is initialized
rupt request will not be acknowledged, even if the re- by setting the Timer/Event Counter interrupt request flag
lated interrupt is enabled, until the SP is decremented. If (TF; bit 5 of the INTC), which is normally caused by a
immediate service is desired, the stack must be pre- timer overflow. After the interrupt is enabled, and the
vented from becoming full. stack is not full, and the TF bit is set, a subroutine call to
All these kinds of interrupts have a wake-up capability. location ²08H² occurs. The related interrupt request flag
As an interrupt is serviced, a control transfer occurs by (TF) is reset, and the EMI bit is cleared to disable further
pushing the program counter onto the stack, followed by maskable interrupts.

Bit No. Label Function

0 EMI Controls the master (global) interrupt (1= enable; 0= disable)
1 EEI Controls the external interrupt (1= enable; 0= disable)
2 ETI Controls the Timer/Event Counter interrupt (1= enable; 0= disable)
3 EADI Control the A/D converter interrupt (1= enable; 0= disable)
4 EIF External interrupt request flag (1= active; 0= inactive)
5 TF Internal Timer/Event Counter request flag (1= active; 0= inactive)
6 ADF A/D converter request flag (1= active; 0= inactive)
For test mode used only.
7 ¾
Must be written as ²0²; otherwise may result in unpredictable operation.

INTC (0BH) Register

Rev. 1.00 10 August 24, 2006

 HT46R53A/HT46R54A

The A/D converter interrupt is initialized by setting the Both of them are designed for system clocks, namely
A/D converter request flag (ADF; bit 6 of the INTC), the external RC oscillator and the external Crystal oscil-
caused by an end of A/D conversion. When the interrupt lator, which are determined by options. No matter what
is enabled, the stack is not full and the ADF is set, a sub- oscillator type is selected, the signal provides the sys-
routine call to location ²0CH² will occur. The related in- tem clock. The HALT mode stops the system oscillator
terrupt request flag (ADF) will be reset and the EMI bit and ignores an external signal to conserve power.
cleared to disable further interrupts. If an RC oscillator is used, an external resistor between
During the execution of an interrupt subroutine, other in- OSC1 and VSS is required and the resistance must
terrupt acknowledgments are held until the ²RETI² in- range from 30kW to 750kW. The system clock, divided
struction is executed or the EMI bit and the related by 4, is available on OSC2 with pull-high resistor, which
can be used to synchronize external logic. The RC os-
interrupt control bit are set to 1 (if the stack is not full). To
cillator provides the most cost effective solution. How-
return from the interrupt subroutine, ²RET² or ²RETI²
ever, the frequency of oscillation may vary with VDD,
may be invoked. RETI will set the EMI bit to enable an in- temperatures and the chip itself due to process varia-
terrupt service, but RET will not. tions. It is therefore not suitable for timing sensitive op-
Interrupts, occurring in the interval between the rising erations where an accurate oscillator frequency is
edges of two consecutive T2 pulses, will be serviced on desired.
the latter of the two T2 pulses, if the corresponding inter- If the Crystal oscillator is used, a crystal across OSC1
rupts are enabled. In the case of simultaneous requests and OSC2 is needed to provide the feedback and phase
the following table shows the priority that is applied. shift required for the oscillator, and no other external
These can be masked by resetting the EMI bit. components are required. Instead of a crystal, a resona-
tor can also be connected between OSC1 and OSC2 to
Interrupt Source Priority Vector
get a frequency reference, but two external capacitors in
External Interrupt 1 04H OSC1 and OSC2 are required (If the oscillator can be
Timer/Event Counter Overflow 2 08H disabled by options to conserve power).

A/D Converter Interrupt 3 0CH The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
EMI, EEI, ETI, and EADI are used to control the en- tem enters the power down mode, the system clock is
abling/disabling of interrupts. These bits prevent the re- stopped, but the WDT oscillator still works with a period of
quested interrupt from being serviced. Once the approximately 65ms at 5V. The WDT oscillator can be dis-
interrupt request flags (TF, EIF, and ADF) are set, they abled by option to conserve power.
will remain in the INTC register until the interrupts are
serviced or cleared by a software instruction. Watchdog Timer - WDT
It is recommended that a program does not use the The clock source of the WDT is implemented by a dedi-
²CALL subroutine² within the interrupt subroutine. In- cated RC oscillator (WDT oscillator) or instruction clock
terrupts often occur in an unpredictable manner or (system clock divided by 4) decided by options. This
need to be serviced immediately in some applications. timer is designed to prevent a software mal-function or
If only one stack is left and enabling the interrupt is not sequence jumping to an unknown location with unpre-
well controlled, the original control sequence will be dam- dictable results. The watchdog timer can be disabled by
aged once the ²CALL² operates in the interrupt subrou- an option. If the watchdog timer is disabled, all the exe-
tine. cutions related to the WDT result in no operation.
The WDT clock (fS) is further divided by an internal
Oscillator Configuration counter to give longer watchdog time-outs. In the case
There are two oscillator circuits in the microcontroller. of HT46R53A/Ht46R54A devices, the division ratio can
be varied by selecting different configuration options to
V D D
give 212 to 215 division ratio range.

4 7 0 p F Once an internal WDT oscillator (RC oscillator with pe-

O S C 1
riod of 65ms normally) is selected, it is divided by 216 to
O S C 1 get the time-out period of approximately 4.3s. This
time-out period may vary with temperature, VDD and
process variations.
O S C 2 O S C 2
fS Y S /4
If the WDT oscillator is disabled, the WDT clock may still
C r y s ta l O s c illa to r R C O s c illa to r come from the instruction clock and operate in the same
System Oscillator manner except that in the HALT state the WDT may stop
counting and lose its protecting purpose. In this situation

Rev. 1.00 11 August 24, 2006

 HT46R53A/HT46R54A

C L R W D T 1 F la g
C o n tro l
L o g ic
C L R W D T 2 F la g

1 o r 2 In s tr u c tio n s

C L R
fS Y S /4 W D T S o u rc e fS fS /2 8
C o n fig u r a tio n 8 - b it C o u n te r 7 - b it C o u n te r ¸ 2 W D T T im e - o u t
W D T O s c illa to r O p tio n (2 13/fS , 2 14/fS , 2 15/fS o r 2 1 6
/fS )

W D T D iv is io n
C o n fig u r a tio n O p tio n
fS /2 1 2 , fS /2 1 3 , fS /2 1 4 o r fS /2 1 5

Watchdog Timer

the logic can only be restarted by external logic. If the The system quits the HALT mode by way of an external
device operates in a noisy environment, using the reset, an interrupt, an external falling edge signal on port
on-chip RC oscillator (WDT OSC) is strongly recom- A or a WDT overflow. An external reset causes a device
mended, since the HALT will stop the system clock. initialization and the WDT overflow performs a ²warm
The WDT overflow under normal operation will initialize reset². After examining the TO and PDF flags, the cause
a ²chip reset² and set the status bit TO. Whereas in the for a chip reset can be determined. The PDF flag is
HALT mode, the overflow will initialize a ²warm reset² cleared by system power-up or by executing the ²CLR
wherein only the Program Counter and SP are reset to WDT² instruction and is set when executing the ²HALT²
zero. To clear the contents of the WDT, three methods instruction. On the other hand, the TO flag is set if the
are adopted; external reset (a low level to RES), soft- WDT time-out occurs, and causes a wake-up that only
ware instructions, or a HALT instruction. The software resets the Program Counter and SP, and leaves the oth-
instructions include ²CLR WDT² and the other set CLR ers in their original status.
WDT1 and CLR WDT2. Of these two types of instruc- The port A wake-up and interrupt methods can be con-
tion, only one can be active depending on the option - sidered as a continuation of normal execution. Each bit
²CLR WDT times selection option². If the ²CLR WDT² is in port A can be independently selected to wake up the
selected (i.e. CLRWDT times equal one), any execution device by options. Awakening from an I/O port stimulus,
of the CLR WDT instruction will clear the WDT. In case the program resumes execution of the next instruction.
On the other hand, awakening from an interrupt, two se-
²CLR WDT1² and ²CLR WDT2² are chosen (i.e.
quence may occur. If the related interrupt is disabled or
CLRWDT times equal two), these two instructions must
the interrupt is enabled but the stack is full, the program
be executed to clear the WDT; otherwise, the WDT may
resumes execution at the next instruction. But if the in-
reset the chip because of time-out.
terrupt is enabled, and the stack is not full, the regular in-
If the WDT division option is selected to fS/216, the WDT terrupt response takes place. When an interrupt request
time-out period is fixed to fS/216, because the ²CLR flag is set before entering the ²HALT² status, the system
WDT² or ²CLR WDT1² and ²CLR WDT2² instructions will cannot be awakened using that interrupt. If wake-up
clear the whole counter of the WDT. events occur, it takes 1024 tSYS (system clock period) to
resume normal operation. In other words, a dummy pe-
Power Down Operation - HALT riod is inserted after the wake-up. If the wake-up results
from an interrupt acknowledgment, the actual interrupt
The HALT mode is initialized by the ²HALT² instruction subroutine execution is delayed by more than one cycle.
and results in the following... However, if the Wake-up results in the next instruction
· The system oscillator is turned off but the WDT oscil- execution, the execution will be performed immediately
lator keeps running (if the WDT oscillator or the real after the dummy period is finished.
time clock is selected).
To minimize power consumption, all the I/O pins should
· The contents of the on-chip RAM and registers remain
be carefully managed before entering the HALT status.
unchanged
· The WDT and WDT prescaler will be cleared to zero. If
Reset
the WDT clock source is from the RTC/WDT oscilla-
tor, the WDT will remain active, and if the WDT clock There are three ways in which a reset may occur:
source is fSYS/4, the WDT will stop running. · RES reset during normal operation
· All of the I/O ports maintain their original status · RES reset during HALT
· The PDF flag is set and the TO flag is cleared
· WDT time-out reset during normal operation

Rev. 1.00 12 August 24, 2006

 HT46R53A/HT46R54A

The WDT time-out during HALT differs from other chip V D D

reset conditions, for it can perform a ²warm reset² that 0 .0 1 m F *

resets only the Program Counter and SP, leaving the
other circuits at their original state. Some registers re- 1 0 0 k W

main unaffected during any other reset conditions. Most R E S

registers are reset to the ²initial condition² when the re- 1 0 k W
set conditions are met. Examining the PDF and TO
flags, the program can distinguish between different 0 .1 m F *

²chip resets².
Reset Circuit
TO PDF RESET Conditions
0 0 RES reset during power-up Note: ²*² Make the length of the wiring, which is con-
nected to the RES pin as short as possible, to
u u RES reset during normal operation
avoid noise interference.
0 1 RES wake-up HALT
1 u WDT time-out during normal operation
V D D
1 1 WDT wake-up HALT
R E S tS S T + tO P D
Note: ²u² stands for ²unchanged²
S S T T im e - o u t
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an C h ip R e s e t

extra-delay of 1024 system clock pulses when the sys- Reset Timing Chart
tem reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state. When a system re-
set occurs, the SST delay is added during the reset pe- H A L T W a rm R e s e t
riod. Any wake-up from the HALT will enable the SST W D T
W D T
delay. An extra option load time delay is added during T im e - o u t
R e s e t
system reset (Power-up, WDT time-out at normal mode E x te rn a l
R E S
or RES reset). C o ld
R e s e t
The functional unit chip reset status are shown below. S S T
O S C 1 1 0 - b it R ip p le
Program Counter 000H C o u n te r

Interrupt Disable P o w e r - o n D e te c tio n

Prescaler, Divider Cleared
Reset Configuration
Clear. After master reset,
WDT
WDT begins counting
Timer/Event Counter Off
Input/Output Ports Input mode
Stack Pointer Points to the top of the stack

Rev. 1.00 13 August 24, 2006

 HT46R53A/HT46R54A

The register states are summarized below:

Reset WDT Time-out RES Reset RES Reset WDT Time-out
Register
(Power-on) (Normal Operation) (Normal Operation) (HALT) (HALT)*
MP0 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
MP1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
BP
---- ---0 ---- ---0 ---- ---0 ---- ---0 ---- ---u
(HT46R54A only)
ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Program Counter 0000H 0000H 0000H 0000H 0000H
TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
STATUS --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu
INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu
TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu
PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PB 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PBC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu
PC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu
PCC ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu
PD ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PDC ---- ---1 ---- ---1 ---- ---1 ---- ---1 ---- ---u
PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADRL xxxx ---- xxxx ---- xxxx ---- xxxx ---- uuuu ----
ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu
ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu
ACSR ---- --00 ---- --00 ---- --00 ---- --00 ---- --uu

Note: ²*² stands for ²warm reset²

²u² stands for ²unchanged²
²x² stands for ²unknown²

Rev. 1.00 14 August 24, 2006

 HT46R53A/HT46R54A

Timer/Event Counter
Only one timer/event counter (TMR) are implemented in ter register and issues an interrupt request, as in the
the microcontroller. The timer/event counter contains an other two modes, i.e., event and timer modes.
8-bit programmable count-up counter and the clock may To enable the counting operation, the Timer ON bit
come from an external source or an internal clock (TON; bit 4 of the TMRC) should be set to ²1². In the
source. An internal clock source comes from fSYS. The pulse width measurement mode, the TON is automati-
external clock input allows the user to count external cally cleared after the measurement cycle is completed.
events, measure time intervals or pulse widths, or to But in the other two modes, the TON can only be reset
generate an accurate time base. by instructions. The overflow of the timer/event counter
There are two registers related to the Timer/event coun- is one of the wake-up sources and can also be applied
ter; TMR (0DH), TMRC (0EH). Writing TMR will transfer to a PFD (Programmable Frequency Divider) output at
the specified data to timer/event counter registers. PA3 by options. No matter what the operation mode is,
Reading the TMR will read the contents of the writing a ²0² to ETI (bit2 of the INTC) disables the re-
timer/event counter. The TMRC is a control register, lated interrupt service. When the PFD function is se-
which defines the operating mode, counting enable or lected, executing ²SET [PA].3² instruction to enable the
disable and an active edge. PFD output and executing ²CLR [PA].3² instruction to
The TM0 and TM1 bits define the operation mode. The disable the PFD output.
event count mode is used to count external events, In the case of timer/event counter OFF condition, writing
which means that the clock source is from an external data to the timer/event counter preload register also re-
(TMR) pin. The timer mode functions as a normal timer loads that data to the timer/event counter. But if the
with the clock source coming from the internal selected timer/event counter is turn on, data written to the
clock source. Finally, the pulse width measurement timer/event counter is kept only in the timer/event coun-
mode can be used to count the high or low level duration ter preload register. The timer/event counter still contin-
of the external signal (TMR), and the counting is based ues its operation until an overflow occurs.
on the internal selected clock source.
When the timer/event counter (TMR) is read, the clock is
In the event count or timer mode, the timer/event coun- blocked to avoid errors, as this may results in a counting
ter starts counting at the current contents in the error. Blocking of the clock issue should be taken into
timer/event counter and ends at FFH. Once an overflow account by the programmer. It is strongly recommended
occurs, the counter is reloaded from the timer/event to load a desired value into the TMR register first, before
counter preload register, and generates an interrupt re- turning on the related timer/event counter, for proper op-
quest flag (TF; bit 5 of the INTC ). In the pulse width eration since the initial value of TMR is unknown. Due to
the timer/event scheme, the programmer should pay
measurement mode with the values of the TON and TE
special attention on the instruction to enable then dis-
bits equal to 1, after the TMR has received a transient
able the timer for the first time, whenever there is a need
from low to high (or high to low if the TE bit is ²0²), it will to use the timer/event function, to avoid unpredictable
start counting until the TMR returns to the original level result. After this procedure, the timer/event function can
and resets the TON. The measured result remains in the be operated normally.
timer/event counter even if the activated transient oc-
The bit0~bit2 of the TMRC can be used to define the
curs again. In other words, only 1-cycle measurement
pre-scaling stages of the internal clock sources of the
can be made until the TON is set. The cycle measure-
timer/event counter. The definitions are as shown. The
ment will re-operate as long as it receives further tran-
overflow signal of the timer/event counter can be used
sient pulse. In this operation mode, the timer/event
to generate the PFD signal. The timer prescaler is also
counter begins counting not according to the logic level
used as the PWM counter.
but to the transient edges. In the case of counter over-
flows, the counter is reloaded from the timer/event coun-
D a ta B u s

R e lo a d
P r e lo a d R e g is te r

P S C 2 ~ P S C 0 T M 1 T M 0

fS Y S 8 - s ta g e p r e s c a le r T im e r /E v e n t O v e r flo w
T im e r /E v e n t C o u n te r
M o d e C o n tro l C o u n te r to In te rru p t
T O N 8 - B it T im e r /E v e n t C o u n te r ¸ 2 P F D
T M R in p u t

T E
8-Bit Timer/Event Counter Structure

Rev. 1.00 15 August 24, 2006

 HT46R53A/HT46R54A

Bit No. Label Function

Defines the prescaler stages, PSC2, PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
0 PSC0 010: fINT=fSYS/4
1 PSC1 011: fINT=fSYS/8
2 PSC2 100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
Defines the TMR active edge of the timer/event counter:
In Event Counter Mode (TM1,TM0)=(0,1):
1:count on falling edge;
3 TE 0:count on rising edge
In Pulse Width measurement mode (TM1,TM0)=(1,1):
1: start counting on the rising edge, stop on the falling edge;
0: start counting on the falling edge, stop on the rising edge
4 TON Enable/disable timer counting (0=disable; 1=enable)
5 ¾ Unused bit, read as ²0²
Defines the operating mode, TM1, TM0:
01=Event count mode (external clock)
6 TM0
10=Timer mode (internal clock)
7 TM1
11=Pulse width measurement mode
00=Unused
TMRC (0EH) Register

Input/Output Ports
There are 22 bidirectional input/output lines in the tion, these ports are non-latching, that is, the inputs
microcontroller, labeled as PA, PB, PC and PD, which must be ready at the T2 rising edge of instruction ²MOV
are mapped to the data memory of [12H], [14H], [16H] A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
and [18H] respectively. All of these I/O ports can be all the data is latched and remains unchanged until the
used for input and output operations. For input opera- output latch is rewritten.

V D D

C o n tr o l B it
P u ll- h ig h
D a ta B u s D Q

P A 0 ~ P A 2
W r ite C o n tr o l R e g is te r C K Q
S P A 3 /P F D
P A 4 /T M R
C h ip R e s e t P A 5 /IN T
P A 6
R e a d C o n tr o l R e g is te r P A 7
D a ta B it P B 0 /A N 0 ~ P B 7 /A N 7
D Q P C 0 ~ P C 4
P D 0 /P W M
W r ite D a ta R e g is te r C K Q
S
M
U
X

[P A 3 , P F D ] M E N (P F D o r P W M )
U
o r [P D 0 ,P W M ] X
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly ) W a k e - u p O p tio n
IN T fo r P A 5 O n ly

Input/Output Ports

Rev. 1.00 16 August 24, 2006

 HT46R53A/HT46R54A

Each I/O line has its own control register (PAC, PBC, The definitions of the PFD control signal and PFD output
PCC, PDC) to control the input/output configuration. frequency are listed in the following table.
With this control register, CMOS output or Schmitt trig-
Timer
ger input with or without pull-high resistor structures can PA3 Data PA3 Pad
Timer Preload Frequency
be reconfigured dynamically under software control. To Register State
Value
function as an input, the corresponding latch of the con-
trol register must write ²1². The input source also de- OFF X 0 0 X
pends on the control register. If the control register bit is OFF X 1 U X
²1², the input will read the pad state. If the control regis-
ON N 0 0 X
ter bit is ²0², the contents of the latches will move to the
in t e rn a l b u s . Th e l at t er i s p o s s i bl e i n t h e ON N 1 PFD fINT/(2´(256-N))
²read-modify-write² instruction.
Note: ²X² stands for ²unused²
For output function, CMOS is the only configuration. ²U² stands for ²unknown²
These control registers are mapped to locations 13H, ²N² is the preload value for the timer/event
15H, 17H and 19H. counter
After a chip reset, these input/output lines remain at high ²fTMR² is the input clock frequency for the
levels or floating state (dependent on pull-high options). timer/event counter
Each bit of these input/output latches can be set or The PB can also be used as A/D converter inputs. The
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H, A/D function will be described later. There is a PWM
16H or 18H) instructions. function shared with PD0. If the PWM function is en-
Some instructions first input data and then follow the abled, the PWM signal will appear on PD0 (if PD0 is op-
output operations. For example, ²SET [m].i², ²CLR erating in output mode). The I/O functions of PD0 are as
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states shown.
into the CPU, execute the defined operations I/O I/P O/P I/P O/P
(bit-operation), and then write the results back to the Mode (Normal) (Normal) (PWM) (PWM)
latches or the accumulator. Logical Logical Logical
PD0 PWM
Each line of port A has the capability of waking-up the Input Output Input
device. Each I/O port has a pull-high option. Once the
It is recommended that unused or not bonded out I/O
pull-high option is selected, the I/O port has a pull-high
lines should be set as output pins by software instruction
resistor, otherwise, there¢s none. Take note that a non-
to avoid consuming power under input floating state.
pull-high I/O port operating in input mode will cause a
floating state. PWM
The PA3, PA4 and PA5 are pin-shared with PFD, TMR The microcontroller provides one channel PWM output
and INT pins respectively. shared with PD0. The PWM supports (7+1) or (6+2)
If the PFD option is selected, the output signal in output modes which are selected by configuration option. The
mode of PA3 will be the PFD signal generated by the PWM channel has their data register denoted as
timer/event counter overflow signal. The input mode al- PWM(1AH). The frequency source of the PWM counter
ways remain in its original functions. Once the PFD op- comes from fSYS. The PWM register is an 8-bit register.
tion is selected, the PFD output signal is controlled by The waveforms of the PWM outputs are as shown.
the PA3 data register only. The I/O functions of PA3 are Once the PD0 are selected as the PWM outputs and the
shown below. output function of the PD0 are enabled (PDC.0= ²0²),
writing ²1² to PD0 data register will enable the PWM out-
I/O I/P O/P I/P O/P
put function and writing ²0² will force the PD0 to stay at
Mode (Normal) (Normal) (PFD) (PFD)
²0².
Logical Logical Logical PFD
PA3 A (6+2) bits mode PWM cycle is divided into four modu-
Input Output Input (Timer on)
lation cycles (modulation cycle 0~modulation cycle 3).
Note: The PFD frequency is the timer/event counter Each modulation cycle has 64 PWM input clock period.
overflow frequency divided by 2. In a (6+2) bit PWM function, the contents of the PWM

Rev. 1.00 17 August 24, 2006

 HT46R53A/HT46R54A

register is divided into two groups. Group 1 of the PWM PWM.7~PWM.1. The group 2 is denoted by AC which is
register is denoted by DC which is the value of the value of PWM.0. In a (7+1) bits mode PWM cycle,
PWM.7~PWM.2. The group 2 is denoted by AC which is the duty cycle of each modulation cycle is shown in the
the value of PWM.1~PWM.0. In a (6+2) bits mode PWM table.
cycle, the duty cycle of each modulation cycle is shown
Parameter AC (0~1) Duty Cycle
in the table.
DC+1
Parameter AC (0~3) Duty Cycle i<AC
Modulation cycle i 128
DC+1 (i=0~1) DC
i<AC i³AC
Modulation cycle i 64 128
(i=0~3) DC
i³AC The modulation frequency, cycle frequency and cycle
64
duty of the PWM output signal are summarized in the
A (7+1) bits mode PWM cycle is divided into two modu- following table.
lation cycles (modulation cycle0~modulation cycle 1).
PWM PWM Cycle PWM Cycle
Each modulation cycle has 128 PWM input clock period.
Modulation Frequency Frequency Duty
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM fSYS/64 for (6+2) bits mode
fSYS/256 [PWM]/256
register is denoted by DC which is the value of fSYS/128 for (7+1) bits mode

fS Y S /2

[P W M ] = 1 0 0

P W M
2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4
[P W M ] = 1 0 1

P W M
2 6 /6 4 2 5 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 2

P W M
2 6 /6 4 2 6 /6 4 2 5 /6 4 2 5 /6 4 2 6 /6 4
[P W M ] = 1 0 3

P W M
2 6 /6 4 2 6 /6 4 2 6 /6 4 2 5 /6 4 2 6 /6 4

P W M m o d u la tio n p e r io d : 6 4 /fS Y S
M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 M o d u la tio n c y c le 2 M o d u la tio n c y c le 3 M o d u la tio n c y c le 0

P W M c y c le : 2 5 6 /fS Y S

(6+2) PWM Mode

fS Y S /2

[P W M ] = 1 0 0

P W M
5 0 /1 2 8 5 0 /1 2 8 5 0 /1 2 8
[P W M ] = 1 0 1

P W M
5 1 /1 2 8 5 0 /1 2 8 5 1 /1 2 8
[P W M ] = 1 0 2

P W M
5 1 /1 2 8 5 1 /1 2 8 5 1 /1 2 8
[P W M ] = 1 0 3

P W M
5 1 /1 2 8 5 2 /1 2 8
5 2 /1 2 8

P W M m o d u la tio n p e r io d : 1 2 8 /fS Y S

M o d u la tio n c y c le 0 M o d u la tio n c y c le 1 M o d u la tio n c y c le 0

P W M c y c le : 2 5 6 /fS Y S

(7+1) PWM Mode

Rev. 1.00 18 August 24, 2006

 HT46R53A/HT46R54A

A/D Converter Bit No. Label Function

The 8 channels 12-bit resolution A/D converter are im- Selects the A/D converter clock source
plemented in this microcontroller. 00= system clock/2
0 ADCS0
The A/D converter contains 4 special registers which 01= system clock/8
1 ADCS1
10= system clock/32
are; ADRL (20H), ADRH (21H), ADCR (22H) and ACSR
11= undefined
(23H). The ADRH and ADRL are A/D result register
higher-order byte and lower-order byte and are 2~6 ¾ Unused bit, read as ²0²
read-only. After the A/D conversion is completed, the 7 TEST For test mode used only
ADRH and ADRL should be read to get the conversion
result data. The ADCR is an A/D converter control regis- ACSR (23H) Register
ter, which defines the A/D channel number, analog
Bit No. Label Function
channel select, start A/D conversion control bit and the
end of A/D conversion flag. If the users want to start an 0 ACS0
A/D conversion, define PB configuration, select the con- 1 ACS1 Defines the analog channel select
verted analog channel, and give START bit a raising 2 ACS2
edge and falling edge (0®1®0). At the end of A/D con- Defines the port B configuration se-
3 PCR0
version, the EOCB bit is cleared and an A/D converter lect. If PCR0, PCR1 and PCR2 are all
4 PCR1
interrupt occurs (if the A/D converter interrupt is en- zero, the ADC circuit is powered off to
5 PCR2
abled). The ACSR is A/D clock setting register, which is reduce power consumption
used to select the A/D clock source. Indicates end of A/D conversion.
(0= end of A/D conversion)
The A/D converter control register is used to control the
Each time bits 3~5 change state the
A/D converter. The bit2~bit0 of the are used to select an
A/D should be initialised by issuing a
analog input channel. There are a total of eight channels 6 EOCB
START signal, otherwise the EOCB
to select. The bit5~bit3 of the ADCR are used to set PB flag may have an undefined condition.
configurations. PB can be an analog input or as digital See ²Important note for A/D initialis-
I/O line determined by these 3 bits. Once a PB line is se- ation².
lected as an analog input, the I/O functions and pull-high
Starts the A/D conversion.
resistor of this I/O line are disabled and the A/D con-
0®1®0= Start
verter circuit is powered on. The EOCB bit (bit6 of the 7 START
0®1= Reset A/D converter and set
ADCR) is end of A/D conversion flag. Check this bit to
EOCB to ²1².
know when the A/D conversion is completed.
The START bit of the ADCR is used to begin the conver- ADCR (22H) Register
sion of the A/D converter. Giving START bit a rising edge
ACS2 ACS1 ACS0 Analog Channel
and falling edge means that the A/D conversion has
started. In order to ensure that the A/D conversion is 0 0 0 AN0
completed, the START should remain at ²0² until the 0 0 1 AN1
EOCB is cleared to ²0² (end of A/D conversion). Bit 7 of 0 1 0 AN2
the ACSR register is used for test purposes only and
must not be used for other purposes by the application 0 1 1 AN3
program. Bit1 and bit0 of the ACSR register are used to 1 0 0 AN4
select the A/D clock source.
1 0 1 AN5
When the A/D conversion has completed, the A/D inter-
1 1 0 AN6
rupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1². 1 1 1 AN7

Important Note for A/D initialisation: Analog Input Channel Selection

Special care must be taken to initialise the A/D con-
Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un- ADRL
D3 D2 D1 D0 0 0 0 0
defined condition. An A/D initialisation is implemented (20H)
by setting the START bit high and then clearing it to zero ADRH
within 10 instruction cycles of the Port B channel selec- D11 D10 D9 D8 D7 D6 D5 D4
(21H)
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initialis- Note: D0~D11 is A/D conversion result data bit
ation is not required. LSB~MSB.

Rev. 1.00 19 August 24, 2006

 HT46R53A/HT46R54A

PCR2 PCR1 PCR0 7 6 5 4 3 2 1 0

0 0 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
0 0 1 PB7 PB6 PB5 PB4 PB3 PB2 PB1 AN0
0 1 0 PB7 PB6 PB5 PB4 PB3 PB2 AN1 AN0
0 1 1 PB7 PB6 PB5 PB4 PB3 AN2 AN1 AN0
1 0 0 PB7 PB6 PB5 PB4 AN3 AN2 AN1 AN0
1 0 1 PB7 PB6 PB5 AN4 AN3 AN2 AN1 AN0
1 1 0 PB7 PB6 AN5 AN4 AN3 AN2 AN1 AN0
1 1 1 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0

Port B Configuration

M in im u m o n e in s tr u c tio n c y c le n e e d e d , M a x im u m te n in s tr u c tio n c y c le s a llo w e d

S T A R T

E O C B A /D s a m p lin g tim e A /D s a m p lin g t im e A /D s a m p lin g tim e

tA D C S tA D C S tA D C S

P C R 2 ~ 0 0 0 B 1 0 0 B 1 0 0 B 1 0 1 B 0 0 0 B
P C R 0
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~
A C S 0 0 0 0 B 0 1 0 B 0 0 0 B 0 0 1 B d o n 't c a r e
P o w e r-o n S ta rt o f A /D S ta rt o f A /D S ta rt o f A /D
R e s e t c o n v e r s io n c o n v e r s io n c o n v e r s io n
R e s e t A /D R e s e t A /D R e s e t A /D
c o n v e rte r c o n v e rte r c o n v e rte r
E n d o f A /D E n d o f A /D E n d o f A /D
1 : D e fin e P B c o n fig u r a tio n c o n v e r s io n c o n v e r s io n c o n v e r s io n
2 : S e le c t a n a lo g c h a n n e l
tA D C tA D C tA D C
A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e A /D c o n v e r s io n tim e

N o te : A /D c lo c k m u s t b e fS Y S /2 , fS Y S /8 o r fS Y S /3 2
tA D C S = 3 2 tA D
tA D C = 8 0 tA D

A/D Conversion Timing

The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock
mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
: ; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
Polling_EOC:
sz EOCB ; poll the ADCR register EOCB bit to detect end of A/D conversion
jmp polling_EOC ; continue polling
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined memory
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined memory
:
:
jmp start_conversion ; start next A/D conversion

Rev. 1.00 20 August 24, 2006

 HT46R53A/HT46R54A

Example: using Interrupt Method to detect end of conversion

clr EADI ; disable ADC interrupt
mov a,00000001B
mov ACSR,a ; setup the ACSR register to select fSYS/8 as the A/D clock

mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs
mov ADCR,a ; and select AN0 to be connected to the A/D converter
:
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr START
set START ; reset A/D
clr START ; start A/D
clr ADF ; clear ADC interrupt request flag
set EADI ; enable ADC interrupt
set EMI ; enable global interrupt
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov acc_stack,a ; save ACC to user defined memory
mov a,STATUS
mov status_stack,a ; save STATUS to user defined memory
:
:
mov a,ADRH ; read conversion result high byte value from the ADRH register
mov adrh_buffer,a ; save result to user defined register
mov a,ADRL ; read conversion result low byte value from the ADRL register
mov adrl_buffer,a ; save result to user defined register
clr START
set START ; reset A/D
clr START ; start A/D
:
:
EXIT_INT_ISR:
mov a,status_stack
mov STATUS,a ; restore STATUS from user defined memory
mov a,acc_stack ; restore ACC from user defined memory
reti

Low Voltage Reset - LVR The relationship between VDD and VLVR is shown below.
There is a low voltage reset circuit (LVR) implemented in V D D V O P R
the microcontrollers. The function can be enabled/dis- 5 .5 V 5 .5 V
abled by options.
If the supply voltage of the device is within the range
0.9V~VLVR such as changing a battery, the LVR will au-
tomatically reset the device internally. V L V R

3 .0 V
The LVR includes the following specifications:
2 .2 V
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function. 0 .9 V

· The LVR uses the ²OR² function with the external RES Note: VOPR is the voltage range for proper chip
signal to perform chip reset. operation at 4MHz system clock.

Rev. 1.00 21 August 24, 2006

 HT46R53A/HT46R54A

V D D

5 .5 V

V L V R L V R D e te c t V o lta g e

0 .9 V

0 V

R e s e t S ig n a l

R e s e t N o r m a l O p e r a tio n R e s e t

*1 *2

Low Voltage Reset

Note: *1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.

Options
The following shows kinds of options in the device. ALL the options must be defined to ensure having a proper function-
ing system.

Options
OSC type selection.
This option is to decide if an RC or crystal oscillator is chosen as system clock.
WDT source selection.
There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² instruction can clear
the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² instructions have been executed,
then WDT can be cleared.
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
chip from a HALT by a falling edge. (Bit option)
Pull-high selection.
This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports. PA is bit op-
tion; PB, PC and PD are port option.
PFD selection.
PA3: Level output or PFD output.
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM output
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212, 213, 214 and 215
LVR selection.
Enable or disable LVR function.

Rev. 1.00 22 August 24, 2006

 HT46R53A/HT46R54A

Application Circuits

V D D

0 .0 1 m F
V D D P A 0 ~ P A 2
1 0 0 k W P A 3 /P F D
V D D
0 .1 m F R E S P A 4 /T M R

1 0 k W P A 5 /IN T 4 7 0 p F R C S y s te m O s c illa to r
O S C 1
P A 6 ~ P A 7 3 0 k W < R O S C < 7 5 0 k W
0 .1 m F R O S C
V S S P B 0 /A N 0 fS Y S /4
O S C 2
|
P B 7 /A N 7 C 1
O S C 1 C ry s ta l S y s te m O s c illa to r
O S C O S C 1 P C 0 ~ P C 4 F o r th e v a lu e s ,
C ir c u it P D 0 /P W M s e e ta b le b e lo w
O S C 2 C 2
O S C 2
S e e R ig h t S id e R 1

H T 4 6 R 5 3 A /H T 4 6 R 5 4 A O S C C ir c u it

The following table shows the C1, C2 and R1 values corresponding to the different crystal values. (For reference only)

Crystal or Resonator C1, C2 R1

4MHz Crystal 0pF 10kW
4MHz Resonator 10pF 12kW
3.58MHz Crystal 0pF 10kW
3.58MHz Resonator 25pF 10kW
2MHz Crystal & Resonator 25pF 10kW
1MHz Crystal 35pF 27kW
480kHz Resonator 300pF 9.1kW
455kHz Resonator 300pF 10kW
429kHz Resonator 300pF 10kW
The function of the resistor R1 is to ensure that the oscillator will switch off should low voltage conditions occur.
Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating volt-
age. Note however that if the LVR is enabled then R1 can be removed.

Note: The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.

Rev. 1.00 23 August 24, 2006

 HT46R53A/HT46R54A

Instruction Set Summary

Instruction Flag
Mnemonic Description
Cycle Affected
Arithmetic
ADD A,[m] Add data memory to ACC 1 Z,C,AC,OV
ADDM A,[m] Add ACC to data memory 1(1) Z,C,AC,OV
ADD A,x Add immediate data to ACC 1 Z,C,AC,OV
ADC A,[m] Add data memory to ACC with carry 1 Z,C,AC,OV
ADCM A,[m] Add ACC to data memory with carry 1(1) Z,C,AC,OV
SUB A,x Subtract immediate data from ACC 1 Z,C,AC,OV
SUB A,[m] Subtract data memory from ACC 1 Z,C,AC,OV
SUBM A,[m] Subtract data memory from ACC with result in data memory 1(1) Z,C,AC,OV
SBC A,[m] Subtract data memory from ACC with carry 1 Z,C,AC,OV
SBCM A,[m] Subtract data memory from ACC with carry and result in data memory 1(1) Z,C,AC,OV
DAA [m] Decimal adjust ACC for addition with result in data memory 1(1) C
Logic Operation
AND A,[m] AND data memory to ACC 1 Z
OR A,[m] OR data memory to ACC 1 Z
XOR A,[m] Exclusive-OR data memory to ACC 1 Z
ANDM A,[m] AND ACC to data memory 1(1) Z
ORM A,[m] OR ACC to data memory 1(1) Z
XORM A,[m] Exclusive-OR ACC to data memory 1(1) Z
AND A,x AND immediate data to ACC 1 Z
OR A,x OR immediate data to ACC 1 Z
XOR A,x Exclusive-OR immediate data to ACC 1 Z
CPL [m] Complement data memory 1(1) Z
CPLA [m] Complement data memory with result in ACC 1 Z
Increment & Decrement
INCA [m] Increment data memory with result in ACC 1 Z
INC [m] Increment data memory 1(1) Z
DECA [m] Decrement data memory with result in ACC 1 Z
DEC [m] Decrement data memory 1(1) Z
Rotate
RRA [m] Rotate data memory right with result in ACC 1 None
RR [m] Rotate data memory right 1(1) None
RRCA [m] Rotate data memory right through carry with result in ACC 1 C
RRC [m] Rotate data memory right through carry 1(1) C
RLA [m] Rotate data memory left with result in ACC 1 None
RL [m] Rotate data memory left 1(1) None
RLCA [m] Rotate data memory left through carry with result in ACC 1 C
RLC [m] Rotate data memory left through carry 1(1) C
Data Move
MOV A,[m] Move data memory to ACC 1 None
MOV [m],A Move ACC to data memory 1(1) None
MOV A,x Move immediate data to ACC 1 None
Bit Operation
CLR [m].i Clear bit of data memory 1(1) None
SET [m].i Set bit of data memory 1(1) None

Rev. 1.00 24 August 24, 2006

 HT46R53A/HT46R54A

Instruction Flag
Mnemonic Description
Cycle Affected
Branch
JMP addr Jump unconditionally 2 None
SZ [m] Skip if data memory is zero 1(2) None
SZA [m] Skip if data memory is zero with data movement to ACC 1(2) None
SZ [m].i Skip if bit i of data memory is zero 1(2) None
SNZ [m].i Skip if bit i of data memory is not zero 1(2) None
SIZ [m] Skip if increment data memory is zero 1(3) None
SDZ [m] Skip if decrement data memory is zero 1(3) None
SIZA [m] Skip if increment data memory is zero with result in ACC 1(2) None
SDZA [m] Skip if decrement data memory is zero with result in ACC 1(2) None
CALL addr Subroutine call 2 None
RET Return from subroutine 2 None
RET A,x Return from subroutine and load immediate data to ACC 2 None
RETI Return from interrupt 2 None
Table Read
TABRDC [m] Read ROM code (current page) to data memory and TBLH 2(1) None
TABRDL [m] Read ROM code (last page) to data memory and TBLH 2(1) None
Miscellaneous
NOP No operation 1 None
CLR [m] Clear data memory 1(1) None
SET [m] Set data memory 1(1) None
CLR WDT Clear Watchdog Timer 1 TO,PDF
CLR WDT1 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
CLR WDT2 Pre-clear Watchdog Timer 1 TO(4),PDF(4)
SWAP [m] Swap nibbles of data memory 1(1) None
SWAPA [m] Swap nibbles of data memory with result in ACC 1 None
HALT Enter power down mode 1 TO,PDF

Note: x: Immediate data

m: Data memory address

A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
: and (2)
(4)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
²CLR WDT1² or ²CLR WDT2² instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.

Rev. 1.00 25 August 24, 2006

 HT46R53A/HT46R54A

Instruction Definition

ADC A,[m] Add data memory and carry to the accumulator

Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADCM A,[m] Add the accumulator and carry to data memory

Description The contents of the specified data memory, accumulator and the carry flag are added si-
multaneously, leaving the result in the specified data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADD A,[m] Add data memory to the accumulator

Description The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation ACC ¬ ACC+[m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADD A,x Add immediate data to the accumulator

Description The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation ACC ¬ ACC+x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

ADDM A,[m] Add the accumulator to the data memory

Description The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation [m] ¬ ACC+[m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

Rev. 1.00 26 August 24, 2006

 HT46R53A/HT46R54A

AND A,[m] Logical AND accumulator with data memory

Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op-
eration. The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

AND A,x Logical AND immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²AND² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

ANDM A,[m] Logical AND data memory with the accumulator

Description Data in the specified data memory and the accumulator perform a bitwise logical_AND op-
eration. The result is stored in the data memory.
Operation [m] ¬ ACC ²AND² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

CALL addr Subroutine call

Description The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation Stack ¬ Program Counter+1
Program Counter ¬ addr
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

CLR [m] Clear data memory

Description The contents of the specified data memory are cleared to 0.
Operation [m] ¬ 00H
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 27 August 24, 2006

 HT46R53A/HT46R54A

CLR [m].i Clear bit of data memory

Description The bit i of the specified data memory is cleared to 0.
Operation [m].i ¬ 0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

CLR WDT Clear Watchdog Timer

Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO PDF OV Z AC C
0 0 ¾ ¾ ¾ ¾

CLR WDT1 Preclear Watchdog Timer

Description Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾ ¾ ¾ ¾

CLR WDT2 Preclear Watchdog Timer

Description Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which im-
plies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO PDF OV Z AC C
0* 0* ¾ ¾ ¾ ¾

CPL [m] Complement data memory

Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation [m] ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.00 28 August 24, 2006

 HT46R53A/HT46R54A

CPLA [m] Complement data memory and place result in the accumulator
Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation ACC ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

DAA [m] Decimal-Adjust accumulator for addition

Description The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumu-
lator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD ad-
justment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö

DEC [m] Decrement data memory

Description Data in the specified data memory is decremented by 1.
Operation [m] ¬ [m]-1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

DECA [m] Decrement data memory and place result in the accumulator
Description Data in the specified data memory is decremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]-1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.00 29 August 24, 2006

 HT46R53A/HT46R54A

HALT Enter power down mode

Description This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation Program Counter ¬ Program Counter+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO PDF OV Z AC C
0 1 ¾ ¾ ¾ ¾

INC [m] Increment data memory

Description Data in the specified data memory is incremented by 1
Operation [m] ¬ [m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

INCA [m] Increment data memory and place result in the accumulator
Description Data in the specified data memory is incremented by 1, leaving the result in the accumula-
tor. The contents of the data memory remain unchanged.
Operation ACC ¬ [m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

JMP addr Directly jump

Description The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation Program Counter ¬addr
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

MOV A,[m] Move data memory to the accumulator

Description The contents of the specified data memory are copied to the accumulator.
Operation ACC ¬ [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 30 August 24, 2006

 HT46R53A/HT46R54A

MOV A,x Move immediate data to the accumulator

Description The 8-bit data specified by the code is loaded into the accumulator.
Operation ACC ¬ x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

MOV [m],A Move the accumulator to data memory

Description The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation [m] ¬ACC
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

NOP No operation
Description No operation is performed. Execution continues with the next instruction.
Operation Program Counter ¬ Program Counter+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

OR A,[m] Logical OR accumulator with data memory

Description Data in the accumulator and the specified data memory (one of the data memories) per-
form a bitwise logical_OR operation. The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

OR A,x Logical OR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation ACC ¬ ACC ²OR² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

ORM A,[m] Logical OR data memory with the accumulator

Description Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation [m] ¬ACC ²OR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.00 31 August 24, 2006

 HT46R53A/HT46R54A

RET Return from subroutine

Description The program counter is restored from the stack. This is a 2-cycle instruction.
Operation Program Counter ¬ Stack
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RET A,x Return and place immediate data in the accumulator

Description The program counter is restored from the stack and the accumulator loaded with the speci-
fied 8-bit immediate data.
Operation Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RETI Return from interrupt

Description The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RL [m] Rotate data memory left

Description The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

RLA [m] Rotate data memory left and place result in the accumulator
Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 32 August 24, 2006

 HT46R53A/HT46R54A

RLC [m] Rotate data memory left through carry

Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re-
places the carry bit; the original carry flag is rotated into the bit 0 position.
Operation [m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

RLCA [m] Rotate left through carry and place result in the accumulator
Description Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

RR [m] Rotate data memory right

Description The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾

RRA [m] Rotate right and place result in the accumulator

Description Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ ¾

RRC [m] Rotate data memory right through carry

Description The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation [m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C
¾ ¾ ¾ ¾ ¾ Ö

Rev. 1.00 33 August 24, 2006

 HT46R53A/HT46R54A

RRCA [m] Rotate right through carry and place result in the accumulator
Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ Ö

SBC A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the accumulator.
Operation ACC ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SBCM A,[m] Subtract data memory and carry from the accumulator
Description The contents of the specified data memory and the complement of the carry flag are sub-
tracted from the accumulator, leaving the result in the data memory.
Operation [m] ¬ ACC+[m]+C
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SDZ [m] Skip if decrement data memory is 0

Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SDZA [m] Decrement data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy-
cles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 34 August 24, 2006

 HT46R53A/HT46R54A

SET [m] Set data memory

Description Each bit of the specified data memory is set to 1.
Operation [m] ¬ FFH
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SET [m]. i Set bit of data memory

Description Bit i of the specified data memory is set to 1.
Operation [m].i ¬ 1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SIZ [m] Skip if increment data memory is 0

Description The contents of the specified data memory are incremented by 1. If the result is 0, the fol-
lowing instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SIZA [m] Increment data memory and place result in ACC, skip if 0
Description The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory re-
mains unchanged. If the result is 0, the following instruction, fetched during the current in-
struction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SNZ [m].i Skip if bit i of the data memory is not 0

Description If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other-
wise proceed with the next instruction (1 cycle).
Operation Skip if [m].i¹0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 35 August 24, 2006

 HT46R53A/HT46R54A

SUB A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation ACC ¬ ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SUBM A,[m] Subtract data memory from the accumulator

Description The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation [m] ¬ ACC+[m]+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SUB A,x Subtract immediate data from the accumulator

Description The immediate data specified by the code is subtracted from the contents of the accumula-
tor, leaving the result in the accumulator.
Operation ACC ¬ ACC+x+1
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ Ö Ö Ö Ö

SWAP [m] Swap nibbles within the data memory

Description The low-order and high-order nibbles of the specified data memory (1 of the data memo-
ries) are interchanged.
Operation [m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SWAPA [m] Swap data memory and place result in the accumulator
Description The low-order and high-order nibbles of the specified data memory are interchanged, writ-
ing the result to the accumulator. The contents of the data memory remain unchanged.
Operation ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 36 August 24, 2006

 HT46R53A/HT46R54A

SZ [m] Skip if data memory is 0

Description If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SZA [m] Move data memory to ACC, skip if 0

Description The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation Skip if [m]=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

SZ [m].i Skip if bit i of the data memory is 0

Description If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruc-
tion (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation Skip if [m].i=0
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

TABRDC [m] Move the ROM code (current page) to TBLH and data memory
Description The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

TABRDL [m] Move the ROM code (last page) to TBLH and data memory
Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation [m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ ¾ ¾ ¾

Rev. 1.00 37 August 24, 2006

 HT46R53A/HT46R54A

XOR A,[m] Logical XOR accumulator with data memory

Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu-
sive_OR operation and the result is stored in the accumulator.
Operation ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

XORM A,[m] Logical XOR data memory with the accumulator

Description Data in the indicated data memory and the accumulator perform a bitwise logical Exclu-
sive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation [m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

XOR A,x Logical XOR immediate data to the accumulator

Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op-
eration. The result is stored in the accumulator. The 0 flag is affected.
Operation ACC ¬ ACC ²XOR² x
Affected flag(s)
TO PDF OV Z AC C

¾ ¾ ¾ Ö ¾ ¾

Rev. 1.00 38 August 24, 2006

 HT46R53A/HT46R54A

Package Information
28-pin SKDIP (300mil) Outline Dimensions

2 8 1 5
B
1 1 4

D
a I
E F G

Dimensions in mil
Symbol
Min. Nom. Max.
A 1375 ¾ 1395
B 278 ¾ 298
C 125 ¾ 135
D 125 ¾ 145
E 16 ¾ 20
F 50 ¾ 70
G ¾ 100 ¾
H 295 ¾ 315
I 330 ¾ 375
a 0° ¾ 15°

Rev. 1.00 39 August 24, 2006

 HT46R53A/HT46R54A

28-pin SOP (300mil) Outline Dimensions

2 8 1 5

A B

1 1 4

C '
G
D H

E F a

Dimensions in mil
Symbol
Min. Nom. Max.
A 394 ¾ 419
B 290 ¾ 300
C 14 ¾ 20
C¢ 697 ¾ 713
D 92 ¾ 104
E ¾ 50 ¾
F 4 ¾ ¾
G 32 ¾ 38
H 4 ¾ 12
a 0° ¾ 10°

Rev. 1.00 40 August 24, 2006

 HT46R53A/HT46R54A

Product Tape and Reel Specifications

Reel Dimensions

D
T 2

A B C

T 1

SOP 28W (300mil)

Symbol Description Dimensions in mm
A Reel Outer Diameter 330±1
B Reel Inner Diameter 62±1.5
13+0.5
C Spindle Hole Diameter
-0.2
D Key Slit Width 2±0.5
24.8+0.3
T1 Space Between Flange
-0.2
T2 Reel Thickness 30.2±0.2

Rev. 1.00 41 August 24, 2006

 HT46R53A/HT46R54A

Carrier Tape Dimensions

P 0 P 1
D t

F
W
B 0
C

D 1 P
K 0

A 0

SOP 28W (300mil)

Symbol Description Dimensions in mm
W Carrier Tape Width 24±0.3
P Cavity Pitch 12±0.1
E Perforation Position 1.75±0.1
F Cavity to Perforation (Width Direction) 11.5±0.1
D Perforation Diameter 1.5+0.1
D1 Cavity Hole Diameter 1.5+0.25
P0 Perforation Pitch 4±0.1
P1 Cavity to Perforation (Length Direction) 2±0.1
A0 Cavity Length 10.85±0.1
B0 Cavity Width 18.34±0.1
K0 Cavity Depth 2.97±0.1
t Carrier Tape Thickness 0.35±0.01
C Cover Tape Width 21.3

Rev. 1.00 42 August 24, 2006

 HT46R53A/HT46R54A

Holtek Semiconductor Inc. (Headquarters)

No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
[Link]

Holtek Semiconductor Inc. (Taipei Sales Office)

4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)

Holtek Semiconductor Inc. (Shanghai Sales Office)

7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
[Link]

Holtek Semiconductor Inc. (Shenzhen Sales Office)

5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 0755-8616-9908, 8616-9308
Fax: 0755-8616-9533

Holtek Semiconductor Inc. (Beijing Sales Office)

Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125

Holtek Semiconductor Inc. (Chengdu Sales Office)

709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 028-6653-6590
Fax: 028-6653-6591

Holmate Semiconductor, Inc. (North America Sales Office)

46729 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
[Link]

Copyright Ó 2006 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this handbook is believed to be accurate at the time of publication. However, Holtek assumes
no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for
the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without
further modification, nor recommends the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices or sys-
tems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please
visit our web site at [Link]

Rev. 1.00 43 August 24, 2006