ANNA UNIVERSITY, CHENNAI

NON- AUTONOMOUS COLLEGES

AFFILIATED TO ANNA UNIVERSITY
M.E., VLSI DESIGN
REGULATIONS 2025

PROGRAMME OUTCOMES (POs):

PO Programme Outcomes
PO1 An ability to independently carry out research /investigation and development
work to solve practical problems
PO2 An ability to write and present a substantial technical report/document.
PO3 Students should be able to demonstrate a degree of mastery over the area as
per the specialization of the program. The mastery should be at a level higher
than the requirements in the appropriate bachelor program

PROGRAMME SPECIFIC OUTCOMES(PSOs):

PSO Programme Specific Outcomes

PSO1 Ability to design and implement innovative solutions to solve complex

problems in VLSI.
PSO2 Competence to independently undertake research projects involving
simulation, measurement, and product development in VLSI-related fields.

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 ANNA UNIVERSITY, CHENNAI

POST GRADUATE CURRICULUM (NON-AUTONOMOUS AFFILIATED INSTITUTIONS)

Programme: M.E., VLSI Design Regulations: 2025

Abbreviations:

BS – Basic Science (Mathematics, Physics, L – Laboratory Course

Chemistry)
ES – Engineering Science (General (G), T – Theory
Programme Core (PC), Programme
Elective (PE)
SD – Skill Development LIT – Laboratory Integrated Theory
SL – Self Learning PW – Project Work
OE – Open Elective
TCP – Total Contact Period(s)

Semester I

Periods Total
S. Course
Course Title Type per week Contact Credits Category
No. Code
Periods
L T P
VL25101 Graph Theory and
1.
Optimization T 3 1 0 4 4 ES (PC)
Techniques
VL25102 ASIC and FPGA
2. LIT 3 0 2 5 4 ES (PC)
Design
AP25C03 Digital CMOS VLSI
3. T 3 0 0 3 3 ES (PC)
Design
AP25C01 Advanced Digital
4. T 3 1 0 4 4 ES (PC)
System Design
AP25C02 Analog Integrated
5 T 3 0 0 3 3 ES (PC)
Circuit Design
AP25C04 Analog IC Design
7. L 0 0 4 4 2 ES (PC)
Laboratory
VL25103 Technical Seminar - 0 0 2 2 1 SD
8.
Total 25 21

Page 2 of 18
 Semester II
Periods Total
S. Course
Type per week Contact Credits Category
No. Code Course Title
L T P Periods
Multi-Core Architecture T 3 0 0 3 3 ES (PC)
1.
and ISA Verification
Data Converters IC T 3 0 0 3 3 ES (PC)
2.
Design
VLSI testing and T 3 0 0 3 3 ES (PC)
3.
verification using UVM
Programme Elective I T 3 0 0 3 3 ES (PC)
4.
Low Power VLSI LIT 3 0 2 5 4
5. ES (PC)
Design
Industry Oriented -- 1 0 0 1 1
6. SD
Course I
7. Verification using UVM L 0 0 4 4 2 ES (PC)
Laboratory
8. Industrial Training - - -- - --- 1 SD
9. Self-Learning Course - - -- - --- 1 --
Total 22 22

Semester III

Periods Total
S. Course
Course Title Type per week Contact Credits Category
No. Code
Periods
L T P
1. Programme Elective II T 3 0 0 3 3 ES (PE)

2. Programme Elective III T 3 0 0 3 3 ES (PE)

3. Programme Elective IV T 3 0 0 3 3 ES (PE)

4. Open Elective T 3 0 0 3 3 --
Industry Oriented -- 1 0 0 1 1 SD
Course I
5. Project Work I -- 0 0 8 12 6 SD

Total 25 19

Semester IV

Periods Total
S. Course
Course Title Type per week Contact Credits Category
No. Code
L T P Periods

1. Project Work II -- 0 0 24 24 12
Total 24 12

Page 3 of 18
 Programme Elective Courses (PE)

Periods Total
S. Course
Course Title per week Contact Credits
No. Code
L T P Periods
1. VLSI Signal Processing 3 0 0 3 3
2. RF IC Design 3 0 0 3 3
3. Electromagnetic Interference 3 0 0 3 3
and Compatibility
4. Physical Design of VLSI 3 0 0 3 3
5. Hardware Software Co-Deign 3 0 0 3 3
for FPGA
6. CAD for VLSI Design 3 0 0 3 3
7. Nanotechnology 3 0 0 3 3
8. Pattern Recognition 3 0 0 3 3
9. Signal Integrity for High Speed 3 0 0 3 3
Design
10. Network On Chip 3 0 0 3 3
11. VLSI for wireless 3 0 0 3 3
Communication
12. DSP Structures for VLSI 3 0 0 3 3
13. MEMS and NEMS 3 0 0 3 3
14 Advanced Transistor Modelling 3 0 0 3 3
15 VLSI Architectures for Image 3 0 0 3 3
Processing
16 Reconfigurable Architecture 3 0 0 3 3
17 Adaptive Signal Processing 3 0 0 3 3
18 Digital Image and Video 3 0 0 3 3
Processing
19 Data Converters 3 0 0 3 3
20 Evolvable Hardware 3 0 0 3 3

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Semester I

Page 5 of 18
 L T P C
VL25101 Graph Theory and Optimization Techniques
3 1 0 4
Course Objectives:
 Introduce and apply graph theory, linear and nonlinear programming, and simulation
modeling techniques to solve real-life engineering and business problems.

Graphs: Graphs and graph models - Graph terminology and special types of graphs -
Matrix representation of graphs and graph isomorphism - Connectivity- Euler and
Hamilton paths - Trees - Spanning trees.
Activities: 1. Construct and analyze graph models using adjacency matrices.
2. Identify Euler, Hamilton paths, and spanning trees in graphs.
Graph Algorithm: Graph Algorithms - Directed graphs - Some basic algorithms -
Shortest path algorithms - Depth - First search on a graph - Theoretic algorithms -
Performance of graph theoretic algorithms - Graph theoretic computer languages.
Activities: 1. Implement DFS and BFS on directed graphs.
2. Apply shortest path algorithms and analyze their performance.

Linear Programming: Formulation - Graphical solution - Simplex method - Two-phase

method - Transportation and Assignment Models.
Activities: 1. Formulate and solve LP problems using graphical and simplex methods.
2. Solve transportation and assignment problems with two-phase method.

Non-Linear Programming: Constrained Problems, Equality constraints- Lagrangean

Method, Inequality constraints, Karush, Kuhn-Tucker {KKT) conditions - Quadratic
Programming.
Activities: 1. Solve constrained optimization using Lagrangean and KKT conditions.
2. Apply quadratic programming to nonlinear optimization problems.

Simulation Model and Network Model: Monte Carlo Simulation, Types of Simulation,
Elements of Discrete Event Simulation, Generation of Random Numbers,Applications to
Queuing systems - Project network, CPM and PERT networks, Critical path scheduling -
Sequencing models
Activities: 1. Perform Monte Carlo and discrete event simulations for queuing
systems.
2. Construct CPM/PERT networks and apply critical path scheduling.
Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%
Assessment Methodology: Quiz (5%), Assignments (10%), Review of Question
Papers (IES, GATE, SSC Questions) (20%), Projects (20%), Flipped Class (5%),
Internal Examinations (40%).

Page 6 of 18
References:
1. Sharma, J. K. (2009). Operation Research (3rd ed.). Macmillan Publishers India Ltd.
2. West, D. B. (2015). Introduction to graph theory. Pearson Education.
3. Balakrishna, R., & Ranganathan, K. (2012). A textbook of graph theory. Springer
Science and Business Media.
4. Deo, N. (2016). Graph theory with applications to engineering and computer science.
Dover Publications, Inc.
5. Rao, G. S. S. B. (2015). Discrete structures and graph theory. Scitech Publications
Pvt. Limited.
6. Natarajan, A. M., Balasubramani, P., & Tamilarasi, A. (2014). Operations research.
Pearson Education Pvt. Limited.

CO description PO PSO1 PSO2

Explain the basics of linear and nonlinear - - -
CO1
programming
Apply fundamental graph algorithms including PO1(3) 3 3
CO2 shortest path and traversal techniques. PO2(3)

Model and analyze graphs and their connectivity PO1(3) 2 2

CO3 for problem-solving. PO2(3)

Utilize simulation and network models like Monte PO1(3) 3 2

CO4 Carlo, CPM, and PERT for engineering PO3(3)
applications.

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 ASIC and FPGA Design L T P C
VL25102
3 0 2 4
Course Objectives:
To Focus on Semi-Custom IC Design: Principles of Logic Cells, I/O Cells, Interconnect
Architecture; Equal emphasis on FPGA & ASIC styles.

Introduction to Asics, CMOS Logic and ASIC Library Design: Types of Asics - Design
Flow - CMOS Transistors - Combinational Logic Cell - Sequential Logic Cell - Data Path
Logic Cell - Transistors as Resistors -Transistor Parasitic Capacitance- Logical Effort.
Activity :Analyze and classify different types of ASICs based on their applications and
design complexity.
Practical Experiments:
1. Simulate CMOS inverter circuits and study transistor parasitic effects using
a circuit simulator tool.
2. Running simulator and debug tools
3. Experiment with 2 state and 4 state data types

Programmable ASICS, Programmable ASIC Logic Cells and Programmable Asic

1/0 Cells: Anti fuse - static RAM - EPROM and EEPROM technology - Actel ACT -
Xilinx LCA -Altera FLEX - Altera MAX DC & AC inputs and outputs - Clock & Power
inputs - Xilinx 1/0 blocks, ASIC Tool Flow.
Activity: Compare different programmable ASIC technologies (Anti-fuse vs SRAM vs
EPROM) in terms of speed, power, and reconfigurability.
Practical Experiments:
1. Experiment with blocking and non-blocking assignments
2. Model and verify simple ALU
3. Model and verify an Instruction stack

Logic Synthesis, Simulation and Testing: Design systems - Logic Synthesis - Half
gate ASIC -Schematic entry - Low level design language - PLA tools -EDIF- CFI design
representation. Verilog and logic synthesis -VHDL and logic synthesis - types of
simulation -boundary scan test-fault simulation - automatic test pattern generation.
Activities:
1: Write simple Verilog/VHDL modules and synthesize them using logic synthesis
tools.
2: Perform functional and timing simulations and create testbenches for boundary
scan testing.
Practical Experiments:
1. Use an interface between testbench and DUT
2. Developing a test program
3. Create a simple and advanced OO testbench
ASIC Physical Design: System partition -partitioning - partitioning methods -
interconnect delay models and measurement of delay - floor planning - placement
- Routing: global routing - detailed routing - special routing - circuit extraction – DRC

Page 8 of 18
Activities:
1: Perform manual floor planning and placement for a simple ASIC design using
CAD tools.
2: Analyze routing challenges and use tools to perform global and detailed routing;
verify design rules compliance.
Practical Experiments:
1. Create a scoreboard using dynamic array
2. Use mailboxes for verification
FPGA: FPGA Building Block Architecture- Xilinx XC4000 - ALTERA's FLEX
8000/10000, ACTEL's ACT-1,2,3 FPGA Interconnect Routing Procedures.
Activities:
1: Explore and document the internal architecture of Xilinx XC4000 or Altera
FLEX FPGA through data sheets.
2: Design and implement a simple combinational circuit on an FPGA
development board and analyze routing.
Practical Experiments:
1. Generate constrained random test values
2. Using coverage with constrained random tests
Weightage: Continuous Assessment: 50%, End Semester Examinations: 50%
Assessment Methodology: Quiz (5%), Assignments (10%), Review of Question
Papers (IES, GATE, SSC Questions) (20%), Projects (20%), Flipped Class (5%),
Internal Examinations (40%).
References:
1. Smith, J. S. (2003). Application-specific integrated circuits. Pearson.
2. Smith, D. J. (1996). HDL chip design. Doone Publications.
3. Chan, K., & Mourad, S. (1994). Digital design using field programmable gate array.
Prentice Hall.
4. Nekoogar, F. (1999). Timing verification of application-specific integrated circuits
(ASICs). Prentice Hall PTR.
5. Wolf, W. (2004). FPGA-based system design. Prentice Hall PTR.
6. Kilts, S. (n.d.). Advanced FPGA design. Wiley Interscience.

CO description PO PSO1 PSO2

Understand ASIC types, design flow, and CMOS - - -
CO1
logic fundamentals.
Design and analyze combinational and PO1(3) 3 3
CO2 PO2(3)
sequential logic cells in ASICs.
Apply programmable ASIC technologies and use PO1(3) 2 2
CO3 PO2(3)
relevant design tools.
Perform logic synthesis, simulation, physical PO1(3) 3 2
CO4 PO3(3)
design, and FPGA implementation.

Page 9 of 18
 L T P C
AP25C03 Digital CMOS VLSI Design
3 0 0 3
Course Objectives:
To Understand CMOS basics and design combinational/sequential circuits; apply
structured VLSI design through case studies.

MOS Transistors and CMOS Inverter: MOS transistor characteristics, short channel
effects, CMOS inverter design, stick diagrams, power, delay, sizing.
Activities:1. Simulate CMOS inverter characteristics and sizing effects
2. Draw stick diagrams and analyze power-delay trade
CMOS, Combinational Circuits: Complementary CMOS, power reduction, ratioed
logic, pass transistor logic, dynamic CMOS, Domino, NP-CMOS.
Activities:1. Design combinational logic using different CMOS styles
2. Analyze power and switching activity in logic gates
CMOS, Sequential Circuits: Latches vs registers, flip-flops, dynamic/static registers,
clocking strategies, Schmitt trigger, mono/astable circuits.
Activities:1. Implement various flip-flops and compare timing behavior
2. Design clocking schemes for latch/register pipelines
CMOS Sub System Design Adders (carry bypass, select, CLA), multipliers, counters,
parity generators, multiplexers, shifters, memory elements.
Activities:1. Design fast adders and multipliers
2. Build and simulate small subsystems (e.g., counter + MUX)
Performance Estimation & Design Techniques:Delay estimation, logical effort, sizing,
power, interconnects, scaling, synchronous and self-timed design.
Activities:1. Estimate delay and power for sample circuits
2. Compare synchronous vs self-timed circuit design .
Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%
Assessment Methodology: Quiz (5%), Assignments (10%), Review of Question
Papers (IES, GATE, SSC Questions) (20%), Projects (20%), Flipped Class (5%),
Internal Examinations (40%).
References
1. Weste, N. H. E., & Harris, D. (2011). CMOS VLSI design: A circuits and systems
perspective. Pearson.
2. Rabaey, J. M., & Nikolić, B. (2003). Digital integrated circuits. Pearson.
3. Martin, K. (2011). Digital integrated circuit design. Oxford University Press.
4. Palnitkar, S. (2003). Verilog HDL (2nd ed.). Pearson Education.
5. Rabaey, J. M., Chandrakasan, A., & Nikolić, B. (2003). Digital integrated circuits .
Pearson.

Page 10 of 18
 CO description PO PSO1 PSO2
CO1 Explain CMOS basics in digital circuits. - - -
Analyze and design CMOS-based combinational PO1(3) 2 2
CO2
and sequential circuits
Apply various CMOS logic styles and techniques to PO1(3) 3 3
CO3 PO2(3)
optimize digital subsystems
Evaluate and estimate circuit performance using PO1(3) 2 2
CO4 structured approaches for subsystem design. PO2(3)

Page 11 of 18
 L T P C
AP25C01 Advanced Digital System Design
3 1 0 4
Course Objectives:
To study design and analysis of synchronous/asynchronous sequential circuits,
PLD/ROM design, combinational/PLA testing, and Verilog HDL for digital system design.

Sequential Circuit Design: State diagrams/tables, state assignment & reduction,

synchronous circuit design, iterative circuits, ASM charts.
Activities: 1. Design state diagrams for given problems
2. Implement synchronous circuits using ASM
Asynchronous Sequential Circuit Design: Flow table reduction, race conditions,
hazards (static/dynamic/essential), mixed-mode circuits, vending machine controller
design.
Activities: 1. Analyze and minimize flow tables
[Link] and eliminate hazards
Fault Diagnosis and Testability Algorithms: Fault table, path sensitization, Boolean
difference, D & Kohavi algorithms, PLA faults, DFT, BIST techniques.
Activities:[Link] fault tables for combinational circuits
2. Simulate fault detection using D-algorithm
Synchronous Design Using Programmable Devices: PLD families, PLA/PAL-based
circuit design, ROM design, FSM realization using PLDs, FPGA (Xilinx Vertex 7).
Activities:1. Iimplement FSM using PLA/PAL
2. Program and simulate FSM on FPGA
System Design Using Verilog: Verilog HDL modeling, data types, behavioral &
structural modeling, FSM synthesis, test benches, combinational/sequential circuit
realization.
Activities: 1. Write and simulate Verilog code for registers, counters, serial adders
[Link] and test a simple microprocessor in Verilog
Weightage: Continuous Assessment: 50%, End Semester Examinations: 50%
Assessment Methodology: Quiz (5%), Assignments (10%), Review of Question
Papers (IES, GATE, SSC Questions) (20%), Projects (20%), Flipped Class (5%),
Internal Examinations (40%).
References:
1. Roth, C. H., Jr. (2013). Fundamentals of logic design (7th ed.). Thomson Learning.
2. Arnold, M. G. (1999). Verilog digital – computer design. Prentice Hall PTR.
3. Biswas, N. N. (2001). Logic design theory. Prentice Hall of India.
4. Lala, P. K. (2020). Fault tolerant and fault testable hardware design. B S
Publications.
5. Lala, P. K. (2015). Digital system design using PLD (Reprint ed.). B S Publications.
6. Palnitkar, S. (2003). Verilog HDL – A guide to digital design and synthesis. Pearson.

Page 12 of 18
 PO PSO1 PSO2
CO description

CO1 Explain the fundamentals of synchronous and - - -

asynchronous sequential circuits
Analyze and design sequential circuits using
CO2 PO1(3) 2 2
state diagrams and ASM charts.
Apply fault diagnosis and testability algorithms PO1(3)
CO3 3 3
to digital circuits. PO2(3)
Develop and simulate digital systems using PO1(3)
CO4 2 2
Verilog HDL and FPGA. PO2(3)

Page 13 of 18
 L T P C
AP25C02 Analog Integrated Circuit Design
3 0 0 3
Course Objectives:
To Study single-stage amplifier design, high-frequency/noise characteristics,
operational amplifiers, voltage/current reference circuits with practical exercises
Single Stage Amplifiers: MOS physics, equivalent circuits, CS, CG, source follower,
differential & cascode amplifiers, design for SR, gain, BW, ICMR, power, voltage swing.
Activities:1. Design and simulate CS, CG amplifiers
2. Calculate gain, bandwidth, slew rate for given specification
High Frequency and Noise Characteristics of Amplifiers:Miller effect, pole
analysis, frequency response of stages, noise sources, noise analysis in single stage
and differential amplifiers.
Activities:1. Analyze frequency response using pole-zero plots
2. Simulate noise performance in amplifiers.
Negative Feedback Amplifiers and Operational Amplifiers: Feedback types,
loading effects, op-amp parameters, one/two-stage op-amps, gain boosting, slew rate,
PSRR, noise in op-amps.
Activities: [Link] and simulate negative feedback circuits
2. Evaluate gain, slew rate, and PSRR of op-amps
Stability and Frequency Compensation of Two Stage Operational Amplifier: Two-
stage op-amp analysis, phase margin, compensation methods, slew rate issues,
advanced compensation techniques.
Activities:1. Analyze phase margin and stability in two-stage op-amps
2. Implement frequency compensation methods in simulations

Voltage and Current References: Current mirrors (Wilson, Widlar, Cascode), high
swing cascode sinks, supply/temperature independent biasing, PTAT & CTAT currents,
constant-Gm biasing.
Activities: 1. Design and simulate various current mirrors
2. Implement PTAT and CTAT current references
Weightage: Continuous Assessment: 40%, End Semester Examinations: 60%
Assessment Methodology: Quiz (5%), Assignments (10%), Review of Question
Papers (IES, GATE, SSC Questions) (20%), Projects (20%), Flipped Class (5%),
Internal Examinations (40%).
References:
1. Razavi, B. (2016). Design of analog CMOS integrated circuits (2nd ed.). Tata
McGraw Hill.
2. Sansen, W. M. C. (2007). Analog design essentials. Springer.
3. Grebene, A. B. (2003). Bipolar and MOS analog integrated circuit design. John Wiley
& Sons, Inc.
4. Allen, P. E., & Holberg, D. R. (2013). CMOS analog circuit design (3rd ed.). Oxford
University Press.
5. Natarajan, A. (n.d.). EE5390: Analog IC Design [Recorded lecture]. Retrieved from
[Link]
Page 14 of 18
6. Baker, R. J. (2019). CMOS: Circuit design, layout, and simulation (4th ed.). Wiley
IEEE Press.

PO
CO description PSO1 PSO2
Mapping
Explain the theory and design concepts of analog -
CO1 - -
circuits .
Analyse and design single-stage and multi-stage
amplifiers considering high-frequency and noise PO1(3)
CO2 2 2
characteristics to meet specified performance
criteria.
Apply concepts of negative feedback, stability, PO1(3)
CO3 and frequency compensation in the design and PO2(3) 3 3
analysis of operational amplifiers.
Design and simulate voltage and current PO1(3)
CO4 reference circuits with temperature and supply PO2(3) 2 2
independence for analog integrated systems.

Page 15 of 18
 L T P C
AP25C04 Analog IC Design Laboratory
0 0 4 2
Course Objectives:
To Design analog circuits from transistor level to IA implementation using CAD tools for
simulation, layout, LVS, and parasitic extraction.
List of Experiments
1. Extraction of process parameters of CMOS process transistors
a. Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
b. Plot ID vs. VGS at particular drain voltage for NMOS, PMOS and determine Vt.
c. Plot log ID vs. VGS at particular gate voltage for NMOS, PMOS and determine
IOFF and sub- threshold slope.
d. Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine
Channel length modulation factor.
e. Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use
VDS of appropriate voltage To extract Vth use the following procedure.
i. Plot gm vs VGS using SPICE and obtain peak gm point.
ii. Plot y=ID/(gm) as a function of VGS using SPICE.
iii. Use SPICE to plot tangent line passing through peak gm point in y (VGS) plane
and determine Vth.
f. Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line
and calculate gm, gds, gm/gds, and unity gain frequency. Tabulate result
according to technologies and comment on it.
2. CMOS inverter design and performance analysis
a. i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin
and determine transition voltage and gain g. Calculate VIL, VIH, NMH, NML
for the inverter.
ii. Plot VTC for CMOS inverter with varying VDD.
iii. Plot VTC for CMOS inverter with varying device ratio.
b. Perform transient analysis of CMOS inverter with no load and with load and
determine propagation delay tpHL, tpLH, 20%-to-80% rise time tr and 80%-to-
20% fall time tf.
c. Perform AC analysis of CMOS inverter with fanout 0 and fanout 1.
3. Use spice to build a three stage and five stage ring oscillator circuit and
compare its frequencies. Use FFT and verify the amplitude and frequency
components in the spectrum.
4. Single stage amplifier design and performance analysis
a. Plot small signal voltage gain of the minimum-size inverter in the technology
chosen as a function of input DC voltage. Determine the small signal voltage
gain at the switching point using spice and compare the values for two
different process transistors.
b. Consider a simple CS amplifier with active load, with NMOS transistor as
driver and PMOS transistor as load.
i. Establish a test bench to achieve VDSQ=VDD/2.
ii. Calculate input bias voltage for a given bias current.
Page 16 of 18
 iii. Use spice and obtain the bias current. Compare with the theoretical
value
iv. Determine small signal voltage gain, -3dB BW and GBW of the amplifier
v. using small signal analysis in spice, considering load capacitance.
vi. Plot step response of the amplifier with a specific input pulse amplitude.
vii. Derive time constant of the output and compare it with the time constant
viii. resulted from -3dB Band Width.
ix. Use spice to determine input voltage range of the amplifier
5. Three OPAMP Instrumentation Amplifier (INA).
Use proper values of resistors to get a three OPAMP INA with differential-
mode voltage gain=10. Consider voltage gain=2 for the first stage and voltage
gain=5 for the second stage.
i. Draw the schematic of op-amp macro model.
ii. Draw the schematic of INA.
iii. Obtain parameters of the op-amp macro model such that it meets a
given specification for: [Link]-frequency voltage gain, ii. unity gain BW (fu),
[Link] capacitance, [Link] resistance, [Link]
a. Draw schematic diagram of CMRR simulation setup.
b. Simulate CMRR of INA using AC analysis (it's expected to be around 6dB
below CMRR of OPAMP).
c. Plot CMRR of the INA versus resistor mismatches (for resistors of second stage
only) changing from -5% to +5% (use AC analysis). Generate a separate plot
for mismatch in each resistor pair. Explain how CMRR of OPAMP changes with
resistor mismatches.
d. Repeat (iii) to (vi) by considering CMRR of all OPAMPs with another low
frequency gain setting.
[Link] Layout editor.
a. Draw layout of a minimum size inverter using transistors from CMOS process
library. Use Metal 1 as interconnect line between inverters.
b. Run DRC, LVS and RC extraction. Make sure there is no DRC error.
c. Extract the netlist. Use extracted netlist and obtain tPHLtPLH for the inverter
using Spice.
d. Use a specific interconnect length and connect and connect three inverters in
a chain.
e. Extract the new netlist and obtain tPHL and tPLH of the middle inverter.
f. Compare new values of delay times with corresponding values obtained in part
‘c’.
7. Design a differential amplifier with resistive load using transistors from CMOS
process library that meets a given specification for the following parameter
a. low-frequency voltage gain,
b. unity gain BW (fu),
c. Power dissipation
i. Perform DC analysis and determine input common mode range and
compare with the theoretical values.
ii. Perform time domain simulation and verify low frequency gain.
iii. Perform AC analysis and verify.
Page 17 of 18
Weightage: Continuous Assessment: 60%, End Semester Examinations: 40%
Assessment Methodology: Project (30%), Assignment (10%), Practical (30%),
Internal Examinations (30%)

CO description PO PSO1 PSO2

Characterize MOS transistors and design basic
CO1 PO1(3) 2 2
analog building blocks using simulation tools.
Implement and simulate analog circuits through
PO1(3)
CO2 schematic entry, layout design, LVS, and 3 3
PO2(3)
parasitic extraction.
Design and validate an instrumentation amplifier
PO1(3)
CO3 using a structured analog design flow with CAD 2 2
PO2(3)
tools.

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