VLSI Design Flow

1. Specification
In this step, we decide what our chip will do. We write all the details like function, power,
speed, and size. This is like a plan before starting any design. It helps engineers understand
what is needed. Without a clear specification, the chip cannot be made properly.

2. Architecture Design
After the specification, we design the structure of the chip. It includes blocks, memory, and
data flow between them. This step tells how the chip will work inside. It is like a blueprint of
the complete system.

3. RTL Design
Here, we write the design in Verilog or VHDL language. RTL means Register Transfer Level,
which shows how data moves inside the chip. This is the main design part that defines chip
behavior. It is the base for the next steps.

4. Functional Verification
In this step, we test if our RTL code is working correctly. We use simulations and testbenches
to check all functions. If any error is found, it is fixed here. This ensures the design meets the
specification before going ahead.

5. Logic Synthesis
Now, the RTL code is converted into logic gates using tools like Synopsys Design Compiler. It
changes the design into a gate-level circuit. The goal is to make it fast, small, and low power.
This step prepares the design for physical layout.

6. Floorplanning & Placement

In this step, we decide where each block or cell will be placed on the chip. Proper placement
helps in better performance and less wiring. Floorplanning is like setting rooms in a house
before construction. It is very important for timing and power.

7. CTS (Clock Tree Synthesis)

The clock signal controls all parts of the chip. In CTS, we design how the clock will reach
every part evenly. It helps to reduce clock delay and skew. This step ensures synchronization
in the entire chip.

8. Routing
After placement, we connect all cells using wires. This is called routing. It completes all
electrical connections in the chip. The routing should be clean and follow all design rules to
avoid errors.

9. Sign-off
This is the final checking step before manufacturing. We verify timing, power, and design
rules. Tools like PrimeTime and Calibre are used here. Once everything is okay, the design is
ready for fabrication.

10. Fabrication
In this step, the chip is made on a silicon wafer in a semiconductor foundry. The layout design
is printed using photolithography. It is a very costly and careful process done in clean rooms.

11. Testing & Packaging

After fabrication, each chip is tested to find if it works correctly. Faulty chips are rejected.
Good chips are packed in protective cases before selling. The final chip is now ready to use in
electronic devices.

Critical Path
The critical path is the longest delay path between input and output in a digital circuit.
It decides the maximum speed or minimum clock period of the chip.
If the critical path is too long, the circuit will work slowly or may fail at high speed.
Designers try to reduce the critical path delay using faster logic or better placement.
So, optimizing the critical path is very important for timing and performance of VLSI design.

Formula:
T_clock = T_critical path
f_max = 1 / T_critical path

Where:
T_clock = minimum clock period (time per clock cycle)
T_critical path = total delay of the longest path
f_max = maximum clock frequency of the circuit

Worst Case Timing Analysis

Worst Case Timing Analysis means checking the maximum delay that can happen in a circuit
under the worst conditions.
It is done to make sure the chip works properly even when temperature is high, voltage is low,
or process variation occurs.
In this case, we take the slowest path delay and calculate the timing of the circuit.
This helps designers ensure that the chip never fails in any real situation.
It is very important for reliable and stable performance of the VLSI design.

Formula:
T_worst = T_logic delay(max) + T_setup

Where:
T_logic delay(max) = maximum delay of the logic path
T_setup = setup time of the flip-flop

Setup Time Condition

Setup time is the minimum time before the clock edge during which the data must be stable
(not changing).
If data changes during this time, the flip-flop may store the wrong value.
So, data should arrive early enough before the clock edge.
This ensures the correct data is captured by the flip-flop.

Condition (Setup Time):

T_clk ≥ T_comb + T_setup

Where:
T_clk = clock period
T_comb = combinational logic delay
T_setup = setup time of flip-flop

Hold Time Condition

Hold time is the minimum time after the clock edge during which the data must remain stable.
If data changes too early after the clock edge, the flip-flop may capture the wrong data.
So, data should stay stable for some time after the clock signal.

Condition (Hold Time):

T_comb ≥ T_hold

Where:
T_comb = combinational logic delay
T_hold = hold time of flip-flop

Design Hierarchy
Design hierarchy means breaking a big chip design into smaller parts (modules) and
arranging them in levels.
Top level = system or chip, below that are blocks (like CPU, memory, I/O), then modules,
then cells, gates, and transistors.
Each module is designed and verified separately, then connected together — this makes
work easier and less error-prone.
Hierarchy helps reuse modules (IP blocks), speeds up verification, and makes debugging
simpler.
Using hierarchy also helps teams work in parallel: one person can do the ALU while
another does the memory block.
Design principle support hierarchy
1. Top Level

This is the highest level of design. It defines the overall system and shows how different
blocks connect together.

2. Block Level

At this level, the design is divided into smaller functional blocks. Each block performs a
specific task within the system.
3. Modules

Blocks are further broken into modules. Modules describe detailed functions and can be
reused in other designs.

4. Bottom Level

This is the lowest level of the design. It contains basic elements like gates, flip-flops, and
other hardware components.

Level & layers of abstractions

1. System Level

This is the highest level of design. At this level, we focus on what the chip or system should
do, not how it works inside. It includes functions, algorithms, and overall behavior. Engineers
plan the system architecture and modules here. It is like planning the whole project before
building.

2. Register Transfer Level (RTL)

RTL shows how data moves between registers inside the chip. It is written in Verilog or VHDL.
At this level, designers describe the operations and timing of the system. RTL is detailed
enough for synthesis but still abstract from physical circuits.

3. Logic Level

At the logic level, we represent the design using logic gates like AND, OR, and NOT. The focus
is on how signals are processed using combinational and sequential circuits. This level shows
the functional implementation of RTL in terms of gates.

4. Circuit Level

Circuit level goes deeper and shows how transistors implement logic gates. It includes
MOSFETs, capacitors, and resistors. Here, electrical behavior like voltage, current, and delay
is analyzed. This level is important for timing, power, and performance optimization.

5. Layout (Physical) Level

This is the lowest level, where the design is drawn on silicon. It defines the exact placement of
transistors, wires, and components. Layout ensures that the chip can be manufactured
correctly. After layout, the design goes to fabrication.
Integrated Density

Integrated density refers to how many transistors or components can be placed on a given
area of a chip. Higher density means more functions can fit in a smaller chip size. It affects the
chip’s speed, power, and cost. With advanced technology, transistor sizes shrink, so density
increases. Designers try to optimize density without causing heat or signal problems. High
integrated density allows complex chips like processors and memory to be very small and
efficient.

Moore’s Law

Moore’s Law says that the number of transistors on a chip doubles roughly every 18–24
months. This means chips become more powerful and faster over time. It also helps reduce
the size and cost of electronic devices. Thanks to Moore’s Law, computers, phones, and other
gadgets keep improving quickly. However, in recent years, it is becoming harder to keep this
pace because of physical and manufacturing limits.

semiconductor designing hierarchy / levels of

integration

6. GSI (Giga-Scale Integration) over a billion of transistors.

Packaging

Packaging is the process of protecting the semiconductor chip after fabrication. It provides
physical support, protects the chip from dust and damage, and allows it to connect with the
outside world. Packaging also helps in heat dissipation and makes the chip easier to handle
and use in devices.

Mounting / Assembling Methods

Mounting or assembly is how we attach a semiconductor chip or package to the PCB (Printed
Circuit Board). It ensures electrical connection and mechanical support. There are two main
types:

1. PTH (Plated Through-Hole)

Pins of the component go through holes in the PCB.

Pins are soldered on the opposite side of the board.
Provides strong mechanical support, suitable for heavy or large components.
Example packages: DIP, some large connectors.

2. SMT (Surface Mount Technology)

Components are placed directly on the PCB surface, no holes needed.

Held by solder pads and reflow soldering.
Allows smaller, lighter, and high-density circuits.
Example packages: SOP, QFP, BGA, CSP.

Lot (Level of Testing or Batch)

In semiconductor manufacturing, a lot is a group of wafers processed together.

Testing and fabrication are often done batch-wise to maintain quality and efficiency.
It ensures uniformity and easier tracking of defects.

design methology and design style

Design Methodology

Design methodology is the approach or process used to create a VLSI chip. It defines how we
start from specifications and reach a working chip. Choosing the right methodology helps in
faster design, better performance, and lower cost.

Design Styles

1. Full-Custom Design
Every transistor, gate, and layout is designed manually.
Offers the best performance, speed, and area optimization.
Used in very high-performance chips like processors.
Disadvantage: Takes a lot of time and is expensive.
2. Semi-Custom Design
Uses pre-designed blocks like standard cells or gate arrays.
Designer arranges these blocks to build the chip.
Faster and cheaper than full-custom, still efficient.
Commonly used in general-purpose ICs.
3. Programmable Design
Chips can be reprogrammed after manufacturing.
Examples: FPGA, CPLD.
Flexible and fast to develop, but not as optimized as custom designs.
CMOS Logic

CMOS stands for Complementary Metal-Oxide-Semiconductor.

It uses both PMOS and NMOS transistors to implement logic gates.
CMOS is very popular because it consumes very low power when idle.
It provides high noise immunity and fast switching speed.
 Almost all modern VLSI chips like processors, memory, and ICs use CMOS technology.

Propagation Delay (tpt_ptp​)

It is the time taken for a signal to travel from input to output of a logic gate.
Usually measured from 50% of input transition to 50% of output transition.
Formula (for inverter) can be approximated as:

tp=tPLH+tPHL2t_p = \frac{t_{PLH} + t_{PHL}}{2}tp​=2tPLH​+tPHL​​

Where:

tPLHt_{PLH}tPLH​= propagation delay from low to high

tPHLt_{PHL}tPHL​= propagation delay from high to low

Rise Time (trt_rtr​)

Time taken for the output signal to rise from 10% to 90% of its maximum value.
Formula:

tr=t90%−t10%t_r = t_{90\%} - t_{10\%}tr​=t90%​−t10%​

It tells how fast a gate output can rise from 0 → 1.

Fall Time (tft_ftf​)

Time taken for the output signal to fall from 90% to 10% of its maximum value.
Formula:

tf=t90%−t10%t_f = t_{90\%} - t_{10\%}tf​=t90%​−t10%​

It tells how fast a gate output can fall from 1 → 0.

Sheet Resistance (RsR_sRs​)

Sheet resistance is the resistance of a thin layer of material (like polysilicon) per square.
Formula:

Rs=ρtR_s = \frac{\rho}{t}Rs​=tρ​

Where:

ρ\rhoρ = resistivity of the material

ttt = thickness of the layer
Total resistance of a rectangular strip:

R=Rs⋅LWR = R_s \cdot \frac{L}{W}R=Rs​⋅WL​

Where:

LLL = length of the strip

 WWW = width of the strip

1. Static CMOS Design

Description: Uses both PMOS and NMOS transistors to implement logic gates. Output is
always connected to VDD or GND, so it consumes very low static power. Works in all input
conditions without needing clocking. Very reliable, but the area and speed may be slightly
larger than dynamic CMOS.

2. Dynamic CMOS Design

Description: Uses a clock signal to control logic evaluation. Output is stored temporarily
on a capacitor instead of always being connected to VDD/GND. Faster and requires less
transistor count, so area is smaller. But it consumes power during clocking and needs
careful timing.

3. Operation Phases of Dynamic CMOS

1. Precharge Phase
 The output node is charged to VDD (logic high) via the PMOS transistor.
Happens when the clock is low.
2. Evaluation Phase
When the clock is high, the NMOS network evaluates the inputs.
If the logic condition is satisfied, the output may discharge to GND.

4. Steady State Condition

Output voltage remains stable either at VDD or GND.

No current flows through the transistors in steady state (except leakage).
This ensures low static power consumption.

5. Features of Dynamic CMOS Circuits

Faster operation due to fewer transistors.

Smaller area compared to static CMOS.
Requires clocking for proper operation.
Sensitive to noise, charge leakage, and timing issues.

Noise Considerations in Dynamic Design

In dynamic circuits, the stored charge on nodes is small, so they are very sensitive to noise.
Any unwanted voltage, like from neighboring circuits or switching, can change the node value.
This can cause wrong logic output or glitches. Designers must reduce noise by careful layout,
shielding, and proper sizing of transistors. Power supply noise and clock coupling are also
important to control. Proper noise analysis ensures the circuit works reliably and faster.

Charge Leakage

In dynamic circuits, a node stores charge to represent logic. Over time, this charge can leak
through transistors or junctions. Leakage reduces the voltage level and may cause the circuit
to misinterpret logic values. Designers use proper transistor sizing and low-leakage
techniques to minimize this problem.

Effects :-

Both charge leakage and charge sharing can cause dynamic circuits to fail or give wrong
results. They affect reliability, speed, and noise margin. Designers must analyze and control
these effects to ensure the circuit works correctly.

Solutions for Charge Leakage :

Minimize internal node capacitance and use precharge transistors on internal

node

1. Use high-threshold transistors to reduce leakage current.

2. Keep transistor sizes optimal; too small increases leakage.
 3. Use low-leakage design techniques like stacking or sleep transistors.
4. Proper refreshing of dynamic nodes in long circuits to restore charge.

Charge Sharing

Charge sharing happens when a node’s stored charge gets distributed to other connected
nodes during switching. This can reduce the node voltage unexpectedly. It may lead to
incorrect logic output or glitches in the circuit. Careful design of transistor connections can
reduce charge sharing.

Effects :-

Both charge leakage and charge sharing can cause dynamic circuits to fail or give wrong
results. They affect reliability, speed, and noise margin. Designers must analyze and control
these effects to ensure the circuit works correctly.

Solutions for Charge Sharing

1. Add keeper transistors to maintain the charge on critical nodes.

2. Properly size the transistors to avoid large voltage drops.
3. Avoid connecting too many nodes that can share charge together.
4. Use layout techniques to separate sensitive nodes from switching nodes.

Solutions for Charge Leakage :

Minimize internal node capacitance and use precharge transistors on internal

node

Capacitive Coupling (Crosstalk)

Capacitive coupling, also called crosstalk, happens when a signal in one wire affects a nearby
wire due to capacitance between them. It can cause unwanted voltage changes on the victim
wire. This may lead to glitches, wrong logic outputs, or timing errors in the circuit. Designers
reduce crosstalk by increasing spacing, using shield wires, and careful layout of wires.

Clock Feedthrough

Clock feedthrough occurs when the clock signal unintentionally couples to a data node
through transistor gate capacitance. This can inject unwanted voltage into the node. It may
cause wrong logic values or timing problems. Using proper transistor sizing, shielding, and
careful clock routing can minimize feedthrough effects.