############################ pre_floorplan_checks ####################

check_design -checks {dp_pre_floorplan}

check_timing
Check_library

################ Setting Macro Constraints #######################

set macro_cells [get_cells -physical_context -filter “is_hard_macro && !is_physical_only” -quiet]

set_macro_constraints -allowed_orientations {R0 R180} $macro_cells

report_macro_constraints

######################### floorplan initialization ###########################

#initialize_floorplan -core_utilization 0.60 -core_offset 15. – – – → Sqaure shape

#initialize_floorplan -core_utilization 0.6 -shape U -orientation N -side_ratio {2 1 1 1 1 1} -core_offset 15 -coincident_boundary

true – – -> U shape

#initialize_floorplan -core_utilization 0.6 -shape L -orientation N -core_offset 15 -coincident_boundary true -side_ratio {1 1 1 1} –

– -> L shape

#initialize_floorplan -core_utilization 0.6 -shape T -orientation N -core_offset 15 -coincident_boundary true -side_ratio {1 1 2 1 2

1} – – -> T shape

#initialize_floorplan -core_utilization 0.6 -shape R -orientation N -core_offset 15 -coincident_boundary true -side_ratio {10 3} -
boundary {{0 0} {150 300}} – – -> R shape

#initialize_floorplan -control_type die -boundary {{0 0} {0 3000} { 1000 3000} {1000 2000} {2000 2000} { 2000 3000} {3000 3000}
{ 3000 0} {2000 0} { 2000 1000} { 1000 1000} {1000 0}} -core_offset 100. – – > H shape

########################## tap cell insertion #######################

get_lib_cells *TAP*

create_tap_cells -lib_cell saed14rvt_frame_timing_ccs/SAEDRVT14_TAPDS -pattern stagger -distance 15

################################ boundary cells insertion #######################

get_lib_cells *BOUND*

create_boundary_cells -tap_distance 20 -left_boundary_cell <cell name> -right_boundary_cell <cell names>

write_floorplan -output [Link]

report_design -floorplan. (or) report_design -all

report_global_timing
get_cells -filter “design_type==physical_only”

get_cells -filter “design_type==fill”

########################### pin placement #################################

set_app_options -name [Link] -value false -block [current_block]

#set_app_options -name [Link].layer_range -value 2 -block [current_block]

#set_app_options -name [Link].pin_range -value 3 -block [current_block]

set_block_pin_constraints -self -allowed_layers {M3} -pin_spacing 3 -sides {1 3} -width {0.07} -corner_keepout_num_tracks 1 -

self – – – > for inputs

place_pins -ports [get_ports -filter {direction == in }] (or) place_pins -ports [all_inputs]

set_block_pin_constraints -self -allowed_layers {M2} -pin_spacing 3 -sides {2 4} -width {0.07} -corner_keepout_num_tracks 1 -

self – – -> for outputs

place_pins -ports [get_ports -filter {direction == out}] (or) place_pins -ports [all_outputs]

place_pins -legalize -ports [all_inputs]

place_pins -legalize -ports [all_outputs]

check_pin_placement

set_fixed_objects [get_flat_cells -filter “is_hard_macro “] – – – → to fix the status

############################# IO filler cells #######################

create_io_filler_cells -prefix filler_reference_cells {{ FILLER20A FILLER10A FILLER5A

FILLER1A FILLER05A FILLER0005A }}

####################### powerplan1 ##########################

##### create ports vdd vss #####

create_port -port_type ground -direction in VSS

create_port -port_type power -direction in VDD

###### create nets vdd vss #####

create_net -power VDD

create_net -ground VSS

#### connect ports to nets. #####

connect_pg_net -net VDD [get_port VDD]

connect_pg_net -net VSS [get_port VSS]

connect_pg_net. -net VDD [get_pins -hierarchical */VDD]

connect_pg_net. -net VSS [get_pins -hierarchical */VSS]

###### to dissable via connection during compile pg

set_app_options -name [Link].disable_via_creation -value true

###### to create rail ######

create_pg_std_cell_conn_pattern rail_pattern -layers M1 -rail_width 0.15

set_pg_strategy M1_rails -core -pattern {{name: rail_pattern} nets: VDD VSS}

compile_pg. -strategies M1_rails

###### define pg mesh for m2 t0 m7 layers (only core region) ######

create_pg_mesh_pattern M4toM7 -layers {{{vertical_layer: M4} {spacing: minimum} {pitch: 2.2} {width: 0.22} {offset: 0.6}}
{{vertical_layer: M6} {spacing: minimum} {pitch: 2.4} {width:0.24} {offset: 0.6}} {{horizontal_layer: M5} {spacing: minimum} {pitch:
2.6} {width:0.26} {offset: 0.6}} {{horizontal_layer: M7} {spacing: minimum} {pitch: 3} {width:0.5} {offset: 0.6}}}

set_pg_strategy pg_mesh -core -pattern. {{name: M4toM7 } {nets: VDD VSS }} -extension {{stop: 0.2} {layers: M4}}

compile_pg -strategies. pg_mesh

############ define pg for M9 M8. ##################

create_pg_mesh_pattern. M9 -layers {{horizontal_layer: M9} {width: 1.0} {pitch: 3} {spacing: minimum} {offset: 0.9}}

set_pg_strategy ring_pg_M9 -design_boundary -pattern {{name: M9 } {nets: VDD VSS }} -extension {{stop:
design_boundary_and_generate_pin}}

compile_pg -strategies ring_pg_M9

create_pg_mesh_pattern. M8 -layers {{vertical_layer: M8 } {width: 1.0} {pitch: 6} {spacing: minimum} {offset: 1.4}}

set_pg_strategy ring_pg_M8 -design_boundary -pattern {{name: M8 } {nets: VDD VSS }} -extension {{stop: 1} {layers: M9}}

compile_pg -strategies ring_pg_M8

###### checks after pg mesh #####

check_pg_drc

##### create via creation ########

### m4 to m1. ####

set_pg_via_master_rule M4_M1 -contact_code {VIA12_LONG_H VIA23_1cut_V VIA34_LONG_HH}

create_pg_vias -nets. {VDD VSS} -from_layers M4 -to_layers M1 -via_masters M4_M1 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

#M5_M4#33

set_pg_via_master_rule M5_M4 -contact_code {VIA45_LONG_V}

create_pg_vias -nets {VDD VSS} -from_layers M5 -to_layers M4 -via_masters M5_M4 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

# M6_M5

set_pg_via_master_rule M6_M5 -contact_code {VIA56_1cut_V}

create_pg_vias -nets {VDD VSS} -from_layers M6 -to_layers M5 -via_masters M6_M5 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

#M7_M6

set_pg_via_master_rule M7_M6 -contact_code {VIA67_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M7 -to_layers M6 -via_masters M7_M6 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

# M8_M7
set_pg_via_master_rule M8_M7 -contact_code {VIA78_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M8 -to_layers M7 -via_masters M8_M7 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

#M9_M8

set_pg_via_master_rule M9_M8 -contact_code {VIA89_1cut}

create_pg_vias -nets {VDD VSS} -from_layers M9 -to_layers M8 -via_masters M9_M8 -allow_parallel_objects -within_bbox
[get_attribute [current_block] bbox]

check_pg_drc

check_pg_missing_vias

############################# powerplan 2. ###########################

remove_pg_via_master_rules -all

remove_pg_patterns -all

remove_pg_strategies -all

remove_pg_strategy_via_rules -all

create_net -power VDD

create_net -ground VSS

create_pg_ring_pattern ring_pattern -horizontal_layer M9 -horizontal_width {3} -horizontal_spacing {1} -vertical_layer M9 -

vertical_width {3} -vertical_spacing {1}

set_pg_strategy core_ring -pattern {{name: ring_pattern} {nets: {VDD VSS }} {offset: {1 1}}} -core -extension {{stop:
design_boundary_and_generate_pin}}

compile_pg -strategies core_ring

###### 1st level grid######

create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M6} {width: 1.5} {pitch: 5} {offset: 5} { trime: true }}
{{horizontal_layer: M5} {width: 1.2} {pitch: 5} {offset: 5} {trim : true}}}

set_pg_strategy M5M6_mesh -pattern {{name: mesh_pattern} {nets: VDD VSS }} -core -extension {{stop: design_boundary}}

compile_pg -strategies M5M6_mesh

###### 2nd level grid ########

create_pg_mesh_pattern mesh_pattern -layers {{{vertical_layer: M5} {width: 1} {pitch: 3} {offset: 1.7} { trime: true }}
{{horizontal_layer: M4} {width: 0.89} {pitch: 1.7} {offset: 1.5} {trim : true}}}

set_pg_strategy M4M5_mesh -pattern {{name: mesh_pattern} {nets: VDD VSS }} -core -extension {{stop: core_ring}}

compile_pg -strategies M4M5_mesh

##### rails ############

create_pg_std_cell_conn_pattern rail_pattern -layers M1 -rail_width 0.9

set_pg_strategy M1_rails -core -pattern {{name: rail_pattern} nets: VDD VSS}

compile_pg. -strategies M1_rails

############## checks after powerplan ##############

check_pg_drc -nets {VDD VSS}

analyze_power_plan -report_track_utilization_only

check_pg_missing_vias

#before placement we should do

######### buffer adding at each ports#######################

remove_from_collection [get_port *] {clk I1 I2 VDD VSS}

report_utilization

check_design -checks pre_placement_stage

add_buffer -lib_cell <tcbn28hpcplusbwp40p140hvt_c/BUFFD4BWP40P140HVT> [remove_from_collection [all_inputs] {clk I1 I2

VDD VSS}]

legalize_placement

add_buffer -lib_cell <tcbn28hpcplusbwp40p140hvt_c/BUFFD4BWP40P140HVT> [all_outputs]

legalize_placement

set_placement_status fixed [get_cell eco_cell*]

#avoid overlapps

legalize_placement
#to set dont touch on net & cell

get_cells eco_cell*

set_dont_touch [get_cell eco_cell*]

get_nets eco_net*

set_dont_touch [get_nets eco_net*]

check_pg_drc

sizeof_collection [get_cells eco*]

connect_pg_net. -net VDD [get_pins -hierarchical */VDD]

connect_pg_net. -net VSS [get_pins -hierarchical */VSS]

check_pg_drc

### prefixing the newly added cells. during place_opt ######

set_app_options -name [Link].user_instance_name_prefix -value “newly_added”

#[Link].user_instance_name_prefix newly_added

#### do not use CK buff during placements ###

set_lib_cell_purpose -include none [get_lib_cells */CK*]

####### do not use high drive strength cell for better utilization###################

set_lib_cell_purpose -include none [get_lib_cells {*/*D12* */*D16**/*D20* */*D24*}]

############ checks before place cells ####################

report_qor -summary

report_design

report_utilization -verbose

check_pg_drc

check_pg_missing_vias

check_legality
check_boundary_cells

report_scenarios

report_parasitic_parameters

report_utilization

####################### placement ##########################

set_app_options -name time.disable_recovery_removal_checks -value false

set_app_options -name time.disable_case_analysis -value false

set_app_options -name [Link].continue_on_missing_scandef -value true

set_app_options -name [Link].auto_create_blockages -value auto

set_app_options -name [Link].user_instance_name_prefix -value place

set_app_options -name [Link].auto_density_control -value true

##### magnetic placement #######

magnet_placement [get_cells “INST_1"] – → performs magnet placement on the INST_1 cell

magnet_placement -mark_fixed [get_cells “INST_2"] – -→ performs magnet placement. and. marks. the. moved cells as fixed
afterwards

magnet_placement -logical_levels 2. [get_cells “INST_2"] – -→ pulls two levels of cells to INST_2

. ##### bounds creation ###########

create_bound -effort high -name bound1 {cell1 cell2 cell3 … celln} – -→ Create a group bound for the collection of island of
cells/macros

create_bound -name “movebound1" -boundary {{50 60} { 40 80}} -type hard -exclusive {invA1 reset} – -→ creates a hard exclusive
move bound named “move bound1" with. square bound. shape. The. bound contains the invA1 cell and reset port.

######### keepout margin / cell padding ###########

create_keepout_margin -type soft -outer {10 10 10 10} [get_cells MY_LEAF_CELL]

#### to reduce congestion b/w hard macros & perform. coarse placement ####

set_app_options -name [Link].congestion_driven_mode -value macro

create_placement -floorplan -congestion -congestion_effort high

#### timing-driven placement only to standard cells ######

set_app_options -name [Link].timing_driven_mode -value std_cell

create_placement -floorplan -timing_drivenmagnet_placement INST_3 -cells {Cel_1 Cel_2 Cel_3}

####### Combined Congestion-Driven and Timing-Driven Placement ########

set_app_options -name [Link].congestion_driven_mode -value both

set_app_options -name [Link].timing_driven_mode -value both

create_placement -timing_driven -buffering_aware_timing_driven -congestion -effort high -congestion_effort high -incremental

########## individual stages placement #########

place_opt -from initial_place -to. initial_place

report_utilization

place_opt -from initial_drc -to. initial_drc

report_utilization

place_opt -from initial_opto -to initial_opto

report_utilization

place_opt -from final_place -to final_place

report_utilization

place_opt -from final_opto -to final_opto

report_utilization

legalize_placement -incremental

check_legality -verbos

report_congestion

report_utilization

Description - CTS
############################################################################
################sanity_checks##################
check_design -checks pre_clock_tree_stage
check_design -checks physical_constraints

#common_optimization_settings_icc.tcl set
timing_enable_multiple_clocks_per_reg true set_auto_disable_drc_nets -
constant false
set mv_continue_on_opcond_mismatch true
connect_pg_net -verbose

source ./scripts/reports_cts.tcl

########################################################
#### CTS specs
######################################################## proc cts_specs {{stage clock_opt}} {

source ./inputs/sdc_constraints/mcmm_ORCA_TOP.tcl

## propagate the clocks

## make sure clock is propagated for all scenarios set_propagated_clock [all_clocks ]
####################################
## Dont Touch Cells
####################################

set_dont_touch [get_cells "I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*"]

#report_dont_touch I_SDRAM_TOP/I_SDRAM_IF/sd_mux_*

set_dont_touch [get_cells "I_CLOCKING/sys_clk_in_reg"]

#report_dont_touch I_CLOCKING/sys_clk_in_reg

####################################
## Clock Tree Targets
####################################

set_clock_tree_options -target_skew 0.05 -corners [get_corners ss_*] set_clock_tree_options -target_skew 0.02 -corners
[get_corners ff_*] #report_clock_tree_options
####################################
## CTS NDRs
#################################### set_ignored_layers -max_routing_layer M5 set_ignored_layers -min_routing_layer
M2 remove_routing_rules -all create_routing_rule iccrm_clock_double_spacing -default_reference_rule -multiplier_spacing 2
-taper_distance 0.4 -driver_taper_distance 0.4
set_clock_routing_rules -net_type sink -rules iccrm_clock_double_spacing -min_routing_layer
M4 -max_routing_layer M5 #report_routing_rules -verbose
#report_clock_routing_rules

### change the uncertainty for all clocks in all scenarios

foreach_in_collection scen [get_scenarios] { current_scenario $scen

set_clock_uncertainty 0.1 -setup [all_clocks]
set_clock_uncertainty 0.05 -hold [all_clocks]
}

# set a max transition for the clocks in func mode only current_mode func set_max_transition 0.15 -
clock_path [get_clocks] -corners [all_corners]

#################################################
## clock_opt
################################################# remove_routes -global_route

## build_clock cts_specs build_clock clock_opt -to

build_clock cts build_clock
save_block -as build_clock_done

## route_clock cts_specs route_clock clock_opt -to

route_clock cts route_clock save_block -as
cts_route_done

################################################################
###### hold related app options

# Hold cells and settings

set_lib_cell_purpose -exclude hold [get_lib_cells] set_lib_cell_purpose -include hold [get_lib_cells "*/DELLN*_HVT
*/NBUFFX2_HVT */NBUFFX4_HVT */NBUFFX8_HVT"]
set_lib_cell_purpose -include hold [get_lib_cells "*/DELLN*_RVT */NBUFFX2_RVT
*/NBUFFX4_RVT */NBUFFX8_RVT"]

#################################################
## Final Task with ccd enabled
#################################################

current_scenario func.ss_125c
set_path_margin -setup -to [get_pins I_BLENDER_1/s2_op*_reg[*]/D] 1.0 set_path_margin -setup -to [get_pins
I_BLENDER_1/s4_op*_reg[*]/D] 1.0 report_qor -summary

set_app_options -name clock_opt.flow.enable_ccd -value true

remove_routes -global_route cts_specs clock_opt_ccd_enabled

clock_opt
cts clock_opt_ccd_enabled

######## ROUTING ##########

##Scenario settings

set_scenario_status -active true [all_scenarios]

##Instance prefix

set_app_options -name [Link].user_instance_name_prefix value "PNR_ROUTE_"

set_app_options -name [Link].timing_driven -value true set_app_option -name [Link].timing_driven -value true
set_app_option -name [Link].crosstalk_driven -value true
##Crosstalk enable

set_app_options -name time.si_enable_analysis -value true

route_auto

add_redundant_vias // replaces all single cut vias by 2-cut via arrays connect_pg_net -automatic

save_block -as Routed

##reporting file mkdir route_reports set report_dir route_reports
set report_prefix route ## Constraint violations
redirect -file ${report_dir}/${report_prefix}.report_constraint {report_constraint -all_violators -max_transition -max_capacitance
scenarios [all_scenarios]}

redirect -file ${report_dir}/${report_prefix}.report_timing.max {report_timing -delay max -scenarios [all_scenarios] -input_pins -

nets -transition_time -capacitance -attributes -physical -derate -report_by group}

analyze_design_violations -type setup -stage postroute -output ${report_dir}/${report_prefix}.analyze_design_violations

redirect -tee -file ${report_dir}/${report_prefix}.report_utilization
{report_utilization}

redirect -file ${REPORTS_DIR}/${REPORT_PREFIX}.report_design

{report_design -library -netlist -floorplan -routing} redirect -file ${report_dir}/${report_prefix}.check_legality
{check_legality -verbose}

##CTS specific reports

redirect -tee -file

${report_dir}/${report_prefix}.report_clock_qor.summary
{report_clock_qor}

redirect -file ${report_dir}/${report_prefix}.report_clock_qor.latency

{report_clock_qor -type latency -show_paths} redirect -file
${report_dir}/${report_prefix}.report_clock_qor.cell_area
{report_clock_qor -type area}

redirect -file
${report_dir}/${report_prefix}.report_clock_qor.structure
{report_clock_qor -type structure}

redirect -file
${report_dir}/${report_prefix}.report_clock_qor.drc_violators
{report_clock_qor -type drc_violators -all}

#Route specific

redirect -file ${report_dir}/${report_prefix}.check_routes

{check_routes}

redirect -file ${report_dir}/${report_prefix}.check_lvs {check_lvs max_errors 0}

#######post route#######
##Scenario settings
set_scenario_status -active true [all_scenarios]

##Instance prefix

set_app_options -name [Link].user_instance_name_prefix value "PNR_ROPT"

###Lib cell dont use

set_lib_cell_purpose -include optimization [get_lib_cells {*/*LVT}] set_lib_cell_purpose -exclude optimization [get_lib_cells

{*/CK* */*D24* */*D32* */*D20* */*D18*}]

##Cells for hold fixing

set_lib_cell_purpose -include hold [get_lib_cells {*/DEL* */BUFFD1BWP* */BUFFD2BWP*}]

route_track

rouet_global route_detail route_opt

connect_pg_net -automatic

save_block -as Post_route

##reporting

file mkdir route_opt_reports set report_dir route_opt_reports set

report_prefix route_opt ## Constraint violations
redirect -file ${report_dir}/${report_prefix}.report_constraint {report_constraint -all_violators -max_transition -max_capacitance
scenarios [all_scenarios]}

redirect -file ${report_dir}/${report_prefix}.report_timing.max {report_timing -delay max -scenarios [all_scenarios] -input_pins -

nets -transition_time -capacitance -attributes -physical -derate -report_by group}

redirect -file ${report_dir}/${report_prefix}.report_timing.min {report_timing -delay min -scenarios [all_scenarios] -input_pins -

nets transition_time -capacitance -attributes -physical -derate -report_by group}

analyze_design_violations -type setup -stage postroute -output

${report_dir}/${report_prefix}.analyze_design_violations

redirect -tee -file ${report_dir}/${report_prefix}.report_utilization

{report_utilization}

redirect -file ${REPORTS_DIR}/${REPORT_PREFIX}.report_design {report_design -library -netlist -floorplan -routing}

#redirect -tee -file
${report_dir}/${report_prefix}.report_congestion.rpt
{report_congestion -layers [get_layers -filter
"layer_type==interconnect"] -rerun_global_router -nosplit} redirect -file ${report_dir}/${report_prefix}.check_legality
{check_legality -verbose} }

INNOVUS COMMANDS
INNOVUS commands at floorplan stage:

1) create_floorplan -box_size {die_box io_box core_box}

The create_floorplan command initializes the floorplan and calls the add_tracks command to create new routing tracks.

2) create_row -area {x1 y1 x2 y2}

Create rows in the specified rectangle

3) create_tracks -direction -layer -num -start -step

Creates non uniform and customized tracks in the selected design area
-direction — specifies tracks direction as a string
-start —starting co-ordinate to create the track
-layer —specifies the routing layer used for the tracks, more than 1 layer can specified
-step —specifies the spacing between the tracks
-num —specifies the number of tracks to create for the grid

4) delete_tracks -direction -layer

Delete the set of tracks in the database for a given metal layer.

5)edit_pin -pin_name -location -edge -layer -snap {track} -spacing Modifies the properties of pins, such as pin
spreading, pin location, width and depth etc

6)init_design
To load the netlist file

7) read_def
Load a DEF file containing the floorplan saved by any tool.
Load the DEF file containing the scan chain information so that the placement can do scan chain reorder.

8) snap_floorplan {-all | -selected }

Snap floorplan command is used to snap blocks, I/O Pads, standard cells to the FINFET grid.

9) check_place
Checks FIXED and PLACED cells for violations, adds violations markers to the display area, and generates the
violation report.

10) add_io_buffers
Adds buffers/inverters to the I/O pins and places the buffers/inverters near the I/O pins.

11) check_pin_assignment
Sanity checks with respect to port placement like spacing, allignment with tracks, allingment with proper metal layer
etc.
12) legalize_pins -keep_layer -keep_order
This command moves a pin to the nearest legal location. Moves a pin from its existing location in the following
cases: /
 Pin overlap with any other object or pin.
 If the pin is not in the non preffered layer, a non reserved layer, or the metal layer.
 If the pin is not on the routing track.
 If the pin does not honor corner mask settings.
-keep_layer — Maintains the pin layer while legalizing the pins.
-keep_order — Maintains the pin order while legalizing the pins.

13) create_route_blockage
Creates an area which prevents which prevents routing of specified metal layer, signal routes and hierarchical
instances. {-insts name} - blockage over a particular instance {-layers layer name} -blockage over particular
layer
{-rects {x1 y1 x2 y2} … { } } - specifies the rectangular area of the blockage
{polygon {x1 y1 x2 y2} …{ } } -specifies the polygon area of the blockage {-except_pg_nets} - applies routing blockage
to all the nets except PG nets

14) create_place_blockage
Creates a placement blockage for the specified area.
-rects {x1 y1 x2 y2} -area of the blockage
-all_macros -keeps the placement blockage around all macro
-type -hard/soft/{-partial -density -exclude_flops}/macro only
 hard -niether standard cell nor macros may be placed in the blockage
 soft - allows only buffers, inverters, isolation cells, clock gates, tie cells and level shifters.
 partial -creates a placement blockage that has a maximum density as specified (sometime excludes flops
and latches too)
 macro_only - enable proto_design command to keep macros out of the placement blockage
-inst instance name - specifies the name of instances in which placement blockage has to be applied.

15) add_endcaps
Places physical only end cap cells at the end of site rows. add_endcaps is always done after floorplan and before
add_well_taps {-rect x1 y1 x2 y2} — boundary box.
{-core_boundary_only} —specifies that endcaps cells are placed within the core boundary.
{-power_domain power domain name} —specifies the power domain name in which the endcaps are inserted.

16) add_well_taps
Add physical only well tap cells. Well tap cells are physical only filler cells that are required by some technology
libraries to limit the resistance between power and ground connections.
{-area x1 y1 x2 y2} -specifies the co ordinates of all row in which well tap needed to be placed
{-cell_interval microns} -specifies the maximum distance from the center of one well tap to the other well tap
{-checker_board} —places the well tap in checker board pattern

17) add_decaps
Adds decoupling capacitance to the end of design.
[-place_status] -keep the place status of macro as fixed or placed
[-area lllx lly urx ury | -exclude _areas { {lax lly urx ury} … { } ] -defines the entire area in which decaps are to be added
[-pg_net net name] —add decaps to the specified power rail.
18) check_floorplan -report_density
Checks the quality of the floorplan to detect potential problems before the design is passed on to other tools.
{-outfile filename} - outputs detailed information for the specified blocks.
{-report_density} - Reports target utilization( (TU) and effective utilization (EU) for the entire design, fences and
regions.

19) create_place_halo
Adds a halo to the block. A halo is an area that prevents the placement of standard cells within the specified halo
distance from the edge of a hard macro to avoid congestion.
{-all_blocks} — add halo around all hard macros, black boxes and commited partitions.
{-all_io_pads} —add halo around all IO Pads.
{-cell name} —Add halo around all instances of cell.

Sanity check after Powerplan:

1) check_connectivity
Detects conditions such as opens, unconnected, wires(geometric antennas), unconnected pins, loops, partial
routing and unrouted nets and generates violation marker in the design window; reports violations. {-out_file
filename} specifies the report file for connectivity violation data

2)check_power_vias
This command checks missing powergrid vias.
{-area {x1 y1 x2 y2}} specifies the co-ordinates of the area to be checked {-report filename } specifies the
name of output file for the report. {-what_if_report filename } write out the violations data into an ECO file that
can be used directly as an input for what if rail analysis

3) check_drc
Checks for the DRC Violations and creates violation markers in the design database that can be seen on the
GUI and browsed with the violation browser.
{-area {x1 y1 x2 y2} … {} } checks DRC within the specified area
{-out_file filename} specifies the report file that contains DRC violations information.

4) add_rings -around {each_block} -layer {layer1 layer2} -offset {a b c d} -spacing {value} -width {value}
Create rings for the specified nets around the core boundary or selected blocks.
5) add_stripes -area
Creates power strips within the specified area.
update_power_vias
Adds power vias to the design or perform one of the following actions to
existing power vias:
 Modies the power vias
 Deletes the power vias
 Fixes the vias that violate LEF minimum cut rule

INNOVUS command Placement:

1) set_cell_padding
Add cell padding to the specified instance
{-cells leaf cell name}
{-padding right | left | top |bottom}

2) set_inst_padding creates cell padding for entire

hierarchy of instances.
{-inst instance name}
{-padding number of sites | [-right_side numofsites] [-left_side numofsites] [-top_side
numofsites] [-bottom_side numofsites]

3)create_group
Command for creating fence, region, guide, cluster
{-name group_name} Name of the created group {-type fence/region/guide/cluster}
specifies the type of group to create {-density value} specifies the placement density
percentage {-rects {x1 y1 x2 y2}……{ } } specifies the coordinates of the rectangle for
fence, region and guide

4)group_path
Creates group path in the design, and identifies them with the path group name.
{-name path group name } specifies the name of path group {-from fromlist} List of
pins, instances at the start of path {-through throughlist } list of pins, instances where
the paths go through {-to to list } list of pins, instances where the path ends

5) place_connected
Magnetic placement
{-attractor_pin pinlist} specifies hard macros/IOs/fixed standard cells for attracting
standard cells.
{-attractor macrolist } places only standard cells connected with specified pins of
attractor close to attractor.
{-sequential all_connected} pulls sequential cells connected close to the attractor.

6) place_opt_design
Executes pre-CTS with both placement and pre CTS optimization. {-expanded_views} prints
timing information for each active view at the end of the command.
{-incremental} specifies the “place_opt_design” to run incremental mode
{-num_paths numofpaths} specifies the number of paths to be reported in the timing report.
{-report_dir directoryname} specifies the output directory in which the timing/DRV reports will
be saved.
{report_prefix outfilename} specifies the file name that is generated at the end of
place_opt_design.

NOTE - place_opt_design is made from two commands which were used separately
place_design and opt_design -pre_cts.

7) opt_design
Performs timing optimization before or after the clock tree is built, or after routing and
generates timing reports.
{-drv} — corrects max_cap and max_trans violations, if we want to correct fanout_load we
have to first specify opt_fix_load attribute before you specify opt_design.

{-expanded_views} generates detailed view-specific timing reports at the reports at the ends
of opt_design command.

{-hold} corrects hold violations.

{-hold_vioaltion_report filename} generates the following report files for the remaining
violation that remain after hold fixing.

{-incremental} performs setup optimization incrementally on the violated paths until they
cannot be optimized more. Both WNS and TNS are optimized.

{-post_cts} performs timing optimization o design whose clock tree has been created.

{-post_route} performs timing optimaztion on the design whose routing is complete.

{-pre_cts} performs timing optimization on the place design, before the clock tree is built.

{-report_dir directoryname} reports are generated in the given directory.

{-setup} corrects setup violations for the post_route optimization flow. When -hold parameter
is given, a combined setup and hold optimization is performed.

8) report_congestion
Reports the average congestion and the local hotspot score.
{-hotspot} reports the local hotspot score. It reports the local and total hotspot area.
{-overflow} reports horizontal and vertical overflow. {-3d} honors 3d
congestion map.

9) set_db opt_multi_bit_flop_opt true

To enable multi bit flip flop conversion

10) set_db opt_power_effort

medium/high To enable leakage power
optimization.

INNOVUS Commands CTS stage:

1) ccopt_design
Performs clock concurrent optimization (CCOpt) on the current loaded design in Innovus.
{-check _cts_config} checks that all the prerequites for running the clock tree synthesis are
fulfilled without actual doing CTS.

2) create_clock_tree_spec
Create a clock tree network with associated skew groups and other clock tree synthesis
(CTS) configuration setting such as ignore pins, case analysis, max trans etc.
{-out_file filename} writes this clock tree specification script file in Stylus UI format.
{-views} specifies the TCL list of analysis view names.

3) delete_clock_tree_spec
This command deletes all the skew group definitions and other clock tree synthesis
configuration information.

INNOVUS command Routing Stage:

1) route_design
Runs routing per postroute via or wire optimization using the nanoroute router. Using without
any arguments runs global and detailed routing.

{-placement_check} -checks for placement violation before routing.

{-track_opt} perform timing optimization after track assignment.
{-via_opt} optimizes vias after routing

2) opt_design -post_route
Performs timing optimization after post route.

3) time_design -report_dir filename

Runs early global route, extraction and timing analysis, and generates detailed timing
reports. The generated timing reports are saved in the directory that you specified using -
report_dir