Digital System Design (EC- 20005)

Module-4
Sequential Circuits

Prof. (Dr.) Amitkumar V. Jha

School of Electronics Engineering (SOEE)
KIIT Deemed to be University

Disclaimer: The contents in this slide have been referred from many sources including [1] and [2] which I do not claim as my own. Some of the content has been modified for easier
understanding of the students without any malafide intention. This slide is only for educational purpose strictly, and not for the commercial purpose.
[1] Morris Mano, and Michael D. Ciletti, “Digital Design”, Fifth Edition, PHI, 2012.
[2] Samir Palnitkar, “Verilog HDL”, Second Edition, Pearson Education, 2003.
 Contents

• Latch (NAND based SR latch)

• Flip-flop (SR, D, JK, T, Master-Slave)
• Triggering of flip-flops
• Flip-flop conversion
• Shift register using D flip-flop (SISO, SIPO, PISO, PIPO)
• Counter design (Synchronous and asynchronous)

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Latch (NAND based)
• Latches are digital circuits that store a single bit of information and
hold its value until it is updated by new input signals.
• They are used in digital systems as temporary storage elements to
store binary information.
• Latches can be implemented using various digital logic gates, such as
AND, OR, NOT, NAND, and NOR gates.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 SR Latch using NAND Gates

• S-R (Set-Reset) Latches

• S-R latches are the simplest form of latches and are implemented using two
inputs: S (Set) and R (Reset).
• The S input sets the output to 1, while the R input resets the output to 0.
• When both S and R are at 1, the latch is said to be in an “undefined” state.
• They are also known as preset and clear states. The SR latch forms the basic
building blocks of all other types of flip-flops.
• SR Latch is a circuit with:
(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
(ii) 2 input S for SET and R for RESET.
(iii) 2 output Q, Q’.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 Working of SR Latch using NAND Gates
Case 1: 𝑆ҧ = 0, 𝑅ത = 0 Case 2: 𝑆ҧ = 0, 𝑅ത = 1

Case 3: 𝑆ҧ = 1, 𝑅ത = 0 Case 4: 𝑆ҧ = 1, 𝑅ത = 1
Note that the two
outputs i.e., Q and
Q’ are complement
to each other.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Some Key points
• Latches are basic storage elements that operate with signal levels (rather than signal
transitions).
• Latches are level-sensitive devices.
• Latches are useful for the design of the asynchronous sequential circuit.
• Latches are sequential circuit with two stable states.
• Latches are sensitive to the input voltage applied and does not depend on the clock
pulse.
• Latches controlled by a clock transition are flip-flops.
• Flip flops that do not use clock pulse are referred to as latch.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Types of Triggering
• Following are the two possible types of triggering that are used in sequential circuits.
• Level triggering
• Edge triggering
• Level triggering: There are two levels, namely logic High and logic Low in clock signal.
Following are the two types of level triggering.
• Positive level triggering
• Negative level triggering

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Types of Triggering: Level Triggering
• If the sequential circuit is operated with the clock signal when it is in Logic High, then
that type of triggering is known as Positive level triggering. It is highlighted in below
figure.

• If the sequential circuit is operated with the clock signal when it is in Logic Low, then
that type of triggering is known as Negative level triggering. It is highlighted in the
following figure.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Types of Triggering: Edge Triggering
• There are two types of transitions that occur in clock signal. That means, the clock signal
transitions either from Logic Low to Logic High or Logic High to Logic Low.
• Following are the two types of edge triggering based on the transitions of clock signal.
• Positive edge triggering
• Negative edge triggering

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 • If the sequential circuit is operated with the clock signal that is transitioning from Logic
Low to Logic High, then that type of triggering is known as Positive edge triggering. It is
also called as rising edge triggering. It is shown in the following figure.

• If the sequential circuit is operated with the clock signal that is transitioning from Logic
High to Logic Low, then that type of triggering is known as Negative edge triggering. It is
also called as falling edge triggering. It is shown in the following figure.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Flip-Flop
• Flip-flop is a circuit that maintains a state until directed by input to change the state.
• A flip flop is a sequential circuit which consist of single binary state of information or
data.
• The digital circuit is a flip flop which has two outputs and are of opposite states.
• It is also known as a Bistable Multivibrator.
• Types of flip-flops:
• SR Flip Flop
• JK Flip Flop
• D Flip Flop
• T Flip Flop

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

S-R Flip Flop
• The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and RESET.
The SET input 'S' set the device or produce the output 1, and the RESET input 'R' reset
the device or produce the output 0. The SET and RESET inputs are labeled as S and R,
respectively.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

S-R Flip Flop: Logic Diagram and Truth Table

SR Flip-Flop Truth Table

Clock S R Qn+1 State
Active 0 0 Qn No Change
Active 0 1 0 Reset
Active 1 0 1 Set
Active 1 1 X Invalid

Note: Clock must be active to get the output.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 S-R Flip Flop: Characteristics Equation
• The characteristic equation is an algebraic expression for the characteristic table’s binary information.
• It specifies the value of the next state of a flip-flop in terms of its present state and present excitation.
• To obtain the characteristic equation of SR flip-flop, the K-map for the next state Qn+1 in terms of present state
and inputs should be solved which is as shown below.

S R Qn Qn+1
0 0 0 0 (No change)

0 0 1 1 (No change)
The characteristic equation of SR flip-flop from
0 1 0 0 (Reset) the above K-map is
0 1 1 0 (Reset)

1 0 0 1 (Set)

1 0 1 1 (Set)

1 1 0 X (Invalid)

1 1 1 X (Invalid) © Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Excitation Table of SR Flip-Flop
• In the designing of sequential circuits, we often face situations where the present state
and the next state of the flip-flop are specified, and we must determine the input
conditions that must exist in order for the intended output condition to occur.
• The excitation table of SR flip-flop indicate the excitations required to take the flip-flop
from the present state to the next state.
• The excitation table of SR flip-flops is as follows:

Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
J-K Flip Flop

• The JK flip flop is basically a gated SR flip-flop with the addition of a

clock input circuitry that prevents the illegal or invalid output
condition that can occur when both inputs S and R are equal to logic
level “1”.
• Due to this additional clocked input, a JK flip-flop can be given with
both inputs high.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 J-K Flip Flop: Logic Diagram and Truth Table

JK Flip-Flop Truth Table

Clock J K Qn+1 State
Active 0 0 Qn No change
Active 0 1 0 Reset
Active 1 0 1 Set
Active 1 1 𝑄𝑛 Toggle

Note: Clock must be active to get the output.

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs called the J and K inputs, respectively after its inventor Jack Kilby.
Then this equates to: J = S and K = R.
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
 J-K Flip Flop: Characteristics Equation
• To obtain the characteristic equation of JK flip-flop, the K-map for the next state Qn+1 in terms of present state
and inputs should be solved which is as shown below.

J K Qn Qn+1
0 0 0 0 (No change)

0 0 1 1 (No change)
The characteristic equation of JK flip-flop from
0 1 0 0 (Reset) the above K-map is
0 1 1 0 (Reset)

1 0 0 1 (Set)

1 0 1 1 (Set)

1 1 0 1 (Toggle)

1 1 1 0 (Toggle) © Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Excitation Table of JK Flip-Flop
• The excitation table of SR flip-flop indicate the excitations required to take the flip-flop
from the present state to the next state.
• The excitation table of SR flip-flops is as follows:

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

D Flip Flop
• It ensures that at the same time, both the inputs, i.e., S and R, are never equal to 1.
• The Delay flip-flop is designed using a gated SR flip-flop with an inverter connected between the
inputs allowing for a single input D(Data).
• This single data input, which is labeled as "D" used in place of the "Set" input and for the
complementary "Reset" input, the inverter is used.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

D Flip Flop: Logic Diagram and Truth Table

D Flip-Flop Truth Table

Clock D Qn+1
Active 0 0
Active 1 1

Note: Clock must be active to get the output.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 D Flip Flop: Characteristics Equation
• To obtain the characteristic equation of D flip-flop, the K-map for the next state Qn+1 in terms of present state
and inputs should be solved which is as shown below.

D Qn Qn+1
0 0 0

0 1 0
The characteristic equation of T flip-flop from the
1 0 1 K-map is

1 1 1

Q(n+1) = D

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Excitation Table of D Flip-Flop
• The excitation table of T flip-flop indicate the excitations required to take the flip-flop
from the present state to the next state.
• The excitation table of T flip-flops is as follows:

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

T Flip Flop
• In T flip flop, "T" defines the term "Toggle".
• We can construct the "T Flip Flop" by making changes in the "JK Flip Flop".
• The "T Flip Flop" has only one input, which is constructed by connecting the input of JK
flip flop. This single input is called T.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

T Flip Flop: Logic Diagram and Truth Table

T Flip-Flop Truth Table

Clock T Qn+1 State
Active 0 Qn No change
Active 1 𝑄𝑛 Toggle

Note: Clock must be active to get the output.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 T Flip Flop: Characteristics Equation
• To obtain the characteristic equation of T flip-flop, the K-map for the next state Qn+1 in terms of present state
and inputs should be solved which is as shown below.

T Qn Qn+1
0 0 0 (No change)

0 1 1 (No change)
The characteristic equation of T flip-flop from the
1 0 1 (toggle) above K-map is
1 1 0 (toggle)

Q(n+1) = TQn’ + T’Qn = T XOR Qn

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Excitation Table of T Flip-Flop
• The excitation table of T flip-flop indicate the excitations required to take the flip-flop
from the present state to the next state.
• The excitation table of T flip-flops is as follows:

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Flip-flop Conversion
• One flip can be converted to another flip flop using some additional combination circuits.
• Steps to convert one flip flop to another are:
• Consider the characteristic table of desired flip-flop.
• Fill the excitation values inputs of given flip-flop for each combination of present state and next state.
• Get the simplified expressions for each excitation input.
• Draw the circuit diagram of desired flip-flop according to the simplified expressions
using given flip-flop and necessary logic gates.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 Flip Flop Conversion: SR to D flip flop
Characteristics Table of Desired Flip Flop Excitation Table of given flip
flop
Desired FF Input Present State Next State Given Flip flop input
D Qn Qn+1 S R
0 0 0 0 X
0 1 0 0 1
1 0 1 1 0
1 1 1 X 0
Now, we can use K-map for obtaining the simplified Boolean expression for the given flip flop inputs in terms
of desired flip flop inputs and present state:

After solving, you will get:

• 𝑆=𝐷
• 𝑅=𝐷 ഥ
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
 Flip Flop Conversion: SR to JK flip flop
Characteristics Table of Desired Flip Flop Excitation Table of given flip flop

Desired FF Input Present State Next State Given flip flop input
J K Qn Qn+1 S R
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X Reference

0 1 1 0 0 1
1 0 0 1 1 0
1 0 1 1 X 0
1 1 0 1 1 0
1 1 1 0 0 1

Now, we can use K-map for obtaining the simplified Boolean After solving, you will get:
expression for the given flip flop inputs in terms of desired flip • 𝑆 = 𝐽𝑄𝑛
flop inputs and present state: • 𝑅 = 𝐾𝑄𝑛
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
 Flip Flop Conversion: JK to T flip flop
Characteristics Table of Desired Flip Flop Excitation Table of given flip
flop
Desired FF Input Present State Next State Given flip flop input
T Qn Qn+1 J K
0 0 0 0 X
0 1 1 X 0
Reference
1 0 1 1 X
1 1 0 X 1

Now, we can use K-map for obtaining the simplified Boolean After solving, you will get:
expression for the given flip flop inputs in terms of desired flip • 𝐽=𝑇
flop inputs and present state: • 𝐾=𝑇
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
HYU
• Convert
• SR flip flop to T flip flop
• JK flip flop to D flip flop
• JK flip flop to SR flip flop
• D flip flop to T flip flop
• T flip flop to D flip flop

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Key point
• Flip flops can be used to store a single bit of binary data (1 or 0).

Question: How multiple bit can be stored?

• In order to store multiple bits of data, we need multiple flip-flops.

• N flip flops are to be connected in order to store n bits of data.
• A Register is a device that is used to store such information. It is a group of flip-
flops connected in series used to store multiple bits of data.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Shift Register
• Shift Register is a group of flip flops used to store multiple bits of data.
• The bits stored in such registers can be made to move within the registers and in/out of
the registers by applying clock pulses.
• An n-bit shift register can be formed by connecting n flip-flops where each flip-flop stores
a single bit of data.

• There are following types of shift register:

• Serial In Serial Out shift register (SISO)
• Serial In parallel Out shift register (SIPO)
• Parallel In Serial Out shift register (PISO)
• Parallel In parallel Out shift register (PIPO)

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

SISO Shift Register
• The shift register, which allows serial input (one bit after the other through a single data
line) and produces a serial output is known as a Serial-In Serial-Out shift register.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 • In n-bit SISO shift register,
• n clock pulses are required
to load the data
• (n-1) clock pulse are
required to get the data as
serial output

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

SIPO Shift Register
• The data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left
or right direction under clock control.

• In n-bit SIPO shift register,

• n clock pulses are required
to load the data
• 0 clock pulse are required
to get the data as parallel
output

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

PIPO Shift Register
• The parallel data is loaded simultaneously into the register, and transferred together to
their respective outputs by the same clock pulse.

• In n-bit PIPO shift register,

• 1 clock pulses are required
to load the data
• 0 clock pulse are required
to get the data as parallel
output

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

PISO Shift Register
• The parallel data is loaded into the register simultaneously and is shifted out of the register
serially one bit at a time under clock control.

• In n-bit PISO shift register,

• 1 clock pulses are
required to load the
data
• (n-1) clock pulse are
required to get the data
as serial output

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Counters
• The counter is one of the major applications of flip-flops.
• A counter is a sequential circuit, which counts the number of pulses produced
by the clock input.
• The value of the counter represents the number of clock pulses arrived at the
clock input.
• When the clock pulses are counted in an increasing way, it is called up
counter. E.g.,: 0 1 2  3  0
• In the down counter, the count value is decremented by one on the arrival of
each clock pulses. E.g.,: 3 2 1 0  3

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

• Counters are constructed with a series of flip-flops.
• Based on the input and the clock pulses given to the flip-flops, there are several
types of counter as listed below.
• Asynchronous counter: It consists of a series of flip flops, in which the
output of each flip flop is connected to the clock input of the next higher-
order flip flop. The flip flops in the asynchronous counter are triggered
individually, that is, they are not synchronized. It is also also called a Ripple
counter.
• Synchronous counter: If each flip flop in the counter is triggered at the
same time through the clock pulse input, it is said to be synchronous
counter.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

• The number of flip-flops determines the count limit or number of states.
• The n-bit counter will have n number of flip flops and has 2n distinct output states. STATES =
2 number of flip flops
• For example, 2-bit counter has 2 flip lops and has 22 = 4 distinct states (00, 01, 10, 11).
• Each binary counter has a maximum count limit, which is given by 2n – 1.
• For example, a 3-bit counter can have a maximum count of 23 – 1 = 7 (in binary, it is
equivalent to ‘111’).
• After reaching the maximum count of a counter, the counter will reset itself for the next
clock pulse input and starts to count again.
• The total number of counts that a counter counts is called the modulus of counter.
• It is also the number of distinct states that a counter can have.
• For example, the mod-3 counter has 8 stable states and it has a total count of 8. It
indicates that the modulus of the 3-bit counter is 8.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 Question: Find out the total number flip-flops and all possible counting
states for modulus-12 counter.

• A Modulus-12 counter would count from 0 (0000) to 11 (1011) and

requires four flip-flops (16 states - 12 used).

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Design of Synchronous Counter
• Following steps can be used to design any synchronous counter:
• Determine the number of flip-flops required
• Draw the state diagram
• Selection of flip-flops and excitation table
• Obtain the minimized expression for excitations
• Draw the logic diagram

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Example: Design a synchronous counter using D flip flops that goes through states 0, 1,
2, 4, 0. The unused states must always go to zero on the next clock pulse.

• Number of flip flop required: This synchronous counter has four stable states, i.e. 0 (000), 1 (001), 2 (010), 4
(100). But we require three (instead of 2) flip flops because it counts 4 (100) as well. Since three flip-flops
can count eight states. Thus, the remaining four states, i.e. 3 (011), 5 (101), 6 (110), and 7 (111) are unused
states. As per the problem statement, the unused states must go to 0 (000) after the next clock pulse.
Therefore, there are no don’t care states.
• State diagram: The state diagram of the 0, 1, 2, 4, 0, … counter is drawn as shown in the following figure.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 • Selection of flip-flops and excitation table: Lets use D flip flop

Present State Next State Required

Excitation
Q3 Q2 Q1 Q3 Q2 Q1 D3 D2 D1
Obtain the minimized expression for excitations
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 1 0 0 1 0 0
0 1 1 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0
1 0 1 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0
© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
Draw the logic diagram

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
Design 1 bit asynchronous up counter

• The output frequency will be f/2 (If f is clock frequency).

• It is known as binary or mod 2 counter or bit ripple counter.
• It has 2 unique output states (0 and 1)

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 Design mod 4 ripple counter

• If there are n FFs then the output • The output frequency of Q1 is f/4(if f is clock frequency).
frequency will be divide by 2n. Also It can generate 4 different unique states. This is known as
generate 2n unique states. divide by 4 circuits or mod 4 ripple counter.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
Design a 3 bit asynchronous Down Counter

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU
Alternative way: 3-bit asynchronous Down Counter

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

Key points to remember for ripple counter

• The frequency division basically forms a counting state in ripple counter.

• Here we are seeing that the output of the 1st FF acts as clock for 2nd FF.
• Suppose the FF takes 30ns for generating output(i.e. propagation delay because of gates).
Therefore, the output of the second FF will be obtained after 60 ns.
• So the propagation delay ripples through the FFs and becomes more when the number of
FFs increases.
• Therefore, asynchronous counters are too slow for generating big counting.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

 Design 3 bit Asynchronous up/down counter
• It is used more than separate up or down counter.
• In this a mode control input (say M) is used for selecting up and down mode.
• A combinational circuit is required between each pair of flip-flop to decide whether to do up
or do down counting.
• Decision for Mode control input

• When M = 0, then Y= Q, therefore it will perform Up

counting.
• When M = 1, then Y= Q’ therefore it will perform Down
counting.
• Combinational circuit is required for deciding mode
control(i.e whether counter will perform Up counting or
Down counting).

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

• So the all possible combinations are

• K-map for finding output Y that will be

given as clock to next FF.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

• Insertion of Combinational logic between every pair of FFs

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

• Timing diagram :

• Initially Q3 = 0, Q2 = 0, Q1 = 0.

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU

© Prof. (Dr.) Amitkumar V. Jha, School of Electronics Engineering, KIIT-DU