(a) The following table shows part of the instruction set for a processor.

The processor has one

general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to ACC
Indirect addressing: The address to be used is at the given address. Load the
LDI <address>
contents of this second address to ACC
Indexed addressing. Form the address from <address> + the contents of the
LDX <address>
Index Register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
MOV <register> Move the contents of the accumulator to the given register (IX)
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
Bits in ACC are shifted logically n places to the left. Zeros are introduced on
LSL #n
the right hand end
Bits in ACC are shifted logically n places to the right. Zeros are introduced on
LSR #n
the left hand end
<address> can be an absolute address or a symbolic address
# denotes a denary number, e.g. #123

S-21-11
The current contents of the main memory and selected values from the ASCII character set
are shown.

Address Instruction ASCII code table (selected codes only)

200 LDD 365 ASCII code Character
201 CMP 366 65 A
202 JPE 209 66 B
203 INC ACC 67 C
204 STO 365 68 D
205 MOV IX
206 LDX 365
207 OUT
208 JMP 200
209 END

365 1
366 3
367 65
368 66
IX 0

S-21-11
Complete the trace table for the program currently in main memory.

Instruction Memory address

ACC IX Output
address 365 366 367 368

1 3 65 66 0

[6]

S-21-11
(b) (i) The Accumulator currently contains the binary number:

0 0 1 1 0 1 0 1

Write the contents of the Accumulator after the processor has executed the following
instruction:

LSL #2

[1]

(ii) The Accumulator currently contains the binary number:

0 0 1 1 0 1 0 1

Identify the mathematical operation that the following instruction will perform on the
contents of the accumulator.

LSR #3
...........................................................................................................................................

..................................................................................................................................... [1]

S-21-11
 2 The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
Direct addressing. Load the contents of the location at the given address to
LDD <address>
ACC
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
DEC <register> Subtract 1 from the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
# denotes a denary number, e.g. #123

The current contents of the main memory and selected values from the ASCII character set are:

Address Instruction ASCII code table (selected codes only)

70 IN ASCII code Character
71 CMP 100 65 A
72 JPE 80 66 B
73 CMP 101 67 C
74 JPE 76 68 D
75 JMP 80
76 LDD 102
77 INC ACC
78 STO 102
79 JMP 70
80 LDD 102
81 DEC ACC
82 STO 102
83 JMP 70

100 68
101 65
102 100

S-21-12
(a) Complete the trace table for the program currently in main memory when the following
characters are input:

A D
Do not trace the program any further when the third input is required.

Instruction Memory address

ACC
address 100 101 102
68 65 100

[4]

S-21-12
 (b) Some bit manipulation instructions are shown in the table:

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
<address> can be an absolute address or a symbolic address
# denotes a denary number, e.g. #123

The contents of the memory address 300 are shown:

Bit Number 7 6 5 4 3 2 1 0

300 0 1 1 0 0 1 1 0

(i) The contents of memory address 300 represent an unsigned binary integer.

Write the denary value of the unsigned binary integer in memory address 300.

..................................................................................................................................... [1]

(ii) An assembly language program needs to test if bit number 2 in memory address 300
is a 1.

Complete the assembly language instruction to perform this test.

......................... #4
[1]

(iii) An assembly language program needs to set bit numbers 4, 5, 6 and 7 to 0, but keep
bits 0 to 3 with their existing values.

Write the assembly language instruction to perform this action.

...........................................................................................................................................

..................................................................................................................................... [2]

S-21-12
 (a) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The current contents of main memory are shown:

Address Data
100 00001111
101 11110000
102 01010101
103 11111111
104 00000000

W-21-11
 Each row of the following table shows the current contents of ACC in binary and the instruction
that will be performed on those contents.

Complete the table by writing the new contents of the ACC after the execution of each
instruction.

Current contents of the ACC Instruction New contents of the ACC

11111111 OR 101

00000000 XOR #15

10101010 LSR #2

01010101 AND 104

[4]

W-21-11
 (a) The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
STO <address> Store the contents of ACC at the given address
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP <address> Compare the contents of ACC with the contents of <address>
JPN <address> Following a compare instruction, jump to <address> if the compare was False
JMP <address> Jump to the given address
IN Key in a character and store its ASCII value in ACC
OUT Output to the screen the character whose ASCII value is stored in ACC
END Return control to the operating system
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123

The current contents of main memory are shown:

Address Data
100 01010101
101 11110000
102 00001111
103 00000000
104 11111111

W-21-12
 (i) In the following table, each row shows the current contents of the ACC in binary and the
instruction that will be performed on those contents.

Complete the table by writing the new contents of the ACC after the execution of each
instruction.

Current contents of the ACC Instruction New contents of the ACC

01010101 XOR 101

11110000 AND 104

00001111 LSL #4

11111111 OR 102

[4]

(ii) The following table contains five assembly language instruction groups.

Write an appropriate assembly language instruction for each instruction group, using the
given instruction set. The first one has been completed for you.

Instruction Group Instruction

Data movement LDM #2

Input and output of data

Arithmetic operations

Unconditional and conditional instructions

Compare instructions

[4]

W-21-12
(iii) The opcode LDM uses immediate addressing. The opcode LDD uses direct addressing.

Identify and describe one additional mode of addressing.

Mode of addressing ...........................................................................................................

Description ........................................................................................................................

...........................................................................................................................................

...........................................................................................................................................
[2]

W-21-12
 (a) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
XOR #n Bitwise XOR operation of the contents of ACC with the operand
OR #n Bitwise OR operation of the contents of ACC with the operand
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are
introduced on the right hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are
introduced on the left hand end
# denotes a denary number, e.g. #123

(i) Complete the register to show the result after the instruction AND #2 is executed.

Register before: 0 1 1 0 1 1 0 1

Register after:

[1]

(ii) Complete the register to show the result after the instruction OR #8 is executed.

Register before: 0 1 1 0 1 1 0 1

Register after:

[1]

S-22-11
(iii) Complete the register to show the result after the operation LSL #4 is executed.

Register before: 0 1 1 0 1 1 0 1

Register after:

[1]

S-22-11
The table shows part of the instruction set for a processor. The processor has one general purpose
register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
Bitwise AND operation of the contents of ACC with the contents
AND <address>
of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
Bitwise XOR operation of the contents of ACC with the contents
XOR <address>
of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
Bitwise OR operation of the contents of ACC with the contents of
OR <address>
<address>
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123

(a) The ACC currently contains the following positive binary integer:

0 1 1 0 0 1 0 1

Write the bit manipulation instruction that would change the binary integer in ACC to:

1 1 1 1 1 1 1 1

Opcode ..................................................... Operand .....................................................

[2]

(b) The ACC currently contains the following positive binary integer:

0 1 1 0 0 1 0 1

Write the bit manipulation instruction that would change the binary integer in ACC to:

1 0 0 1 1 0 1 0

Opcode ..................................................... Operand .....................................................

[2]

S-22-12
(c) Convert the following positive binary integer into hexadecimal.

01111110
............................................................................................................................................. [1]

(d) A three-place logical shift to the left is performed on the following positive binary integer.

Show the result of this logical shift.

01111110

............................................................................................................................................. [1]

(e) Convert the denary numbers 127 and 12 to 8-bit binary and then perform the subtraction
12 − 127 in binary.

Show your working.

127 in binary .............................................................................................................................

12 in binary ...............................................................................................................................

12 − 127 in binary .....................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[3]

S-22-12
(a) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
Direct addressing. Load the contents of the location at the
LDD <address>
given address to ACC
Indirect addressing. The address to be used is at the given
LDI <address>
address. Load the contents of this second address to ACC
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123

The current contents of main memory are:

Address
100 101
101 67
102 104
103 100
104 68

Complete the table by writing the value stored in the accumulator after the execution of each
instruction.

Instruction Accumulator
LDM #103

LDD 102

LDI 103

[3]

S-22-13
(b) The instructions in part (a) are examples of the data movement group.

Describe two other instruction groups.

1 ................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................
[4]

S-22-13
(c) The table shows part of the instruction set for a processor. The processor has one general
purpose register, the Accumulator (ACC).

Instruction
Explanation
Opcode Operand
AND Bn Bitwise AND operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the operand
OR Bn Bitwise OR operation of the contents of ACC with the operand
B denotes a binary number, e.g. B01001010

The binary value 00111101 is stored in the memory address 200.

Each instruction in the diagram is performed on the data in memory address 200.

Draw one line from each instruction to its correct result.

Instruction Result

01111101

XOR B11110000
00111101

OR B01010101 11111111

AND B11111111 11000010

11001101

[3]

S-22-13
The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
LDX <address> Indexed addressing. Form the address from <address> + the
contents of the index register. Copy the contents of this calculated
address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
CMP #n Compare the contents of ACC with number n
JPE <address> Following a compare instruction, jump to <address> if the
compare was True
JPN <address> Following a compare instruction, jump to <address> if the
compare was False
OUT Output to the screen the character whose ASCII value is stored in
ACC
END Return control to the operating system
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

W-22-11
 (a) The current contents of main memory and selected values from the ASCII character set are
given.

(i) Trace the program currently in memory using the trace table.

Instruction Memory address

ACC IX Output
Address Instruction address 100 101 110 111 112
77 LDR #0
0 0 66 65 35
78 LDX 110
79 CMP #35
80 JPE 92
81 ADD 100
82 STO 101
83 LDM #1
84 ADD 100
85 STO 100
86 INC IX
87 LDX 110
88 CMP #35
89 JPN 81
90 LDD 100
91 ADD #48
92 OUT
93 END
…
100 0
101 0
…
110 66
111 65
112 35

ASCII
Character
value
49 1
50 2
51 3
52 4

65 A
66 B
67 C
68 D

[4]

W-22-11
 (ii) The following instructions are repeated for your reference.

Instruction
Explanation
Opcode Operand
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
STO <address> Store contents of ACC at the given address

State the purpose of this part of an assembly language program.

LDD 100
STO 165
LDD 101
STO 100
LDD 165
STO 101
...........................................................................................................................................

...........................................................................................................................................
[1]

W-22-11
 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given address to
ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents of the
index register. Copy the contents of this calculated address to ACC
LDR #n Immediate addressing. Load the number n to IX
STO <address> Store the contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP <address> Compare the contents of ACC with the contents of <address>
CMI <address> Indirect addressing. The address to be used is at the given address. Compare
the contents of ACC with the contents of this second address
JPE <address> Following a compare instruction, jump to <address> if the compare was True
JPN <address> Following a compare instruction, jump to <address> if the compare was False
END Return control to the operating system
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

W-22-12
 (a) Trace the program currently in memory using the trace table, stopping when line 90 is
executed for a second time.

Address Instruction Instruction Memory address

ACC IX
address 100 101 102 103 110 111 112
75 LDR #0

LDX 110 0 0 112 4 1 4 0

76

77 CMI 102

78 JPE 91

79 CMP 103

80 JPN 84

81 ADD 101

82 STO 101

83 JMP 86

84 INC ACC

85 STO 101

86 LDD 100

87 INC ACC

88 STO 100

89 INC IX

90 JMP 76

91 END

100 0

101 0

102 112

103 4

110 1

111 4

112 0

[5]

W-22-12
 (b) The following table shows another part of the instruction set for the processor.

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR Bn Bitwise XOR operation of the contents of ACC with the binary number n
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

The contents of memory addresses 50 and 51 are shown:

Memory address Data value

50 01001101

51 10001111

(i) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

XOR B00011111

...........................................................................................................................................

...........................................................................................................................................

[1]

W-22-12
(ii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

AND 50

...........................................................................................................................................

...........................................................................................................................................

[1]

(iii) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

LSL #3

...........................................................................................................................................

...........................................................................................................................................

[1]

(iv) The current contents of the ACC are:

0 1 0 1 0 0 1 1

Show the contents of the ACC after the execution of the following instruction.

OR 51

...........................................................................................................................................

...........................................................................................................................................

[1]

W-22-12
 The following table shows part of the instruction set for a processor. The processor has one
general purpose register, the Accumulator (ACC), and an Index Register (IX).

Instruction
Explanation
Opcode Operand
LDM #n Immediate addressing. Load the number n to ACC
LDD <address> Direct addressing. Load the contents of the location at the given
address to ACC
LDX <address> Indexed addressing. Form the address from <address> + the contents
of the index register. Copy the contents of this calculated address to
ACC
LDR #n Immediate addressing. Load the number n to IX
MOV <register> Moves the contents of the accumulator to the given register (IX)
STO <address> Store contents of ACC at the given address
ADD <address> Add the contents of the given address to the ACC
ADD #n Add the denary number n to the ACC
SUB #n Subtract the denary number n from the ACC
INC <register> Add 1 to the contents of the register (ACC or IX)
JMP <address> Jump to the given address
CMP #n Compare the contents of ACC with number n
CMI <address> Indirect addressing. The address to be used is at the given address.
Compare the contents of ACC with the contents of this second
address
JPE <address> Following a compare instruction, jump to <address> if the compare
was True
JPN <address> Following a compare instruction, jump to <address> if the compare
was False
OUT Output to the screen the character whose ASCII value is stored in
ACC
END Return control to the operating system
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

W-22-13
 (a) The current contents of main memory and selected values from the ASCII character set are
given.

(i) Trace the program currently in memory using the trace table.

Instruction Memory address

Address Instruction ACC IX Output
LDR #0 address 100 101 110 111 112
75
76 LDD 100
1 0 97 98 97
77 CMP #2
78 JPE 91
79 LDX 110
80 SUB #32
81 CMP #65
82 JPN 86
83 LDM #1
84 ADD 101
85 STO 101
86 LDM #1
87 ADD 100
88 STO 100
89 INC IX
90 JMP 76
91 LDD 101
92 ADD #48
93 OUT
94 END

100 1
101 0

110 97
111 98
112 97

ASCII Character
value
49 1
50 2
51 3
52 4

65 A
66 B
67 C
68 D

[4]

W-22-13
 (ii) Explain the purpose of relative addressing in an assembly language program.

...........................................................................................................................................

...........................................................................................................................................

...........................................................................................................................................

..................................................................................................................................... [2]

(b) The following table shows another part of the instruction set for the processor.

Instruction
Explanation
Opcode Operand
AND #n Bitwise AND operation of the contents of ACC with the operand
AND Bn Bitwise AND operation of the contents of ACC with the binary number n
AND <address> Bitwise AND operation of the contents of ACC with the contents of <address>
XOR #n Bitwise XOR operation of the contents of ACC with the operand
XOR <address> Bitwise XOR operation of the contents of ACC with the contents of <address>
OR #n Bitwise OR operation of the contents of ACC with the operand
OR Bn Bitwise OR operation of the contents of ACC with the binary number n
OR <address> Bitwise OR operation of the contents of ACC with the contents of <address>
LSL #n Bits in ACC are shifted logically n places to the left. Zeros are introduced on
the right-hand end
LSR #n Bits in ACC are shifted logically n places to the right. Zeros are introduced on
the left-hand end
<address> can be an absolute or a symbolic address
# denotes a denary number, e.g. #123
B denotes a binary number, e.g. B01001101

(i) The current contents of the ACC are:

0 0 1 1 0 1 1 0

Show the contents of the ACC after the execution of the following instruction.

AND B01001100
...........................................................................................................................................

...........................................................................................................................................

[1]

W-22-13
 (ii) The current contents of the ACC are:

1 0 0 1 0 1 0 1

Show the contents of the ACC after the execution of the following instruction.

OR B01001111
...........................................................................................................................................

...........................................................................................................................................

[1]

(iii) The current contents of the ACC are:

1 0 0 1 1 1 0 1

Show the contents of the ACC after the execution of the following instruction.

LSR #2
...........................................................................................................................................

...........................................................................................................................................

[1]

(c) One instruction group is data movement.

Give the name of one other instruction group.

...................................................................................................................................................

............................................................................................................................................. [1]

W-22-13