Next Generation computer Architectures
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Next-Gen Computer Architecture. Smruti R. Sarangi 2
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Advanced Computer Architecture Prof. [Link] Jose 4
Advanced Computer Architecture Prof. [Link] Jose
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Advanced Computer Architecture Prof. [Link] Jose 6
Background Required to Understand Advanced
architecture design
Assembly Languages
Basic Processor Design
Basic Pipeline Design
Next-Gen Computer Architecture | Smruti R. Sarangi 7
The Moore’s Law has Ended
10000000000
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Number of transistors per chip (log
100000000
00
1000000
00
100000
0
1000
0
10
0
scale)
1
a 7 7 7 7 8 8 8 9 9 9 9 0 0 0 0 0 0 0 0 0 1 1 1
Ye 19 19 19 19 19 19 19 19 19 19 19 20 20 20 20 20 20 20 20 20 20 20 20
r 1 2 4 9 2 5 9 3 5 8 9 0 1 2 3 4 5 6 7 9 3 4 5
Ye
ar
Till roughly 2015, the number of transistors per chip was
increasing exponentially.
Next-Gen Computer Architecture | Smruti R. Sarangi 8
Moore’s Law and Dennard Scaling
Moore’s Law
The number of transistors per chip will double
roughly every 1-2 years. By 2023 this trend will
altogether stop.
Dennard Scaling
• The power-density remains constant.
• The performance per Watt increases
exponentially (tracking Moore’s law).
Next-Gen Computer Architecture | Smruti R. Sarangi 9
Our Journey so Far …
Increase the issue width of our regular 5-stage in-order pipelines
20-50% increase in performance
Next-Gen Computer Architecture | Smruti R. Sarangi 10
Move from In-order to OOO Processors
Execute instructions out of order (not in program order)
Next-Gen Computer Architecture | Smruti R. Sarangi 11
Transition from In-order to Out-of-Order
2-4X increase in performance
Next-Gen Computer Architecture | Smruti R. Sarangi 12
Single Core Performance Saturated
From single cores we started moving to multiple cores
Next-Gen Computer Architecture | Smruti R. Sarangi 13
We did not stop there …
Multiple
GPUs
cores
Single
cores
Multiple cores +
accelerators
• The 2010-20 decade belonged to multicore
processors.
• GPUs were repurposed to execute general-purpose
programs
Next-Gen Computer Architecture | Smruti R. Sarangi 14
Need for a High-Performance Memory System
• The memory system has become immensely complicated
• There are elaborate protocols for optimizing the access time of
on-chip caches
• We need an elaborate on-chip network
Cache design On-chip Networks
Theory of Multiprocessor Main Memory and
Systems Nonvolatile Memory
Next-Gen Computer Architecture | Smruti R. Sarangi 15
Assorted Issues
Power and temperature are major issues.
Reliability: transient faults and hard errors.
Parameter variation: variations in the process,
voltage, and temperature
Security
Next-Gen Computer Architecture | Smruti R. Sarangi 16
Architectures for Machine Learning
• This is the future.
• Dedicated on-chip accelerators for
accelerating computer vision, machine
learning and speech processing.
Next-Gen Computer Architecture | Smruti R. Sarangi 17
Next-Gen Computer Architecture | Smruti R. Sarangi 18
Next-Gen Computer Architecture | R. Pacalet 19
Next-Gen Computer Architecture | R. Pacalet 20
Next-Gen Computer Architecture | R. Pacalet 21
Next-Gen Computer Architecture | Smruti R. Sarangi 22
Next-Gen Computer Architecture | R. Pacalet 23
Next-Gen Computer Architecture | Smruti R. Sarangi 24
Next-Gen Computer Architecture | Smruti R. Sarangi 25
Next-Gen Computer Architecture | Smruti R. Sarangi 26
Next-Gen Computer Architecture | Smruti R. Sarangi 27
The
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