Main Memory

Operating System Concepts – 9th Edition Silberschatz, Galvin and Gagne ©2013
 Background

 Program must be brought (from disk) into memory and

placed within a process for it to be run
 Main memory and registers are only storage CPU can
access directly
 Memory unit only sees a stream of addresses + read
requests, or address + data and write requests
 Register access in one CPU clock (or less)
 Main memory can take many cycles, causing a stall
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation

8.2
 Base and Limit Registers
 A pair of base and limit registers define the logical address space
 CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user

8.3
Hardware Address Protection

8.4
 Address Binding
 Programs on disk, ready to be brought into memory to execute form an
input queue
 Without support, must be loaded into address 0000
 Inconvenient to have first user process physical address always at 0000
 How can it not be?
 Further, addresses represented in different ways at different stages of a
program’s life
 Source code addresses usually symbolic
 Compiled code addresses bind to relocatable addresses
 i.e. “14 bytes from beginning of this module”
 Linker or loader will bind relocatable addresses to absolute addresses
 i.e. 74014
 Each binding maps one address space to another

8.5
 Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a

separate physical address space is central to proper memory
management
 Logical address – generated by the CPU; also referred to
as virtual address
 Physical address – address seen by the memory unit
 Logical address space is the set of all logical addresses
generated by a program
 Physical address space is the set of all physical addresses
generated by a program

8.6
 Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical
address
 Many methods possible, covered in the rest of this chapter
 To start, consider simple scheme where the value in the
relocation register is added to every address generated by a
user process at the time it is sent to memory
 Base register now called relocation register
 MS-DOS on Intel 80x86 used 4 relocation registers
 The user program deals with logical addresses; it never sees the
real physical addresses
 Execution-time binding occurs when reference is made to
location in memory
 Logical address bound to physical addresses

8.7
 Dynamic relocation using a relocation register

 Routine is not loaded until it is

called
 Better memory-space utilization;
unused routine is never loaded
 All routines kept on disk in
relocatable load format
 Useful when large amounts of
code are needed to handle
infrequently occurring cases
 No special support from the
operating system is required
 Implemented through program
design
 OS can help by providing libraries
to implement dynamic loading

8.8
 Swapping
 A process can be swapped temporarily out of memory to a
backing store, and then brought back into memory for continued
execution
 Total physical memory space of processes can exceed
physical memory
 Backing store – fast disk large enough to accommodate copies
of all memory images for all users; must provide direct access to
these memory images
 Roll out, roll in – swapping variant used for priority-based
scheduling algorithms; lower-priority process is swapped out so
higher-priority process can be loaded and executed
 Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped
 System maintains a ready queue of ready-to-run processes
which have memory images on disk

8.9
Schematic View of Swapping

8.10
 Context Switch Time including Swapping

 If next processes to be put on CPU is not in memory, need to

swap out a process and swap in target process
 Context switch time can then be very high
 100MB process swapping to hard disk with transfer rate of
50MB/sec
 Swap out time of 2000 ms
 Plus swap in of same sized process
 Total context switch swapping component time of 4000ms
(4 seconds)
 Can reduce if reduce size of memory swapped – by knowing
how much memory really being used
 System calls to inform OS of memory use via
request_memory() and release_memory()

8.11
 Context Switch Time and Swapping (Cont.)

 Other constraints as well on swapping

 Pending I/O – can’t swap out as I/O would occur to wrong
process
 Or always transfer I/O to kernel space, then to I/O device
 Known as double buffering, adds overhead
 Standard swapping not used in modern operating systems
 But modified version common
 Swap only when free memory extremely low

8.12
 Contiguous Allocation
 Main memory must support both OS and user processes
 Limited resource, must allocate efficiently
 Contiguous allocation is one early method
 Main memory usually into two partitions:
 Resident operating system, usually held in low memory with
interrupt vector
 User processes then held in high memory
 Each process contained in single contiguous section of
memory

8.13
 Contiguous Allocation (Cont.)
 Relocation registers used to protect user processes from each
other, and from changing operating-system code and data
 Base register contains value of smallest physical address
 Limit register contains range of logical addresses – each
logical address must be less than the limit register
 MMU maps logical address dynamically
 Can then allow actions such as kernel code being transient
and kernel changing size

8.14
Hardware Support for Relocation and Limit Registers

8.15
 Multiple-partition allocation
 Multiple-partition allocation
 Degree of multiprogramming limited by number of partitions
 Variable-partition sizes for efficiency (sized to a given process’ needs)
 Hole – block of available memory; holes of various size are scattered
throughout memory
 When a process arrives, it is allocated memory from a hole large enough to
accommodate it
 Process exiting frees its partition, adjacent free partitions combined
 Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

8.16
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough

 Best-fit: Allocate the smallest hole that is big enough; must

search entire list, unless ordered by size
 Produces the smallest leftover hole

 Worst-fit: Allocate the largest hole; must also search entire list
 Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

8.17
 Fragmentation
 External Fragmentation – total memory space exists to
satisfy a request, but it is not contiguous
 Internal Fragmentation – allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used
 First fit analysis reveals that given N blocks allocated, 0.5 N
blocks lost to fragmentation
 1/3 may be unusable -> 50-percent rule

8.18
 Fragmentation (Cont.)

 Reduce external fragmentation by compaction

 Shuffle memory contents to place all free memory together
in one large block
 Compaction is possible only if relocation is dynamic, and is
done at execution time
 I/O problem
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers
 Now consider that backing store has same fragmentation
problems

8.19
 Segmentation
 Memory-management scheme that supports user view of memory
 A program is a collection of segments
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays

8.20
User’s View of a Program

8.21
Logical View of Segmentation

4
1

3 2
4

user space physical memory space

8.22
 Segmentation Architecture
 Logical address consists of a two tuple:
<segment-number, offset>,

 Segment table – maps two-dimensional physical addresses; each

table entry has:
 base – contains the starting physical address where the
segments reside in memory
 limit – specifies the length of the segment

 Segment-table base register (STBR) points to the segment

table’s location in memory

 Segment-table length register (STLR) indicates number of

segments used by a program;
segment number s is legal if s < STLR

8.23
 Segmentation Architecture (Cont.)
 Protection
 With each entry in segment table associate:
 validation bit = 0  illegal segment
 read/write/execute privileges
 Protection bits associated with segments; code sharing
occurs at segment level
 Since segments vary in length, memory allocation is a
dynamic storage-allocation problem
 A segmentation example is shown in the following diagram

8.24
Segmentation Hardware

8.25
 Paging
 Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
 Avoids external fragmentation
 Avoids problem of varying sized memory chunks
 Divide physical memory into fixed-sized blocks called frames
 Size is power of 2, between 512 bytes and 16 Mbytes
 Divide logical memory into blocks of same size called pages
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and
load program
 Set up a page table to translate logical to physical addresses
 Backing store likewise split into pages
 Still have Internal fragmentation

8.26
 Address Translation Scheme
 Address generated by CPU is divided into:
 Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
 Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

 For given logical address space 2m and page size 2n

8.27
Paging Hardware

8.28
Paging Model of Logical and Physical Memory

8.29
 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

8.30
 Paging (Cont.)

 Calculating internal fragmentation

 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Solaris supports two page sizes – 8 KB and 4 MB
 Process view and physical memory now very different
 By implementation process can only access its own memory

8.31
 Free Frames

Before allocation After allocation

8.32
 Implementation of Page Table
 Page table is kept in main memory
 Page-table base register (PTBR) points to the page table
 Page-table length register (PTLR) indicates size of the page
table
 In this scheme every data/instruction access requires two
memory accesses
 One for the page table and one for the data / instruction
 The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)

8.33
 Implementation of Page Table (Cont.)
 Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide
address-space protection for that process
 Otherwise need to flush at every context switch
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access
next time
 Replacement policies must be considered
 Some entries can be wired down for permanent fast
access

8.34
 Associative Memory

 Associative memory – parallel search

Page # Frame #

 Address translation (p, d)

 If p is in associative register, get frame # out
 Otherwise get frame # from page table in memory

8.35
Paging Hardware With TLB

8.36
8.37
 Effective Access Time
 Associative Lookup =  time unit
 Can be < 10% of memory access time
 Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative
registers
 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access

 Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
EAT = 0.80 x 100 + 0.20 x 200 = 120ns
 Consider more realistic hit ratio ->  = 99%,  = 20ns for TLB search,
100ns for memory access
 EAT = 0.99 x 100 + 0.01 x 200 = 101ns

8.38
 Memory Protection
 Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
 Can also add more bits to indicate page execute-only, and
so on
 Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the
process’ logical address space, and is thus a legal page
 “invalid” indicates that the page is not in the process’
logical address space
 Or use page-table length register (PTLR)
 Any violations result in a trap to the kernel

8.39
Valid (v) or Invalid (i) Bit In A Page Table

8.40
Virtual Memory
 Background (Cont.)
 Virtual memory – separation of user logical memory from
physical memory
 Only part of the program needs to be in memory for execution
 Logical address space can therefore be much larger than physical
address space
 Allows address spaces to be shared by several processes
 Allows for more efficient process creation
 More programs running concurrently
 Less I/O needed to load or swap processes
 Background (Cont.)
 Virtual address space – logical view of how process is
stored in memory
 Usually start at address 0, contiguous addresses until end of
space
 Meanwhile, physical memory organized in page frames
 MMU must map logical to physical
 Virtual memory can be implemented via:
 Demand paging
 Demand segmentation
Virtual Memory That is Larger Than Physical Memory
 Demand Paging
 Could bring entire process into memory
at load time
 Or bring a page into memory only when
it is needed
 Less I/O needed, no unnecessary
I/O
 Less memory needed
 Faster response
 More users
 Similar to paging system with swapping
(diagram on right)
 Page is needed  reference to it
 invalid reference  abort
 not-in-memory  bring to memory
 Lazy swapper – never swaps a page
into memory unless page will be needed
 Swapper that deals with pages is a
pager
 Basic Concepts
 With swapping, pager guesses which pages will be used before
swapping out again
 Instead, pager brings in only those pages into memory
 How to determine that set of pages?
 Need new MMU functionality to implement demand paging
 If pages needed are already memory resident
 No difference from non demand-paging
 If page needed and not memory resident
 Need to detect and load the page into memory from storage
 Without changing program behavior
 Without programmer needing to change code
 Valid-Invalid Bit
 With each page table entry a valid–invalid bit is associated
(v  in-memory – memory resident, i  not-in-memory)
 Initially valid–invalid bit is set to i on all entries
 Example of a page table snapshot:

 During MMU address translation, if valid–invalid bit in page table

entry is i  page fault
Page Table When Some Pages Are Not in Main Memory
 Page Fault

 If there is a reference to a page, first reference to that page will

trap to operating system:
page fault
1. Operating system looks at another table to decide:
 Invalid reference  abort
 Just not in memory
2. Find free frame
3. Swap page into frame via scheduled disk operation
4. Reset tables to indicate page now in memory
Set validation bit = v
5. Restart the instruction that caused the page fault
Steps in Handling a Page Fault
 Aspects of Demand Paging
 Extreme case – start process with no pages in memory
 OS sets instruction pointer to first instruction of process, non-
memory-resident -> page fault
 And for every other process pages on first access
 Pure demand paging
 Actually, a given instruction could access multiple pages -> multiple
page faults
 Consider fetch and decode of instruction which adds 2 numbers
from memory and stores result back to memory
 Pain decreased because of locality of reference
 Hardware support needed for demand paging
 Page table with valid / invalid bit
 Secondary memory (swap device with swap space)
 Instruction restart
 Instruction Restart
 Consider an instruction that could access several different locations
 block move

 auto increment/decrement location

 Restart the whole operation?
 What if source and destination overlap?
 Performance of Demand Paging
 Stages in Demand Paging (worse case)
1. Trap to the operating system
2. Save the user registers and process state
3. Determine that the interrupt was a page fault
4. Check that the page reference was legal and determine the location of the page on the disk
5. Issue a read from the disk to a free frame:
1. Wait in a queue for this device until the read request is serviced
2. Wait for the device seek and/or latency time
3. Begin the transfer of the page to a free frame
6. While waiting, allocate the CPU to some other user
7. Receive an interrupt from the disk I/O subsystem (I/O completed)
8. Save the registers and process state for the other user
9. Determine that the interrupt was from the disk
10. Correct the page table and other tables to show page is now in memory
11. Wait for the CPU to be allocated to this process again
12. Restore the user registers, process state, and new page table, and then resume the
interrupted instruction
 Performance of Demand Paging (Cont.)
 Three major activities
 Service the interrupt – careful coding means just several hundred
instructions needed
 Read the page – lots of time
 Restart the process – again just a small amount of time
 Page Fault Rate 0  p  1
 if p = 0 no page faults
 if p = 1, every reference is a fault
 Effective Access Time (EAT)
EAT = (1 – p) x memory access
+ p (page fault overhead
+ swap page out
+ swap page in )
 Demand Paging Example
 Memory access time = 200 nanoseconds
 Average page-fault service time = 8 milliseconds
 EAT = (1 – p) x 200 + p (8 milliseconds)
= (1 – p x 200 + p x 8,000,000
= 200 + p x 7,999,800
 If one access out of 1,000 causes a page fault, then
EAT = 8.2 microseconds.
This is a slowdown by a factor of 40!!
 If want performance degradation < 10 percent
 220 > 200 + 7,999,800 x p
20 > 7,999,800 x p
 p < .0000025
 < one page fault in every 400,000 memory accesses
 What Happens if There is no Free Frame?

 Used up by process pages

 Also in demand from the kernel, I/O buffers, etc
 How much to allocate to each?
 Page replacement – find some page in memory, but not really in
use, page it out
 Algorithm – terminate? swap out? replace the page?
 Performance – want an algorithm which will result in minimum
number of page faults
 Same page may be brought into memory several times
 Page Replacement

 Prevent over-allocation of memory by modifying page-

fault service routine to include page replacement
 Use modify (dirty) bit to reduce overhead of page
transfers – only modified pages are written to disk
 Page replacement completes separation between logical
memory and physical memory – large virtual memory can
be provided on a smaller physical memory
Need For Page Replacement
 Basic Page Replacement
1. Find the location of the desired page on disk

2. Find a free frame:

- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm to
select a victim frame
- Write victim frame to disk if dirty

3. Bring the desired page into the (newly) free frame; update the page
and frame tables

4. Continue the process by restarting the instruction that caused the trap

Note now potentially 2 page transfers for page fault – increasing EAT
Page Replacement
 Page and Frame Replacement Algorithms

 Frame-allocation algorithm determines

 How many frames to give each process
 Which frames to replace
 Page-replacement algorithm
 Want lowest page-fault rate on both first access and re-access
 Evaluate algorithm by running it on a particular string of memory
references (reference string) and computing the number of page
faults on that string
 String is just page numbers, not full addresses
 Repeated access to the same page does not cause a page fault
 Results depend on number of frames available
 In all our examples, the reference string of referenced page
numbers is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
Graph of Page Faults Versus The Number of Frames
 First-In-First-Out (FIFO) Algorithm
 Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
 3 frames (3 pages can be in memory at a time per process)

15 page faults
 Can vary by reference string: consider 1,2,3,4,1,2,5,1,2,3,4,5
 Adding more frames can cause more page faults!
 Belady’s Anomaly
 How to track ages of pages?
 Just use a FIFO queue
FIFO Illustrating Belady’s Anomaly
 Optimal Algorithm
 Replace page that will not be used for longest period of time
 9 is optimal for the example
 How do you know this?
 Can’t read the future
 Used for measuring how well your algorithm performs
 Least Recently Used (LRU) Algorithm
 Use past knowledge rather than future
 Replace page that has not been used in the most amount of time
 Associate time of last use with each page

 12 faults – better than FIFO but worse than OPT

 Generally good algorithm and frequently used
 But how to implement?
 LRU Algorithm (Cont.)
 Counter implementation
 Every page entry has a counter; every time page is referenced
through this entry, copy the clock into the counter
 When a page needs to be changed, look at the counters to find
smallest value
 Search through table needed
 Stack implementation
 Keep a stack of page numbers in a double link form:
 Page referenced:
 move it to the top
 requires 6 pointers to be changed
 But each update more expensive
 No search for replacement
 LRU and OPT are cases of stack algorithms that don’t have
Belady’s Anomaly
Use Of A Stack to Record Most Recent Page References
 LRU Approximation Algorithms
 LRU needs special hardware and still slow
 Reference bit
 With each page associate a bit, initially = 0
 When page is referenced bit set to 1
 Replace any with reference bit = 0 (if one exists)
 We do not know the order, however
 Second-chance algorithm
 Generally FIFO, plus hardware-provided reference bit
 Clock replacement
 If page to be replaced has
 Reference bit = 0 -> replace it
 reference bit = 1 then:
– set reference bit 0, leave page in memory
– replace next page, subject to same rules
Second-Chance (clock) Page-Replacement Algorithm
 Counting Algorithms

 Keep a counter of the number of references that have been made

to each page
 Not common

 Lease Frequently Used (LFU) Algorithm: replaces page with

smallest count

 Most Frequently Used (MFU) Algorithm: based on the argument

that the page with the smallest count was probably just brought in
and has yet to be used
 Applications and Page Replacement

 All of these algorithms have OS guessing about future page

access
 Some applications have better knowledge – i.e. databases
 Memory intensive applications can cause double buffering
 OS keeps copy of page in memory as I/O buffer
 Application keeps page in memory for its own work
 Operating system can given direct access to the disk, getting out
of the way of the applications
 Raw disk mode
 Bypasses buffering, locking, etc
 Allocation of Frames
 Each process needs minimum number of frames
 Example: IBM 370 – 6 pages to handle SS MOVE instruction:
 instruction is 6 bytes, might span 2 pages
 2 pages to handle from
 2 pages to handle to
 Maximum of course is total frames in the system
 Two major allocation schemes
 fixed allocation
 priority allocation
 Many variations
 Fixed Allocation
 Equal allocation – For example, if there are 100 frames (after
allocating frames for the OS) and 5 processes, give each process
20 frames
 Keep some as free frame buffer pool

 Proportional allocation – Allocate according to the size of process

 Dynamic as degree of multiprogramming, process sizes
change
m = 64
si  size of process pi s1 = 10
S   si s2 = 127
m  total number of frames a1 =
10
´ 62 » 4
137
s
ai  allocation for pi  i  m 127
S a2 = ´ 62 » 57
137
 Priority Allocation

 Use a proportional allocation scheme using priorities rather

than size

 If process Pi generates a page fault,

 select for replacement one of its frames
 select for replacement a frame from a process with lower
priority number
 Global vs. Local Allocation
 Global replacement – process selects a replacement frame
from the set of all frames; one process can take a frame from
another
 But then process execution time can vary greatly
 But greater throughput so more common

 Local replacement – each process selects from only its own

set of allocated frames
 More consistent per-process performance
 But possibly underutilized memory
 Thrashing
 If a process does not have “enough” pages, the page-fault rate is
very high
 Page fault to get page
 Replace existing frame
 But quickly need replaced frame back
 This leads to:
 Low CPU utilization
 Operating system thinking that it needs to increase the
degree of multiprogramming
 Another process added to the system

 Thrashing  a process is busy swapping pages in and out

Thrashing (Cont.)
 Demand Paging and Thrashing
 Why does demand paging work?
Locality model
 Process migrates from one locality to another
 Localities may overlap

 Why does thrashing occur?

 size of locality > total memory size
 Limit effects by using local or priority page replacement
Locality In A Memory-Reference Pattern
 Working-Set Model
   working-set window  a fixed number of page references
Example: 10,000 instructions
 WSSi (working set of Process Pi) =
total number of pages referenced in the most recent  (varies in time)
 if  too small will not encompass entire locality
 if  too large will encompass several localities
 if  =   will encompass entire program
 D =  WSSi  total demand frames
 Approximation of locality
 if D > m  Thrashing
 Policy if D > m, then suspend or swap out one of the processes
 Keeping Track of the Working Set
 Approximate with interval timer + a reference bit
 Example:  = 10,000
 Timer interrupts after every 5000 time units
 Keep in memory 2 bits for each page
 Whenever a timer interrupts copy and sets the values of all
reference bits to 0
 If one of the bits in memory = 1  page in working set
 Why is this not completely accurate?
 Improvement = 10 bits and interrupt every 1000 time units
 Page-Fault Frequency
 More direct approach than WSS
 Establish “acceptable” page-fault frequency (PFF) rate
and use local replacement policy
 If actual rate too low, process loses frame
 If actual rate too high, process gains frame
 Working Sets and Page Fault Rates
 Direct relationship between working set of a process and its
page-fault rate
 Working set changes over time
 Peaks and valleys over time
Disk Scheduling
 Overview of Mass Storage Structure
 Magnetic disks provide bulk of secondary storage of modern computers
 Drives rotate at 60 to 250 times per second
 Transfer rate is rate at which data flow between drive and computer
 Positioning time (random-access time) is time to move disk arm to
desired cylinder (seek time) and time for desired sector to rotate
under the disk head (rotational latency)
 Head crash results from disk head making contact with the disk
surface -- That’s bad
 Disks can be removable
 Drive attached to computer via I/O bus
 Busses vary, including EIDE, ATA, SATA, USB, Fibre Channel,
SCSI, SAS, Firewire
 Host controller in computer uses bus to talk to disk controller built
into drive or storage array
Moving-head Disk Mechanism
 Disk Scheduling
 The operating system is responsible for using hardware
efficiently — for the disk drives, this means having a fast
access time and disk bandwidth
 Minimize seek time
 Seek time  seek distance
 Disk bandwidth is the total number of bytes transferred,
divided by the total time between the first request for service
and the completion of the last transfer
 Disk Scheduling (Cont.)
 There are many sources of disk I/O request
 OS
 System processes
 Users processes
 I/O request includes input or output mode, disk address, memory
address, number of sectors to transfer
 OS maintains queue of requests, per disk or device
 Idle disk can immediately work on I/O request, busy disk means
work must queue
 Optimization algorithms only make sense when a queue exists
 Disk Scheduling (Cont.)
 Note that drive controllers have small buffers and can manage a
queue of I/O requests (of varying “depth”)
 Several algorithms exist to schedule the servicing of disk I/O
requests
 The analysis is true for one or many platters
 We illustrate scheduling algorithms with a request queue (0-199)

98, 183, 37, 122, 14, 124, 65, 67

Head pointer 53
 FCFS
Illustration shows total head movement of 640 cylinders
 SSTF
 Shortest Seek Time First selects the request with the minimum
seek time from the current head position
 SSTF scheduling is a form of SJF scheduling; may cause
starvation of some requests
 Illustration shows total head movement of 236 cylinders
 SCAN

 The disk arm starts at one end of the disk, and moves toward the
other end, servicing requests until it gets to the other end of the
disk, where the head movement is reversed and servicing
continues.
 SCAN algorithm Sometimes called the elevator algorithm
 Illustration shows total head movement of 236 cylinders
 But note that if requests are uniformly dense, largest density at
other end of disk and those wait the longest
SCAN (Cont.)
 C-SCAN
 Provides a more uniform wait time than SCAN
 The head moves from one end of the disk to the other, servicing
requests as it goes
 When it reaches the other end, however, it immediately
returns to the beginning of the disk, without servicing any
requests on the return trip
 Treats the cylinders as a circular list that wraps around from the
last cylinder to the first one
 Total number of cylinders?
C-SCAN (Cont.)
 C-LOOK
 LOOK a version of SCAN, C-LOOK a version of C-SCAN
 Arm only goes as far as the last request in each direction,
then reverses direction immediately, without first going all
the way to the end of the disk
 Total number of cylinders?
C-LOOK (Cont.)