Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 1

 Application – Specific Integrated Circuits [ASIC]

Application Specific Integrated Circuit

Course Code : BEC714A CIE Marks : 50
Teaching Hours/Week (L:T:P:S) : 3:0:0:0 SEE Marks : 50

Total Hours of Pedagogy : 40 Total Marks : 100

Credits : 03 Exam Hours : 03(Theory)

Course Objective: To study and design various ASIC configurations, analyze

Programmable ASIC memories and use CAD tools for ASIC design flow.

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 Application – Specific Integrated Circuits [ASIC]
SYLLABUS
UNIT- I
Introduction to ASICs: Types of ASIC Design, ASIC Design Flow, FPGA design Flow, Programmable
logic device, ASIC cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic Operator, I/O cells.
UNIT- II
ASIC Library Design: Logical effort: Predicting Delay, Logical area and logical
efficiency, Logical paths, multi-stage cells, Optimum delay and number of stages, library
cell design.
Programmable ASIC Logic Cells: MUX as Boolean function generators, Acted ACT:
ACT 1, ACT 2 and ACT 3 Logic Modules, Xilinx LCA: XC3000 CLB, Altera FLEX and
MAX, Programmable ASIC I/O Cells: Xilinx and Altera I/O Block.
UNIT- III
Low-Level Design Entry: Schematic entry: Hierarchical design, The cell library, Names,
Schematic Icons & Symbols, Nets, Schematic Entry for ASICs, Connections, vectored
instances & buses, Edit in place, attributes, Netlist screener.
ASIC Construction: Physical Design, CAD Tools, System partitioning, Estimating ASIC
size. Partitioning: Goals and objectives, Constructive Partitioning, Iterative Partitioning
Improvement, KL, FM and Look Ahead algorithms.

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 Application – Specific Integrated Circuits [ASIC]

UNIT- IV
Floor planning and placement: Goals and objectives, Measurement
of delay in Floor planning, Floor planning tools, Channel definition,
I/O and Power planning and Clock planning.
Placement: Goals and Objectives, Min-cut Placement algorithm,
Iterative Placement Improvement, Time driven placement methods,
Physical Design Flow.
UNIT- V
Floor Planning and Placement and Routing: Physical Design, CAD Tools,
System Partitioning, Estimating ASIC size, partitioning methods. Floor
planning tools, I/O and power planning, clock planning, placement algorithms.
Global Routing, Local Routing, Detail Routing, Special Routing, Circuit
Extraction and DRC.

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 Application – Specific Integrated Circuits [ASIC]

Text Books:
1. Michael John Sebastian Smith, “Application - Specific Integrated Circuits”, Addison- Wesley
Professional, 2005
2. Khosrow Golshan Conexant Systems, Inc. 2007 Springer Science Business Media “Physical Design
Essentials” An ASIC Design Implementation Perspective

Reference Books:
1. Neil H.E. Weste, David Harris, and Ayan Banerjee, “CMOS VLSI Design: A Circuits and Systems
Perspective”, Addison Wesley/ Pearson education 3rdedition, 2011
2. Vikram Arkalgud Chandrasetty, “VLSI Design: A Practical Guide for FPGA and ASIC Implementations”
Springer, ISBN: 978-1-4614-1119-2. 2011
3. Rakesh Chadha, Bhasker J, “An ASIC Low Power Primer”, Springer, ISBN: 978-14614-4270-7.

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 Application – Specific Integrated Circuits [ASIC]

Unit I
Introduction: Types of ASIC Design, ASIC Design Flow, FPGA design Flow, Programmable
logic device, ASIC cell libraries.
CMOS Logic: Data path Logic Cells: Data Path Elements, Adders, Multiplier, Arithmetic
Operator, I/O cells.
(05+05) Hrs

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 Application – Specific Integrated Circuits [ASIC]

Introduction
• ASIC design is a methodology of cost and size reduction of an electronic circuit, product or system through
miniaturization and integration of individual components and their functionality into a single element – an
Application Specific Integrated Circuit (ASIC).
• An electronic product commonly consists of many integrated circuits (ICs) which are interconnected together
to perform a particular function. For example, It was expensive (component cost and assembly cost) and bulky
(all those components required space).
• As competition intensified, the requirement for lower cost and smaller size drove the need for consolidation
and integration of all those individual components into a single ASIC, reducing not only overall cost and size
of the smoke detector but also improving its reliability (fewer parts, fewer things to go wrong).
• Recently, VLSI CMOS has played a crucial role in placing millions of transistors on a single chip, providing
digital system designers with an ability to implement a vast number of gates with complex functionality on a
single IC.
• According to Moore’s Law, the number of gates or transistors doubles after every 18 months and is growing to
extremely high densities per IC. Rapidly growing technology in logic, parallelization, CAD tools, and memory
promises continued advancement in the next 15 years.
• With the help of CAD tools, high-level descriptions can be translated into specific functions such as registers,
microcontrollers, ALU, control units and more.
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 Application – Specific Integrated Circuits [ASIC]

• Modern ASICs combine multiple complex blocks in a single package, including analog elements such as an
amplifier, ADC, PLL and digital elements such as a microcontroller, OTP, ROM, EEPROM, RAM, and other
building blocks. These types of ICs are known as System On Chip (SoC).
• The analog section of the ASIC is designed using primarily transistor-level design techniques and manual
layout processes.
• The digital section of the chip is designed primarily using hardware description languages such as
VHDL/Verilog followed by automated Place and Route (PnR) layout process.

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 Application – Specific Integrated Circuits [ASIC]

Y-Chart of VLSI Design Flow

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 Application – Specific Integrated Circuits [ASIC]

For your reference

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 Application – Specific Integrated Circuits [ASIC]
5. Physical Design:
VLSI Design Flow
o Transforms netlist into actual layout.
Key Steps in the Design Flow:
o Sub-steps shown on the right side of the image:
1. System Specification: o Partitioning: Dividing the design into manageable blocks.
o High-level description of what the chip/system should do o Floorplanning: Arranging blocks on the chip.
(functionality, performance, power, etc.). o Placement: Placing standard cells within blocks.
o Clock Tree Synthesis (CTS): Distributes the clock signal uniformly.
2. Architectural Design: o Routing: Connecting all placed elements via metal layers.
o Defines data path, control units, memory, I/O structures— o Timing Closure: Ensures timing constraints are met.
determines how the system will be built. 6. Physical Verification and Signoff:
3. Functional Design and Logic Design: o DRC: Design Rule Check
o Converts architecture into RTL (Register Transfer Level) using o LVS: Layout Versus Schematic
HDL (like Verilog or VHDL). o ERC: Electrical Rule Check
o Focuses on designing FSMs, Datapath, control logic, etc. 7. Layout post-processing:
4. Circuit Design: o Adds dummy fills, antenna fixes, and prepares the layout for tape-
o Converts logic into transistor-level design. out.
o Focuses on gate sizing, power estimation, timing analysis, etc. 8. Fabrication:
o Sending the final layout to the foundry to manufacture the silicon
chip.
9. Packaging and Testing:
o Choose Packaging types such as Pin Grid Array & Ball Grid Array
based application & cost requirements.
o Testing for Functionality, Timing and Power.
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 Application – Specific Integrated Circuits [ASIC]

Types of ASIC Design

ASICs

Full Custom ASICs Semi-Custom ASICs

Standard Cell Gate Array Based Programmable

Based ASICs ASICs ASICs
• Full-Custom ASICs: Possibly
all logic cells and all mask Channeled GA FPGA
layers customized
• Semi-Custom ASICs: all Channelless GA PLDs
logic cells are pre-designed
and some (possibly all) mask Structured GA
layers customized
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 Application – Specific Integrated Circuits [ASIC]
✓ Full-Custom ASICs

• A Full custom ASIC is one which includes some (possibly all) logic cells that are customized and all
mask layers that are customized.
• A microprocessor is an example of a full-custom IC.
• Designers spend many hours squeezing the most out of every last square micron of microprocessor chip
space by hand.
• Customizing all of the IC features in this way allows designers to include analog circuits,
optimized memory cells, or mechanical structures on an IC, for example.
• Full-custom ICs are the most expensive to manufacture and to design.
• The manufacturing lead time (the time required just to make an IC not including design time) is
typically eight weeks for a full-custom IC.
• These specialized full-custom ICs are often intended for a specific application so, we might call
some of them as full custom ASICs.
• In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or layout
specifically for one ASIC. This means the designer avoids using pretested and pre characterized cells
for all or part of that design.
• This might be because existing cell libraries are not fast enough, or the logic cells are not small
enough or consume too much power.
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 Application – Specific Integrated Circuits [ASIC]
• One has to use full-custom design if the ASIC technology is new or so specialized that there are no
existing cell libraries or because the ASIC is so specialized that some circuits must be custom
designed.
• Fewer and fewer full-custom ICs are being designed because of the problems with these special parts
of the ASIC. The growing member of this family, now a days is the mixed analog/digital ASIC
Advantages:
- Offer highest performance
- Lowest cost (smallest die size)
Disadvantages
- Increased design time
- Increased Complexity
- Higher design cost
- Higher risk.
Some Examples:
- Microprocessor,
- High-Voltage Automobile Control Chips
- Ana-Digi Communication Chips
- Sensors and Actuator
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 Application – Specific Integrated Circuits [ASIC]

✓ Semi-Custom ASICs

• ASICs , for which all of the logic cells are predesigned and some (possibly all) of the mask
layers are customized are called semi custom ASICs.
• Using the predesigned cells from a cell library makes the design , much easier.
• There are two types of semicustom ASICs
(i) Standard-cell–based ASICs
(ii) Gate-array–based ASICs.

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]
✓ Standard-Cell based ASICs
• A cell-based ASIC (cell-based IC, or CBIC pronounced
sea-bick) uses predesigned logic cells (AND gates, OR
gates, multiplexers, and flip-flops, for example) known as
standard cells.
• One can apply the term CBIC to any IC that uses cells, but
it is generally accepted that a cell-based ASIC or CBIC
means a standard-cell based ASIC.
• The standard-cell areas (also called flexible blocks) in a
CBIC are built of rows of standard cells like a wall built of
bricks.
• The standard-cell areas may be used in combination with
microcontrollers or even microprocessors, known as mega
cells.
• Mega cells are also called mega functions, full-custom Figure: A cell-based ASIC (CBIC)
blocks, system-level macros (SLMs), fixed blocks, cores,
or Functional Standard Blocks (FSBs).
• A cell-based ASIC (CBIC) die with a single standard-cell
area (a flexible block) together with four fixed blocks.
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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]

• The ASIC designer defines only the placement of the

standard cells and the interconnect in a CBIC.
• However, the standard cells can be placed anywhere on
the silicon; this means that all the mask layers of a CBIC
are customized and are unique to a particular customer.
• Advantage of CBICs is that designers save time, money,
and reduce risk by using a predesigned, pretested, and
pre characterized standard-cell library.
• In addition each standard cell can be optimized
individually.
• During the design of the cell library each and every
transistor in every standard cell can be chosen to
maximize speed or minimize area
• Disadvantages are the time or expense of designing or
Figure: Layout of a standard cell buying the standard-cell library and the time needed to
fabricate all layers of the ASIC for each new design

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 Application – Specific Integrated Circuits [ASIC]
Standard Cell ASIC Routing
- A “wall” of standard cells forms a flexible block
- Metal2 may be used in a feedthrough cell to cross over cell rows that use metal1 for wiring
- Other wiring cells: spacer cells , row-end cells , and power cells

Figure: Routing the CBIC

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 Application – Specific Integrated Circuits [ASIC]
✓ Gate Array based ASICs

• In a gate-array-based ASIC, the transistors are predefined on the silicon wafer

• The predefined pattern of transistors is called the base array
• The smallest element that is replicated to make the base array is called the base or primitive cell
• The top level interconnect between the transistors is defined by the designer in custom masks -
Masked Gate Array (MGA)
• Design is performed by connecting predesigned and characterized logic cells from a library
(macros)
• After validation, automatic placement and routing are typically used to convert the macro-based
design into a layout on the ASIC using primitive cells
• Types of MGAs:
- Channeled Gate Array
- Channel-less Gate Array
- Structured Gate Array

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]

PMOS

NMOS

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 Application – Specific Integrated Circuits [ASIC]

Standard Mask for Gate Array

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]
Custom Mask

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 Application – Specific Integrated Circuits [ASIC]

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 Application – Specific Integrated Circuits [ASIC]
Channeled Gate Array Channel-less Gate Array
• Only the interconnect is customized • There are no predefined areas set aside for
• The interconnect uses predefined spaces routing - routing is over the top of the gate-
between rows of base cells array devices
• Manufacturing lead time is between two days • Achievable logic density is higher than for
and two weeks channeled gate arrays
• Manufacturing lead time is between two days
and two weeks

Figure: Channel gate-array die Figure: Sea-Of-Gates (SOG) array die

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 Application – Specific Integrated Circuits [ASIC]

Structured Gate Array

• Only the interconnect is customized
• Custom blocks (the same for each design) can be embedded
• These can be complete blocks such as a processor or memory array, or
• An array of different base cells better suited to implementing a specific function
• Manufacturing lead time is between two days and two weeks.

Figure: Gate array die with embedded block

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 Application – Specific Integrated Circuits [ASIC]

Programmable logic device

• Programmable logic devices ( PLDs ) are standard ICs that are available in standard
configurations.
• However, PLDs may be configured or programmed to create a part customized
to a specific application, and so they also belong to the family of ASICs.
• PLDs use different technologies to allow programming of the device.
• They contain an array of AND gates & another array of OR gates.
• There are three kinds of PLDs based on the type of array , which has
programmable feature.
- Programmable Read Only Memory
- Programmable Array Logic
- Programmable Logic Array
• The process of entering the information into these devices is known as
programming. Basically, users can program these devices or ICs electrically
in order to implement the Boolean functions based on the requirement. Here,
the term programming refers to hardware programming but not software
programming
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 Application – Specific Integrated Circuits [ASIC]

✓ Programmable Read Only Memory

• Read Only Memory is a memory device, which stores the binary information permanently. That
means, we can’t change that stored information by any means later.
• If the ROM has programmable feature, then it is called as Programmable ROM .
• The user has the flexibility to program the binary information electrically once by using PROM
programmer. PROM is a programmable logic device that has fixed AND array & Programmable OR
array.
• The block diagram of PROM is shown in the following figure

Inputs Outputs

FIXED Programmable
AND gate OR gate

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 Application – Specific Integrated Circuits [ASIC]
• Here, the inputs of AND gates are not of programmable
type. So, we have to generate 2 product terms by using 2
AND gates having n inputs each. We can implement
these product terms by using nx2 decoder. So, this
decoder generates ‘n’ min terms.
• Here, the inputs of OR gates are programmable. That
means, we can program any number of required product
terms, since all the outputs of AND gates are applied as
inputs to each OR gate. Therefore, the outputs of PROM
will be in the form of sum of min terms.
• Example:

• The given two functions are in sum of min terms form

and each function is having three variables X, Y & Z. So,
we require a 3 to 8 decoder and two programmable OR
gates for producing these two functions. The
corresponding PROM is shown in the following figure

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 Application – Specific Integrated Circuits [ASIC]
✓ Programmable Array Logic
• PAL is a programmable logic device that has Programmable AND array & fixed OR array. The advantage of
PAL is that we can generate only the required product terms of Boolean function instead of generating all the
min terms by using programmable AND gates.
• The block diagram of PAL is shown in the following figure.
Inputs Outputs

Programmable Fixed
AND gate OR gate

• Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND gates.
• Here, the inputs of OR gates are not of programmable type. So, the number of inputs to each OR gate will be of
fixed type. Hence, apply those required product terms to each OR gate as inputs. Therefore, the outputs of PAL
will be in the form of sum of products form.
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 Application – Specific Integrated Circuits [ASIC]

• Example:
• The given two functions are in sum of products form.
There are two product terms present in each Boolean
function. So, we require four programmable AND
gates & two fixed OR gates for producing those two
functions. The corresponding PAL is shown in the
following figure.
• The programmable AND gates have the access of
both normal and complemented inputs of variables. In
the above figure, the inputs X, , Y, , Z & , are available
at the inputs of each AND gate. So, program only the
required literals in order to generate one product term
by each AND gate.
• The symbol ‘X’ is used for programmable
connections.
• Here, the inputs of OR gates are of fixed type. So, the
necessary product terms are connected to inputs of
each OR gate. So that the OR gates produce the
respective Boolean functions. The symbol ‘.’ is used
for fixed connections.
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 Application – Specific Integrated Circuits [ASIC]

✓ Programmable Logic Array

• PLA is a programmable logic device that has both Programmable AND array & Programmable OR array.
Hence, it is the most flexible PLD. The block diagram of PLA is shown in the following figure.

Inputs Outputs

Programmable Programmable
AND gate OR gate

• Here, the inputs of AND gates are programmable. That means each AND gate has both normal and
complemented inputs of variables. So, based on the requirement, we can program any of those inputs. So, we
can generate only the required product terms by using these AND gates.
• Here, the inputs of OR gates are also programmable. So, we can program any number of required product
terms, since all the outputs of AND gates are applied as inputs to each OR gate. Therefore, the outputs of PAL
will be in the form of sum of products form.

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 Application – Specific Integrated Circuits [ASIC]
Example:
• The given two functions are in sum of products form.
The number of product terms present in the given
Boolean functions A & B are two and three respectively.
One product term, is common in each function.
• So, we require four programmable AND gates & two
programmable OR gates for producing those two
functions. The corresponding PLA is shown in the
following figure.
• The programmable AND gates have the access of both
normal and complemented inputs of variables. In the
above figure, the inputs X, , Y, , Z & , are available at
the inputs of each AND gate. So, program only the
required literals in order to generate one product term by
each AND gate.
• All these product terms are available at the inputs of
each programmable OR gate. But, only program the
required product terms in order to produce the
respective Boolean functions by each OR gate. The
symbol ‘X’is used for programmable connections
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 Application – Specific Integrated Circuits [ASIC]

FPGA
(FIELD PROGRAMMABLE GATE ARRAYS)
• FPGA provide the next generation in the programmable logic devices.
• The word Field in the name refers to the ability of the gate arrays to be programmed for a specific
function by the user instead of by the manufacturer of the device.
• The word Array is used to indicate a series of columns and rows of gates that can be programmed by
the end user.
• As compared to standard gate arrays, the field programmable gate arrays are larger devices.
• The basic cell structure for FPGA is some what complicated than the basic cell structure of standard
gate array. The programmable logic blocks of FPGA are called Configurable Logic Block (CLB).
• The FPGA architecture consists of three types of configurable elements-
(i) IOBs – a perimeter of input/output blocks
(ii) CLBs- a core array of Configurable Logic Blocks/Logic blocks
(iii) Resources for interconnection (i.e. Programmable interconnect)

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 Application – Specific Integrated Circuits [ASIC]

Architecture of FPGA

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 Application – Specific Integrated Circuits [ASIC]

• The IOBs provide a programmable interface between the internal, array of logic blocks
(CLBs) and the device’s external package pins.
• CLBs perform user-specified logic functions, and the interconnect resources carry signals
among the blocks.
• A configurable program stored in internal static memory cells determines the logic functions
and the interconnections. The configurable data is loaded into the device during power-up
reprogramming function.
• FPGA devices are customized by loading configuration data into internal memory cells.
• The FPGA device can either actively read its configuration data out of an external serial or
byte-wide parallel PROM (master modes), or the configuration data can be written to the
FPGA devices (slave and peripheral modes).

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 Application – Specific Integrated Circuits [ASIC]

✓ Configurable Logic Block

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 Application – Specific Integrated Circuits [ASIC]

• A CLB is the basic building block of an FPGA. It’s a logic cell that can be configured or
programmed to perform specific functions. These building blocks are connected to the
interconnect block.
• A CLB can be implemented using LUT or multiplexer-based logic. In LUT-based logic, the
block consists of a look-up table, a D flip-flop, and a 2:1 multiplexer. Flip flops are used as
storage elements. The multiplexer selects the appropriate output.
• Each CLB is made up of a certain number of slices.
• Slices are grouped in pairs and arranged in columns. The number of CLBs in a device varies,
according to the vendor and the family of the device. For example, Xilinx’s Spartan 3E FPGA
contains four slices. Each slice is made up of two LUTs and two storage elements.
• The function of the LUT is to implement logic, whereas the dedicated storage elements can
be flip-flops or latches. The CLBs are arranged in an array of rows and columns.

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Illustration of an FPGA building block, using a LUT-based CLB

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 Application – Specific Integrated Circuits [ASIC]

Illustration of an FPGA building block, using an MUX-based CLB.

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 Application – Specific Integrated Circuits [ASIC]

✓ Programmable Interconnect
• The interconnect is the programmable network of signal pathways existing between the inputs and
outputs of a device’s functional elements. This is also known as routing.
• There are several types of routing including local routing for interconnection between:
- LUTs
- Flip-flops and general routing matrix
- General-purpose routing for interconnection between the rows and columns of CLBs
- I/O routing for the purpose of pin-swapping or locking
• Basically, the routing network consists of connecting wires with programmable switches, which can
be configured using any of the programming technologies. There are basically two types of routing
architectures. They are:
- Island Style Routing (also known as Mesh Routing)
- Hierarchical Routing
• In Island style routing architecture, the logic blocks are arranged in a two-dimensional array and
are interconnected using a programmable routing network. This type of routing is widely used in
commercial FPGAs.
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• Many logic blocks are confined to a

local set of connections and
hierarchical routing architecture
makes use of this feature by dividing
the logic blocks into several groups
or clusters.
• If the logic blocks are residing in
the same cluster, then the
hierarchical routing connects them
in a low level of hierarchy.
• If the logic blocks are residing in
different clusters, then wiring is
done over a higher level of
hierarchy.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 54

 Application – Specific Integrated Circuits [ASIC]

For your reference

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 55

 Application – Specific Integrated Circuits [ASIC]

✓ I/O block
• Input/output blocks (IOBs) offer programmable
unidirectional or bidirectional interfaces
between the package pins and the device’s
internal logic.
• There are three signals present within an IOB:
1. The input path to carry data from the pad to
the respective line.
2. The output path that carries data from the
internal logic to the IOB pad via a
multiplexer and a three-state driver.
3. The three-state path, which determines the
output driver’s state of high impedance
• All of the signals come with the option of an
inverter.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 56

 Application – Specific Integrated Circuits [ASIC]

ASIC Design Flow

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 57

 Application – Specific Integrated Circuits [ASIC]
• The sequence of steps to design an ASIC is known as the Design flow . The various steps involved
in ASIC design flow are given below.
1. Design entry : Design entry is a stage where the micro architecture is implemented in a Hardware
Description language like VHDL, Verilog , System Verilog etc. In early days , a schematic editor
was used for design entry where designers instantiated gates. Increased complexity in the current
designs require the use of HDLs to gain productivity. Another advantage is that HDLs are
independent
2. Logic synthesis: Once the logic is designed using HDL or Schematic entry, the next step is to
extract the description of the logic cells and their interconnections. This information is also called as
Netlist.
3. System Partitioning: The next step is to logically divide the entire system into small ASIC sized
blocks.
4. Pre-layout Simulation: Before going into the actual physical layout of the design, a simulation tool
checks the circuit for proper working. In fact, this process is performed at every step so that if any
errors are found, then it would be easy to correct them at this stage itself. The process until this step
is usually regarded as Logical Design. The steps after this are related to the actual physical layout of
the design.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 58

 Application – Specific Integrated Circuits [ASIC]

5. Floor planning: The first step in the physical design is arrange all the blocks of the circuit on the
chip
6. Placement: In this step, the location of the logic cells in a block are set.
7. Routing: Once the placement of the blocks and cells is completed, then it is time to create the
connections between the cells and the blocks.
8. Extraction: The next step is to determine the resistance and capacitance of the interconnections
previously made, since they decide the delay of the signal. Also, the delays are calculated at this
stage.
9. Post-layout Simulation: Once the physical design is complete, the circuit is again tested for
working. The delays previously calculated are also taken into consideration for the simulation
process.
10. Design Rule Check (DRC): Final step is to verify the layout of the entire circuit and check whether
it complies with the design rule specifications.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 59

 Application – Specific Integrated Circuits [ASIC]

FPGA design Flow

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 60

 Application – Specific Integrated Circuits [ASIC]

Economics of ASICs
• On a parts only basis, an FPGA is more expensive per-gate than an MGA, which is in turn more expensive than
a CBIC
• The key is that the fixed cost of the CBIC is higher than the MGA which is higher than the FPGA
✓ Design cost
✓ Fabrication cost
• Total product (or part) cost is a function of fixed cost, variable cost, and the number of products (parts) sold:
total part cost = fixed part cost + variable cost per part X volume of parts

• Example, assume:
• FPGA fixed cost is $21,800, part cost is $39
• MGA fixed cost is $86,000, part cost is $10
• CIBC fixed cost is $146,000, part cost is $18

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 61

 Application – Specific Integrated Circuits [ASIC]

FIXED COST
• The fixed cost is independent of the sales volume, the number of products sold. An important component of
the fixed cost of an integrated circuit is the effort in time and manpower it takes to produce the design.
• This design cost is strongly influenced by the complexity of the design, the aggressiveness of the
specifications, and the productivity of the designer.
• Advanced design methodologies that automate major parts of the design process can help to boost the latter.
Bringing down the design cost in the presence of an ever increasing IC complexity is one of the major
challenges that is always facing the semiconductor industry.
• Additionally, one has to account for the indirect costs, the company overhead that cannot be billed directly to
one product. It includes amongst others the company’s research and development (R&D), manufacturing
equipment, marketing, sales, and building infrastructure.

VARIABLE COST
• This accounts for the cost that is directly attributable to a manufactured product, and is hence proportional to
the product volume. Variable costs include the costs of the parts used in the product, assembly costs, and
testing costs. The total cost of an integrated circuit is now
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 62
 Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 63

 Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 64

 Application – Specific Integrated Circuits [ASIC]

ASIC Cell Libraries

• The cell library is the key part of ASIC design. For a programmable ASIC the FPGA
company supplies you with a library of logic cells in the form of a design kit , you
normally do not have a choice, and the cost is usually a few thousand dollars.
• For MGAs and CBICs you have three choices: the ASIC vendor (the company that will
build your ASIC) will supply a cell library, or you can buy a cell library from a third-party
library vendor , or you can build your own cell library.
• The first choice, using an ASIC-vendor library , requires you to use a set of design tools
approved by the ASIC vendor to enter and simulate your design. You have to buy the tools,
and the cost of the cell library is folded into the NRE.
• Some ASIC vendors (especially for MGAs) supply tools that they have developed in-house.
• For some reason the more common model in Japan is to use tools supplied by the ASIC
vendor, but in the United States, Europe, and elsewhere designers want to choose their own
tools. Perhaps this has to do with the relationship between customer and supplier being
a lot closer in Japan than it is elsewhere.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 65

 Application – Specific Integrated Circuits [ASIC]
• An ASIC vendor library is normally a phantom library —the cells are empty boxes, or phantoms , but contain
enough information for layout (for example, you would only see the bounding box or abutment box in a
phantom version of the cell in Figure).
• After you complete layout you hand off a netlist to the ASIC vendor, who fills in the empty boxes ( phantom
instantiation ) before manufacturing your chip.
• The second and third choices require you to make a buy-or-build decision . If you complete an ASIC design
using a cell library that you bought, you also own the masks (the tooling ) that are used to manufacture your
ASIC. This is called customer-owned tooling ( COT , pronounced “see-oh-tee”).
• A library vendor normally develops a cell library using information about a process supplied by an ASIC
foundry.
• An ASIC foundry (in contrast to an ASIC vendor) only provides manufacturing, with no design help. If the
cell library meets the foundry specifications, we call this a qualified cell library.
• These cell libraries are normally expensive (possibly several hundred thousand dollars), but if a library is
qualified at several foundries this allows you to shop around for the most attractive terms.
• This means that buying an expensive library can be cheaper in the long run than the other solutions for high-
volume production.
• The third choice is to develop a cell library in-house. Many large computer and electronics companies make
this choice. Most of the cell libraries designed today are still developed in-house despite the fact that the
process of library development is complex and very expensive.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 66
 Application – Specific Integrated Circuits [ASIC]

• However created, each cell in an ASIC cell library must contain the following:
✓ A physical layout
✓ A behavioral model
✓ A Verilog/VHDL model
✓ A detailed timing model
✓ A test strategy
✓ A circuit schematic
✓ A cell icon
✓ A wire-load model
✓ A routing model

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 67

 Application – Specific Integrated Circuits [ASIC]

Introduction: Data Logic Cells

• Suppose we wish to build an n -bit adder (that adds two n -bit numbers) and to exploit the regularity of this function in the
layout. We can do so using a datapath structure.
• The following two functions, SUM and COUT implement the sum and carry out for a full adder ( FA ) with two data inputs (A,
B) and a carry in, CIN:
SUM = A ⊕ B ⊕ CIN = SUM(A, B, CIN) = PARITY(A, B, CIN) , -----------(1)
COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN). -----------(2)
• The sum uses the parity function ('1' if there are an odd numbers of '1's in the inputs). The carry out, COUT, uses the 2-of-3
majority function ('1' if the majority of the inputs are '1'). We can combine these two functions in a single FA logic cell,
ADD(A[i ], B[ i ], CIN, S[ i ], COUT), shown in Figure 1(a), where
S[ i ] = SUM (A[ i ], B[ i ], CIN) , -----------(3)
COUT = MAJ (A[ i ], B[ i ], CIN) -----------(4)
• Now we can build a 4-bit ripple-carry adder ( RCA ) by connecting four of these ADD cells together as shown in Figure 1(b). The
i th ADD cell is arranged with the following: two bus inputs A[ i ], B[ i ];
• one bus output S[ i ]; an input, CIN, that is the carry in from stage ( i – 1) below and is also passed up to the cell above as an output;
and an output, COUT, that is the carry out to stage ( i + 1) above. In the 4-bit adder shown in Figure 1(b) we connect the carry
input, CIN[0], to VSS and use COUT[3] and COUT[2] to indicate arithmetic overflow Notice that we build the ADD cell so that
COUT[2] is available at the top of the data path.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 68
 Application – Specific Integrated Circuits [ASIC]

FIGURE 1: A datapath adder. (a) A full-adder (FA) cell with inputs (A and B), a carry in, CIN, sum output,
S, and carry out, COUT. (b) A 4-bit adder. (c) The layout, using two-level metal, with data in m1 and
control in m2. In this example the wiring is completed outside the cell; it is also possible to design the
datapath cells to contain the wiring. Using three levels of metal, it is possible to wire over the top of the
datapath cells. (d) The datapath layout.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 69

 Application – Specific Integrated Circuits [ASIC]

• Figure 1(c) shows a layout of the ADD cell. The A inputs, B inputs, and S outputs all use m1 interconnect
running in the horizontal direction—we call these data signals.
• Other signals can enter or exit from the top or bottom and run vertically across the datapath in m2—we call
these control signals.
• We can also use m1 for control and m2 for data, but we normally do not mix these approaches in the same
structure.
• Control signals are typically clocks and other signals common to elements.
• For example, in Figure 1(c) the carry signals, CIN and COUT, run vertically in m2 between cells.
• To build a 4-bit adder we stack four ADD cells creating the array structure shown in Figure 1(d). In this case
the A and B data bus inputs enter from the left and bus S, the sum, exits at the right, but we can connect A, B,
and S to either side if we want.
• The layout of buswide logic that operates on data signals in this fashion is called a datapath . The module
ADD is a datapath cell or datapath element .
• Just as we do for standard cells we make all the datapath cells in a library the same height so we can adjoin
other datapath cells on either side of the adder to create a more complex datapath.
• When people talk about a datapath they always assume that it is oriented so that increasing the size in bits
makes the datapath grow in height, upwards in the vertical direction, and adding different datapath elements to
increase the function makes the datapath grow in width, in the horizontal direction—but we can rotate and
position a completed datapath in any direction we want on a chip.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 70

 Application – Specific Integrated Circuits [ASIC]

• What is the difference between using a datapath, standard cells, or gate arrays? Cells are placed together in
rows on a CBIC or an MGA, but there is no generally no regularity to the arrangement of the cells within the
rows—we let software arrange the cells and complete the interconnect.
• Datapath layout automatically takes care of most of the interconnect between the cells with the following
advantages:
- Regular layout produces predictable and equal delay for each bit.
- Interconnect between cells can be built into each cell.
• There are some disadvantages of using a datapath:
- The overhead (buffering and routing the control signals, for example) can make a narrow (small
number of bits) datapath larger and slower than a standard-cell (or even gate-array) implementation
- Datapath cells have to be predesigned (otherwise we are using full-custom design) for use in a wide
range of datapath sizes. Datapath cell design can be harder than designing gate-array macros or
standard cells.
- Software to assemble a datapath is more complex and not as widely used as software for assembling
standard cells or gate arrays.
• There are some newer standard-cell and gate-array tools that can take advantage of regularity in a design and
position cells carefully.
• The problem is in finding the regularity if it is not specified. Using a datapath is one way to specify
regularity to ASIC design tools.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 71
 Application – Specific Integrated Circuits [ASIC]

Data Path Elements

• Figure 2 shows some typical datapath symbols for an adder (people rarely use the IEEE standards in ASIC
datapath libraries).
• Here it uses heavy lines (they are 1.5 point wide) with a stroke to denote a data bus (that flows in the horizontal
direction in a datapath), and regular lines (0.5 point) to denote the control signals (that flow vertically in a
datapath).
• At the risk of adding confusion where there is none, this stroke to indicate a data bus has nothing to do with
mixed- logic conventions. For a bus, A[31:0] denotes a 32-bit bus with A[31] as the leftmost or most-significant
bit or MSB , and A[0] as the least-significant bit or LSB . Sometimes we shall use A[MSB] or A[LSB] to refer to
these bits.
• Notice that if we have an n -bit bus and LSB = 0, then MSB = n – 1. Also, for example, A[4] is the fifth bit
on the bus (from the LSB). We use a ' S ' or 'ADD' inside the symbol to denote an adder instead of '+', so we can
attach '–' or '+/–' to the inputs for a subtracter or adder/subtracter.
• Some schematic datapath symbols include only data signals and omit the control signals—but we must not forget
them. In Figure 2, for example, we may need to explicitly tie CIN[0] to VSS and use COUT[MSB] and
COUT[MSB – 1] to detect overflow.
• Why might we need both of these control signals? Table 2.11 shows the process of simple arithmetic for the
different binary number representations, including unsigned, signed magnitude, ones’ complement, and two’s
complement.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 72
 Application – Specific Integrated Circuits [ASIC]

FIGURE 2: Symbols for a datapath adder. (a) A data bus is shown by a heavy line (1.5 point) and a bus
symbol. If the bus is n -bits wide then MSB = n – 1. (b) An alternative symbol for an adder. (c) Control
signals are shown as lightweight (0.5 point) lines.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 73

 Application – Specific Integrated Circuits [ASIC]

Adders
• Addition is one of the basic operation perform in various processing like counting, multiplication
and altering.
• Adders can be implemented in various forms to suit different speed and density requirements. The
truth table of a binary full adder is shown in Figure, along with some functions that will be of
use during the discussion of adders. Adder inputs: A, B, Carry input.
• Output: SUM
• Carry output: CARRY
• Generate signal: G (A B); occurs when
CARRY is internally generated within
adder.
• Propagate signal: P (A + B); when it is
1, C is passed to CARRY.
• In some adders A, B is used as the P
term because it may be reused to
generate the sum term.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 74

 Application – Specific Integrated Circuits [ASIC]

Block Diagram of a 1D Iterative Array

✓ Example: n = 32
• Number of inputs = ?
• Truth table rows = ?
• Equations with huge number of terms
✓ Iterative array takes advantage of the regularity to make design feasible

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 75

 Application – Specific Integrated Circuits [ASIC]

Functional Blocks: Addition

✓ Addition Development:
• Half-Adder(HA), a 2-input bit-wise addition functional block,
• Full-Adder(FA), a 3-input bit-wise addition functional block,
• Ripple Carry Adder, an iterative array to perform binary addition
• Carry-Look-AheadAdder (CLA), a hierarchical structure to improve performance.
• Carry Select Adder
• Carry Skip Adder
• Carry Save Adder

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 76

 Application – Specific Integrated Circuits [ASIC]

Functional Block: Half-Adder

✓ A 2-input, 1-bit width binary adder that performs the following
computations:
X 0 0 1 1
+Y +0 +1 +0 +1
CS 00 01 01 10
✓ A half adder adds two bits to produce a two-bit sum
✓ The sum is expressed as a sum bit , S and a carry bit, C

X Y C S

✓ The half adder can be specified a truth

0 0 0 0
table for S and C
0 1 0 1
1 0 0 1
1 1 1 0
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 77
 Application – Specific Integrated Circuits [ASIC]

Logic Simplification: Half-Adder

S Y C Y
✓ The K-Map for S, C is:
0
11 0 1

X 12 3 X 2
13
✓ This is a pretty trivial map! By inspection:
S= X  Y + X  Y = X  Y
S = (X + Y )  (X + Y )
✓ and
C = XY
C = ((XY ))
✓ These equations lead to several implementations.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 78
 Application – Specific Integrated Circuits [ASIC]

Five Implementations: Half-Adder For your reference

✓ We can derive following sets of equations for a

half-adder:
(a) S = X  Y + X  Y (d) S = (X + Y )  C
C = XY C = (X + Y )
(b) S = (X + Y )  (X + Y ) (e) S = X  Y
C = X Y C = X Y
(c) S = ( C + X  Y ) C = X Y
✓ (a), (b), and (e) are SOP, POS, and XOR implementations for S.
✓ In (c), the C function is used as a term in the AND-NOR
implementation of S, and in (d), the C function is used in a POS term for
S.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 79

 Application – Specific Integrated Circuits [ASIC]

Implementations: Half-Adder For your reference

✓ The most common half

adder implementation is: X
Y S
(e)
S= X  Y C
C = XY

✓ A NAND only implementation is:

C
S = (X + Y )  C X
C = ((XY ))
S
Y

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 80

 Application – Specific Integrated Circuits [ASIC]

Functional Block: Full-Adder

✓ A full adder is similar to a half adder, but includes a carry-in bit from
lower stages. Like the half- adder, it computes a sum bit, S and a carry
bit, C.
• For a carry-in (Z) of 0, it is the same as the
half-adder: Z 0 0 0 0

• For a carry-in (Z) of 1: +Y

X 0
+0 +1
0 1
+0
1
+1
CS 00 01 01 10

Z 1 1 1 1
X 0 0 1 1
+Y +0 +1 +0 +1
CS 01 10 10 11
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 81
 Application – Specific Integrated Circuits [ASIC]

Logic Optimization: Full-Adder

✓ Full-Adder Truth Table: X Y Z C S

0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
✓ Full-Adder K-Map: 1 1 0 1 0
1 1 1 1 1
S Y C Y
1 1 1
0 1 3 2 0 1 3 2
X 1 1 X 1 1 1
4 5 7 6 4 5 7 6
Z Z

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 82

 Application – Specific Integrated Circuits [ASIC]

Equations: Full-Adder

✓ From the K-Map, we get:

S= X Y Z+ X Y Z+XY Z+ XY Z
C = X Y + X Z + Y Z = X Y + (X + Y) Z
✓ The S function is the three-bit XOR function (Odd
Function):
S= X  Y  Z
✓ The Carry bit C is 1 if both X and Y are 1 (the sum is 2), or if
the sum is 1 and a carry-in (Z) occurs. Thus, C can be re-
written as:
C = X Y + (X  Y ) Z
✓ The term X·Y is carry generate.
✓ The term XY is carry propagate.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 83

 Application – Specific Integrated Circuits [ASIC]

Implementation: Full Adder

✓ Full Adder Schematic Ai Bi

Gi
✓ Here X, Y, and Z, and C
(from the previous pages)
are A, B, Ci and Co,
respectively. Also,
G = generate and Pi
P = propagate. Ci

✓ Note: This is really a combination

of a 3-bit odd function (for S) and
Carry logic (for Co): Ci+1 Si
(G = Generate) OR (P =Propagate AND Ci = Carry In)
Ci+1 = G + P · Ci

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 84

 Application – Specific Integrated Circuits [ASIC]

Sequential Adder

✓ 1-bit memory and 2 4-bit memory

✓ Only one full-adder!
✓ 4 clocks to get the output
✓ The 1-bit memory defines the circuit state (0 or 1)

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 85

 Application – Specific Integrated Circuits [ASIC]

BinaryAdders

✓ To add multiple operands, we “bundle” logical signals together into vectors

and use functional blocks that operate on the vectors
✓ Example: 4-bit ripple carry adder: Adds input vectors
A(3:0) and B(3:0) to get Description Subscript Name
a sum vector S(3:0) 3210
✓ Note: carry out of cell i becomes carry in of cell i+1 Carry In 0110 Ci

Augend 1011 Ai
0011
Addend Bi
1110
Sum Si
0011
Carry out Ci+1

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 86

 Application – Specific Integrated Circuits [ASIC]

4-bit Ripple-Carry Binary Adder

✓ A four-bit Ripple Carry Adder made from
four 1-bit Full Adders:
B3 A3 B2 A2 B1 A1 B0 A0

C3 C2 C1
FA FA FA FA C0

C4 S3 S2 S1 S0

74LS283

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 87

 Application – Specific Integrated Circuits [ASIC]

✓ Critical delay
• The propagation of carry from low to high order stages
• 1111 + 0001 is the worst case addition
• Carry must propagate through all bits

S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid

Ai Bi
Gi
C0
S0
C1
S1
Pi
Ci C2
S2
C3
S3
Ci+1
Si C4
T0 T2 T4 T6 T8

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 88

 Application – Specific Integrated Circuits [ASIC]

Ripple-Carry Adders
✓ Critical Delay
• The propagation of carry from low to high order stages

Cin
4 stage adder
0 A 1 N+1
0 B A0 S0 2
N Cin B0 C1 2
Cout
0 A N+2
0 B 1 A1 S1 3
B1 C2 4
late arriving two gate delays
signal to compute Cout A2 S2 5
B2 C3 6

A3 S3 7
B3 Cout 8

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 89

 Application – Specific Integrated Circuits [ASIC]

Ai B i
Gi

Pi
C
i

Ci+1 Si

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 90

 Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 91

 Application – Specific Integrated Circuits [ASIC]
Ai B i
Gi
Carry-Lookahead Logic
✓ Carry generate: Gi = Ai Bi
• Must generate carry when A = B = Pi
Ci
1
✓ Carry propagate: Pi = Ai xor Bi
✓ Sum and Cout can be re- Ci+1 Si
expressed in terms of
generate/propagate:
• Si = Ai xor Bi xor Ci
= Pi xor Ci

• Ci+1 = Gi + Ci Pi

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 92

 Application – Specific Integrated Circuits [ASIC]

• Consider the 4-bit ripple carry adder circuit above. Here the sum S3 can be produced as soon as
the inputs A3 and B3 are given.
• But carry C3 cannot be computed until the carry bit C2 is applied whereas C2 depends on
C1.
• Therefore to produce final steady-state results, carry must propagate through all the states. This
increases the carry propagation delay of the circuit.
• The propagation delay of the adder is calculated as “the propagation delay of each gate times
the number of stages in the circuit”.
• For the computation of a large number of bits, more stages have to be added, which makes the
delay much worse. Hence, to solve this situation, Carry Look-ahead Adder was introduced.
• In this adder, the carry input at any stage of the adder is independent of the carry bits generated at
the independent stages.
• Here the output of any stage is dependent only on the bits which are added in the previous stages
and the carry input provided at the beginning stage.
• Hence, the circuit at any stage does not have to wait for the generation of carry-bit from the
previous stage and carry bit can be evaluated at any instant of time.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 93

 Application – Specific Integrated Circuits [ASIC]

Carry-Lookahead Logic (cont’d)

✓ Re-express the carry logic as follows:

• C1 = G0 + P0C0
• C2 = G1 + P1C1 = G1 + P1G0 + P1P0C0
• C3 = G2 + P2C2 = G2 + P2G1 + P2P1G0 + P2P1P0C0
• C4 = G3 + P3C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0

✓ Each of the carry equations can be implemented with

two-level logic
• All inputs are now directly derived from data inputs and not
• from intermediate carries
this allows computation of all sum outputs to proceed in
parallel

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 94

 Application – Specific Integrated Circuits [ASIC]

Carry-Lookahead Implementation

Ai B i
Gi

Pi
C
i

Ci+1 Si

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 95

 Application – Specific Integrated Circuits [ASIC]

Carry-Lookahead Adder with Cascaded Carry-Lookahead Logic

✓ Carry-lookahead adder
• 4 four-bit adders with internal carry lookahead
• Second level carry lookahead unit extends lookahead to 16 bits

4 4 4 4 4 4 4 4

A[15-12] B[15-12] A[11-8] B[11-8] A[7-4] B[7-4] A[3-0] B[3-0]

4-bit Adder C12 4-bit Adder C8 4-bit Adder C4 4-bit Adder C0
@0
P G P G P G P G
4 4 4 4

S[15-12] S[11-8] S[7-4] S[3-0]

@8 @8 @7 @4
@2 @3 @2 @3 @2 @3 @2 @3
@5 @5 @4

P3 G3 C3 P2 G2 C2 P1 G1 C1 P0 G0
C16 C4 C0 C0
Lookahead Carry Unit @0
@4
P3-0 G3-0
@3 @5

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 96

 Application – Specific Integrated Circuits [ASIC]

Carry-Select Adder
✓ Redundant hardware to make carry calculation go faster
• Compute two high-order sums in parallel while waiting for carry-in
• One assuming carry-in is 0 and another assuming carry-in is 1
• Select correct result once carry-in is finally computed

C8 4-bit adder 1 adder

[7:4]
high

C8 4-bit adder 0
[7:4] adder
low

five 1 0 1 0 1 0 1 0 1 0 C4 4-Bit Adder C0

2:1 mux [3:0]

C8 S7 S6 S5 S4 S3 S2 S1 S0

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 97

 Application – Specific Integrated Circuits [ASIC]

Carry Skip Adder

• As the name indicates, Carry Skip Adder (CSkA) uses skip logic in the propagation of carry . It is
designed to speed up the addition operation by adding a propagation of carry bit around a portion
of entire adder. The carry-in bit designated as Ci. The output of RCA (the last stage) is Ci+4. The
Carry Skip circuitry consists of two logic gates. AND gate accepts the carry-in bit and compares it
with the group of propagated signals.
Pi, Pi+3= (Pi+3)*(Pi+2)*(Pi+1)*Pi & Carry= Ci+4 + (Pi, i+3)* Ci.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 98

 Application – Specific Integrated Circuits [ASIC]

Carry Save Adder

• In Carry Save Adder (CSA), three bits are added parallelly at a time.
• In this scheme, the carry is not propagated through the stages. Instead, carry is stored in present
stage, and updated as addend value in the next stage.
• Hence, the delay due to the carry is reduced in this scheme. The architecture of CSA is shown in
Fig

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 99

 Application – Specific Integrated Circuits [ASIC]

Multiplier
• In many digital signal processing operations - such as correlations, convolution, filtering, and
frequency analysis - one needs to perform multiplication.
• The most basic form of multiplication consists of forming the product of two positive binary
numbers.
• This may be accomplished through the traditional technique of successive additions and shifts, in
which each addition is conditional on one of the multiplier bits. Here is an example.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 100
 Application – Specific Integrated Circuits [ASIC]

• The multiplication process may be viewed to consist of the following two steps:
- Evaluation of partial products.
- Accumulation of the shifted partial products.
• It should be noted that binary multiplication is equivalent to a logical AND operation.
• Thus evaluation of partial products consists of the logical ANDing of the multiplicand and the
relevant multiplier bit.
• Each column of partial products must then be added and, if necessary, any carry values passed to the
next column.
• There are a number of techniques that may be used to perform multiplication.
• In general, the choice is based on factors such as speed, throughput, numerical accuracy, and area.
• As a rule, multipliers may be classified by the format in which data words are accessed, namely:-
- Serial form
- Serial/parallel form
- Parallel form

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 101
 Application – Specific Integrated Circuits [ASIC]

Array Multiplication (Braun Array Multiplier)

• A parallel multiplier is based on the observation that partial products in the multi-plication process
may be independently computed in parallel. For example, consider the unsigned binary integers X
and Y.

• Thus Pk are the partial product terms called summands. There are mn summands, which are
produced in parallel by a set of mn AND gates.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 102
 Application – Specific Integrated Circuits [ASIC]
• For 4-bit numbers, the expression above may be expanded as in the table below,

Figure: An n x n multiplier requires

(n 1)2full adders, n 1 half adders, and n2 AND gates
• The worst-case delay associated with such a multiplier is (2n + l)tg, where tg is the worst-case
adder delay.
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 103
 Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 104
 Application – Specific Integrated Circuits [ASIC]

• Cell shown in Figure is a cell that may be used to construct a parallel multiplier.

• The Xi term is propagated diagonally from top

right to bottom left, while the yj term is
propagated horizontally.
• Incoming partial products enter at the top.
Incoming CARRY IN values enter at the top right
of the cell.
• The bit-wise AND is performed in the cell, and
the SUM is passed to the next cell below.
• The CARRY 0UT is passed to the bottom left of
the cell.

Figure: Basic cell to construct a parallel multiplier

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 105
 Application – Specific Integrated Circuits [ASIC]

• Figure on next slide depicts the multiplier array with the partial products enumerated.
• The Multiplier can be drawn as a square array, as shown here, Figure is the most convenient for
implementation.
• In this version the degeneration of the first two rows of the multiplier are shown.
• The first row of the multiplier adders has been replaced with AND gates while the second row
employs half-adders rather than full adders.
• This optimization might not be done if a completely regular multiplier were required (i.e. one array
cell).
• In this case the appropriate inputs to the first and second row would be connected to ground, as
shown in the previous slide.
• An adder with equal carry and sum propagation times is advantageous, because the worst-case
multiply time depends on both paths

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 106
 Application – Specific Integrated Circuits [ASIC]

Figure: Array multiplier

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 107
 Application – Specific Integrated Circuits [ASIC]

Wallace Tree Multiplication

• If the truth table for an adder, is examined, it may be seen that an adder is in effect a one's counter"
that counts the number of l's on the A, B, and C inputs and encodes them on the SUM and CARRY
outputs.
• A l-bit adder provides a 3:2 (3 inputs, 2 outputs) compression in the number of bits. The
addition of partial products in a column of an array multiplier may be thought of as totaling up the
number of l's in that column, with any carry being passed to the next column to the left.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 108
 Application – Specific Integrated Circuits [ASIC]

Figure: Most convenient way for

implementation of array multiplier

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 109
 Application – Specific Integrated Circuits [ASIC]

• Example for implementation of 4x4 multiplier (4-bit) using Wallace Tree Multi-plication
methods

Figure: Table to nd product terms

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 110
 Application – Specific Integrated Circuits [ASIC]

• Considering the product P3, it may be seen that it requires the summation of four partial products
and a possible column carry from the summation of P2.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 111
 Application – Specific Integrated Circuits [ASIC]

Dadda Multiplier Self Study

• NOTES

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 112
 Application – Specific Integrated Circuits [ASIC]

Arithmetic Operator

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 113
 Application – Specific Integrated Circuits [ASIC]

Datapath Operators
Figure 2.32 shows symbols for some other datapath elements. The combinational datapath
cells, NAND, NOR, and so on, and sequential datapath cells (flip-flops and latches) have standard-
cell equivalents and function identically. I use a bold outline (1 point) for datapath cells instead of
the regular (0.5 point) line I use for scalar symbols. We call a set of identical cells a vector of
datapath elements in the same way that a bold symbol, A , represents a vector and A represents a
scalar.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 114
 Application – Specific Integrated Circuits [ASIC]

A subtracter is similar to an adder, except in a full subtracter we have a borrow-in signal,

BIN; a borrow-out signal, BOUT; and a difference signal, DIFF:

DIFF = A • NOT(B) • NOT(BIN) = SUM(A, NOT(B), NOT(BIN))

NOT(BOUT) = A · NOT(B) + A · NOT(BIN) + NOT(B) · NOT(BIN)
= MAJ(NOT(A), B, NOT(BIN))

Keywords: adder/subtracter • barrel shifter • normalizer • denormalizer • leading-one detector •

priority encoder • exponent correcter • accumulator • multiplier–accumulator (MAC) • incrementer
• decrementer • incrementer/decrementer • all-zeros detector • all-ones detector • register file •
first-in first-out register (FIFO) • last-in first-out register (LIFO)

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 115
 Application – Specific Integrated Circuits [ASIC]

I/O cells
Figure 2.33 shows a three-state bidirectional output buffer (Tri-State ® is a registered trademark of
National Semiconductor). When the output enable (OE) signal is high, the circuit functions as a
noninverting buffer driving the value of DATAin onto the I/O pad. When OE is low, the output transistors
or drivers, M1 and M2, are disconnected. This allows multiple drivers to be connected on a bus. It is up
to the designer to make sure that a bus never has two drivers-a problem known as contention.
In order to prevent the problem opposite to contention a bus floating to an intermediate voltage
when there are no bus drivers-we can use a bus keeper or bus-hold cell (TI calls this Bus-Friendly logic).
A bus keeper normally acts like two weak (low drive-strength) cross-coupled inverters that act as a latch
to retain
the last logic state on the bus, but the latch is weak enough that it may be driven easily to the opposite
state. Even though bus keepers act like latches, and will simulate like latches, they should not be used as
latches, since their drive strength is weak.
Transistors M1 and M2 in Figure 2.33 have to drive large off-chip loads. If we wish to change the
voltage on a C = 200 pF load by 5 V in 5 ns (a slew rate of 1 Vns^1) we will require a current in the
output transistors of
I DS = C (dV /d t ) = (200*10 ^-12 ) (5/5*10 ^-9 ) = 0.2 A or 200 mA.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 116
 Application – Specific Integrated Circuits [ASIC]
Such large currents flowing in the output transistors must also flow in the power supply bus and can
cause problems. There is always some inductance in series with the power supply, between the point at
which the supply enters the ASIC package and reaches the power bus on the chip. The inductance is due to
the bond
wire, lead frame, and package pin. If we have a power-supply inductance of 2 nH and a current changing
from zero to 1 A (32 I/O cells on a bus switching at 30 mA each) in 5 ns, we will have a voltage spike on
the power supply (called power-supply bounce ) of
L (dI /d t ) = (2*10^-9 )(1/(5*10^-9 )) = 0.4 V.
We do several things to alleviate this problem: We can limit the number of simultaneously
switching outputs (SSOs), we can limit the number of I/O drivers that can be attached to any one VDD and
GND pad, and we can design the output buffer to limit the slew rate of the output (we call these slew-rate
limited I/O pads). Quiet-I/O cells also use two separate power supplies and two sets of I/O drivers: an AC
supply (clean or quiet supply) with small AC drivers for the I/O circuits that start and stop the output
slewing at the beginning and end of an output transition, and a DC supply (noisy or dirty supply) for the
transistors that handle large currents as they slew the output.
The three-state buffer allows us to employ the same pad for input and output bidirectional I/O.
When we want to use the pad as an input, we set OE low and take the data from DATAin. Of course, it is
not necessary to have all these features on every pad: We can build output-only or input-only pads.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 117
 Application – Specific Integrated Circuits [ASIC]

FIGURE 2.32 A three-state bidirectional output

buffer. When the output enable, OE, is '1' the
output section is enabled and drives the I/O pad.
When OE is '0’ the output buffer is placed in a
high-impedance state.

Keywords: Tri-State® is a registered trademark of National Semiconductor) • drivers • contention • bus keeper or
bus-hold cell (TI calls this Bus-Friendly logic) • slew rate • power supply bounce • simultaneously switching
outputs (SSOs) • quiet-I/O • bidirectional I/O • open-drain • level shifter • electrostatic discharge, or ESD •
electrical overstress(EOS) • ESD implant• human-body model(HBM) • machine model(MM) • charge-device
model (CDM, also called device charge–discharge) • latch-up • undershoot • overshoot • guard rings

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 118
 Application – Specific Integrated Circuits [ASIC]

Cell Compilers
The process of hand crafting circuits and layout for a full-custom IC is a tedious, time-consuming, and error-prone
task. There are two types of automated layout assembly tools, often known as a silicon compilers. The first type produces a
specific kind of circuit, a RAM compiler or multiplier compiler , for example. The second type of compiler is more flexible,
usually providing a programming language that assembles or tiles layout from an input command file, but this is full-custom
IC design.
They can build a register file from latches or flip-flops, but, at 4.56.5 gates (1826 transistors) per bit, this is an
expensive way to build memory. Dynamic RAM (DRAM) can use a cell with only one transistor, storing charge on a
capacitor that has to be periodically refreshed as the charge leaks away. ASIC RAM is invariably static (SRAM), so we do
not need to refresh the bits. When we refer to RAM in an ASIC environment we almost always mean SRAM. Most ASIC
RAMs use a six-transistor cell (four transistors to form two cross-coupled inverters that form the storage loop, and two more
transistors to allow us to read from and write to the cell). RAM compilers are available that produce single-port RAM (a
single shared bus for read and write) as well as dual-port RAMs , and multiport RAMs . In a multi-port RAM the compiler
may or may not handle the problem of address contention (attempts to read and write to the same RAM address
simultaneously). RAM can be asynchronous (the read and write cycles are triggered by control and/or address transitions
asynchronous to a clock) or synchronous (using the system clock).
In addition to producing layout we also need a model compiler so that we can verify the circuit at the behavioral
level, and we need a netlist from a netlist compiler so that we can simulate the circuit and verify that it works correctly at the
structural level. Silicon compilers are thus complex pieces of software. We assume that a silicon compiler will produce
working silicon even if every configuration has not been tested. This is still ASIC design, but now we are relying on the fact
that the tool works correctly and therefore the compiled blocks are correct by construction .
Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 119
 Application – Specific Integrated Circuits [ASIC]

Questions
1. Explain the ASIC Design flow with a neat flow chart.
2. Differentiate channel and channel less gate array based ASIC design.
3. Illustrate internal structure of Configurable Logic Block (CLB) with an example.
4. Discuss field programmable gate array with a neat diagram.
5. Illustrate Programmable Logic Array and Programmable Array Logic design with an example.
6. Illustrate the information of ASIC cell Library with an example.
7. What is CBICs? State the important features of CBICs.
8. Differentiate between Full custom, Semi-Custom, FPGA and Gate Array based ASIC
Design Styles.
9. Discuss the Economics of the ASIC Design.
10. Discuss the fixed and Variable cost of ASIC Design.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 120
 Application – Specific Integrated Circuits [ASIC]

Questions
1. Calculate the logical effort for 2 input NAND and NOR gate, and show logical effort for inverter is equal
to 1.
2. Assume 4-bit multiplicand 𝑎3𝑎2𝑎1𝑎0 and 4-bit multiplier 𝑏3𝑏2𝑏1𝑏0 produce partial products and sum
of partial product and represent same using half adder and full adder.
3. Discuss any two techniques used to reduce the number of adders and delay in multiplier.
4. Explain the reduction of partial products in array multiplier using canonical signed digit (CSD).
5. Discuss how to predict the delay in single stage and multistage cells.
6. Discuss how the delay is reduced using Carry save adder (CSA) and Ripple carry adder (RCA) with neat
Datapath layout.
7. Explain 4-bit Ripple Carry Binary Adder and Carry-Lookahead Logic with proper example.
8. Describe the flow of 4x4 multiplier (4-bit) using Wallace Tree Multi-plication method.

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 121
 Application – Specific Integrated Circuits [ASIC]

Mr. Hemanth T S [Link], Assistant Professor, Dept. of E&CE, AIET, Moodbidri. 122