📦 Microprocessor‑Based System Overview

Microprocessor – programmable logic device that reads binary instructions from memory, processes data in its ALU, and
communicates via a system bus.
Memory – stores program (ROM/EPROM) and temporary data (R/W RAM).
I/O – input devices (keyboard, A/D converters) and output devices (LEDs, LCD, fan, heater).
Bus Architecture – three parallel buses:
Bus Width Direction Primary Function
Address Bus 16 bits (A15‑A0) Unidirectional (CPU → Select memory location or I/O
peripherals) port
Data Bus 8 bits (D7‑D0) Bidirectional Transfer instructions, data, or
control information
Control Bus Multiple single‑line signals Unidirectional Timing and operation control
(RD, WR, IO/M, ALE, etc.)

Definition: System bus – a group of wires that carry address, data, and control signals between the CPU, memory, and I/O devices.

🧩 8085 Programming Model

The 8085 architecture is split into hardware (physical registers, ALU) and a programming model used by the assembler.
Element Description
Accumulator (A) 8‑bit register used by most arithmetic/logic operations.
General‑purpose registers B, C, D, E, H, L – can be paired (BC, DE, HL) for 16‑bit operations.
Flag Register Five status bits: S, Z, AC, P, CY (see table below).
Program Counter (PC) 16‑bit register pointing to the next instruction address.
Stack Pointer (SP) 16‑bit register pointing to the top of the stack in RAM.

Flag Register
Flag Symbol Condition (set = 1)
Sign S MSB (D7) of the result is 1 (negative for
signed numbers).
Zero Z Result is 0.
Auxiliary Carry AC Carry from bit 3 to bit 4 (used for BCD
arithmetic).
Parity P Result contains an even number of 1’s.
Carry CY Carry out of the most‑significant bit (or
borrow for subtraction).

📚 8085 Instruction Set Overview

The 8085 provides 74 opcodes (246 instructions) grouped into five functional categories.
Category Typical Operations Example Mnemonics
Data Transfer (Copy) Load, store, move between MVI A,32H, MOV C,A, LDA 2050H, OUT
registers/memory/I/O 01H
 Arithmetic Add, subtract, increment, decrement, ADD B, ADI 37H, INR D, DCR M
16‑bit add/sub
Logical / Bit Manipulation AND, OR, XOR, complement, rotate, ANA B, ORI 3FH, CMA, CMP C
compare
Branching Conditional/unconditional jumps, calls, JMP 2050H, JZ LABEL, CALL SUBR, RET
returns
Machine Control Halt, NOP, interrupt control HLT, NOP

Instruction Word Sizes

Size Description Byte Count
1‑byte Opcode only (or implicit operand) 1
2‑byte Opcode + 8‑bit immediate operand or 2
address low byte
3‑byte Opcode + 16‑bit address (low byte first) 3
Mnemonic → Opcode → Operand mapping is fixed; the assembler translates mnemonics to the appropriate hex codes.

✍️ Writing & Assembling an 8085 Program

1. Break the problem into logical steps (load, compute, store/display).
2. Translate each step into a mnemonic using the instruction set.
3. Lookup the hex opcode (or use an assembler) to obtain the machine code.
4. Enter the hex bytes into RAM at the desired start address.
5. Set the PC to the start address and execute (or single‑step).
Example: Add Two Hex Numbers
Problem: Load 32H into A, 48H into B, add, display result on port 01H.

;--- Add Two Hex Numbers --------------------------------

MVI A,32H ; Load 0x32 into accumulator
MVI B,48H ; Load 0x48 into accumulator B
ADD B ; A ← A + B, result in A, flags updated
OUT 01H ; Send accumulator content to port 01H
HLT ; Stop execution
;-------------------------------------------------------

Corresponding Hex Codes

Address Hex Comment
2000H 3E 32 MVI A,32H
2002H 06 48 MVI B,48H
2004H 80 ADD B
2005H D3 01 OUT 01H
2007H 76 HLT

🧮 Example: Subtract Two Bytes in Memory

Task:
Subtract byte at 2051H (49H) from byte at 2052H (9FH).
 Store result at 2053H.
Program starts at 2030H.

;--- Subtract Memory Bytes -------------------------------

LDA 2051H ; A ← [2051H] (49H)
MOV B,A ; B ← A (save first operand)
LDA 2052H ; A ← [2052H] (9FH)
SUB B ; A ← A – B → 9FH – 49H = 56H
STA 2053H ; [2053H] ← A
HLT ; End of program
;-------------------------------------------------------

Hex Listing (starting 2030H)

Addr Hex Mnemonic
2030 3A 51 20 LDA 2051H
2033 47 MOV B,A
2034 3A 52 20 LDA 2052H
2037 90 SUB B
2038 32 53 20 STA 2053H
203B 76 HLT

🔌 Input / Output Methods

Method Address Size Instructions Used Typical Use
Peripheral‑mapped I/O 8‑bit port address (00‑FFH) IN, OUT Simple devices, separate I/O
space
Memory‑mapped I/O Full 16‑bit address Same as memory instructions Devices share address space
(LDA, STA) with RAM/ROM

Note: In peripheral‑mapped I/O the IO/M status line is high; in memory‑mapped I/O it is low. The control signals IOR and IOW are
generated by ANDing IO/M with RD/WR.

🧩 Interfacing Devices
Device Function Typical Part Numbers
Tri‑state Buffer Three states: 0, 1, high‑impedance; 74LS244, 74LS240
isolates bus when not selected.
Octal Buffer Increases drive capability for address or 74LS244
data lines.
Bidirectional Buffer (Bus Transceiver) Allows data flow in both directions; DIR 74LS245
pin selects direction.
Decoder (1‑out‑of‑N) Converts binary address to a single active 74LS138 (3‑to‑8), 74LS154 (4‑to‑16)
low line (chip select, port select).
Encoder Reverse of decoder; generates binary 74LS148 (priority encoder)
code from active input lines.
 Latch (D‑type flip‑flop) Stores a byte; often used to latch 74LS373
low‑order address (A0‑A7) from the
multiplexed AD bus.
Register (Octal Latch) Holds 8‑bit data for output devices (e.g., 74LS373
LEDs).
Tri‑state Logic Illustration

The image shows a basic tri‑state inverter; when Enable is high the inverter works normally, when low the output is high‑impedance,
allowing other devices to drive the bus.

🕒 Timing & Machine Cycles

Basic Cycle Types
Cycle Status Signals (IO/M, S1, S0) Control Signals Typical T‑states
Opcode Fetch (M1) IO/M = 0, S1 = 1, S0 = 1 MEMR (RD) 4–6
Memory Read (M2) IO/M = 0, S1 = 1, S0 = 0 MEMR (RD) 3
Memory Write (M3) IO/M = 0, S1 = 0, S0 = 1 MEMW (WR) 3
I/O Read IO/M = 1, S1 = 1, S0 = 0 IOR (RD) 3
I/O Write IO/M = 1, S1 = 0, S0 = 1 IOW (WR) 3
Interrupt Acknowledge IO/M = 1, S1 = 0, S0 = 0 IOR (RD) 4

Opcode Fetch Example (Clock = 2 MHz)

T‑state duration = 1 / 2 MHz = 0.5 µs
Total time for a 4‑T‑state fetch = 4 × 0.5 µs = 2 µs.
Memory Read Example (MVI instruction)
T‑state Signal Activity
T1 PC placed on address bus (high‑order A15‑A8); low‑order
AD0‑AD7 hold low address; ALE goes high.
T2 RD asserted (low); memory enabled.
 T3 Data byte appears on D0‑D7; RD de‑asserted.
T4 Instruction decoded (if needed).
Total time = 3 × 0.5 µs = 1.5 µs.

📐 Generating Control Signals

The 8085 provides RD, WR, and IO/M. By combining them with simple logic gates you obtain the four active‑low signals used by
external circuits:
MEMR = RD AND ¬IO/M
MEMW = WR AND ¬IO/M
IOR = RD AND IO/M
IOW = WR AND IO/M
Typical implementation uses two 2‑input NAND gates (or the 74LS32 OR gates wired as NANDs) plus an inverter for IO/M.

The diagram shows how RD, WR, and IO/M are combined to produce MEMR, MEMW, IOR, and IOW.

📊 Memory Organization & Addressing

Address Line Calculation
For a memory chip with N registers:
[ \text{Address lines } = \log_2 N ]
Memory Size Registers Required Address Lines
256 × 8 bits (256 B) 256 8
1 K × 8 bits (1 KB) 1024 10
8 K × 8 bits (8 KB) 8192 13
64 K × 8 bits (64 KB) 65536 16

Memory Map Example (256‑byte chip)

High‑order lines (A15‑A8) → Chip Select (CS) logic (often through a NAND gate).
Low‑order lines (A7‑A0) → internal decoder to select one of the 256 registers.
If CS is asserted only when A15‑A8 = 0000 0000, the chip occupies addresses 0000H–00FFH.
Changing the CS logic (e.g., forcing A15 = 1) moves the range to 8000H–80FFH.

The figure shows how high‑order address lines select the chip (CS) while low‑order lines address individual registers, giving a range of
0000H–03FFH for a 1 K‑byte chip.
Memory Types
Type Volatility Typical Use Example Devices
SRAM (Static RAM) Volatile Cache, high‑speed RAM 6264, 6116
DRAM (Dynamic RAM) Volatile Main system memory 4164, 41256
Masked ROM Non‑volatile Mass‑produced firmware –
PROM One‑time programmable Prototyping –
EPROM Erasable with UV Development, boot ROM 2716, 2732
EEPROM / Flash Electrically erasable BIOS, firmware updates 28C256, AT29C256

🖥️ Example: Complete 8085‑Based Microcomputer Block Diagram

The schematic shows the 8085 MPU, address & data buses, demultiplexing latch, control‑signal generators, RAM, ROM, and I/O ports.
Tri‑state buffers and decoders isolate each peripheral.
Key Points in the Diagram
1. AD latch (74LS373) – captures low‑order address (A0‑A7) on the ALE pulse.
2. Octal buffer (74LS244) – drives the high‑order address lines with sufficient current.
3. Decoder – turns the high‑order address into a chip‑select for RAM, ROM, or I/O.
4. Bidirectional buffer (74LS245) – drives the data bus during reads/writes.

📋 Quick Reference Tables

Instruction Byte Length
 Length Example Mnemonics
1 byte NOP, CMA, RRC, JC label (opcode only)
2 byte MVI A,32H, ADI 7FH, LXI H,2000H (opcode + 8‑bit operand)
3 byte LDA 2050H, JMP 2085H, CALL 2075H (opcode + 16‑bit address)

Common Flag Effects (selected instructions)

Instruction Affected Flags
ADD r Z, S, P, CY, AC
SUB r Z, S, P, CY, AC
INR r Z, S, P, AC (CY unchanged)
DCR r Z, S, P, AC (CY unchanged)
CMA No flags changed

Memory Chip Address‑Line Summary

Chip Size (bytes) Required Address Lines Typical High‑Order Lines for CS
256 (0.25 KB) 8 A15‑A8 = 0000 0000
1 KB 10 A15‑A6 = 0000 00xx
4 KB 12 A15‑A4 = 0000 xxxx
8 KB 13 A15‑A3 = 0000 0xxx
64 KB 16 Entire address space (no extra CS
needed)

🛠️ Frequently Used Assembly Constructs

;--- Loop to Increment Register B 10 Times -------------
MVI B,00H ; B = 0
MVI C,0AH ; Counter = 10
LOOP: INR B
DCR C
JNZ LOOP
HLT
;-------------------------------------------------------

MVI – Move Immediate (2‑byte).

INR / DCR – Increment/Decrement (1‑byte, affect flags).
JNZ – Jump if Zero flag is clear (conditional branch).

📖 Summary of Core Concepts

1. 8085 architecture – 8‑bit data path, 16‑bit address bus (high‑order A15‑A8 + multiplexed AD0‑AD7).
2. Programming model – Accumulator, six general registers, flag register, PC, SP.
3. Instruction set – Five functional groups, variable byte length, fixed opcode/operand layout.
4. Bus timing – Machine cycles (M1, M2, M3) broken into T‑states; ALE latches low address, RD/WR control data flow.
5. Memory interfacing – Chip select via high‑order address decoding, low‑order address latch, MEMR/MEMW signals.
6. I/O interfacing – Peripheral‑mapped (8‑bit ports) vs memory‑mapped (16‑bit addresses).
7. Tri‑state logic – Essential for shared bus systems; buffers, decoders, and latches isolate devices.
8. Flag usage – Decision‑making in branches (JZ, JC, JNC, etc.) based on result of ALU operations.
These notes capture the essential hardware and software concepts needed to understand, program, and interface the Intel 8085
📡
microprocessor in both educational labs and simple embedded applications.## Memory Interfacing Basics
8085 places a 16‑bit address on the address bus (A15‑A0).
Only one register (or memory location) must be selected for a given address.
Step Action Key Signals
1 Connect the low‑order address lines (e.g., –
A10‑A0) to the memory chip.
2 Decode the remaining high‑order lines to –
generate a Chip Select (CS) pulse.
3 Combine RD/WR with IO/M to form MEMR = RD ∧ IO/M, MEMW =
MEMR (read) or MEMW (write). WR ∧ IO/M
4 During T2 of the read cycle, the memory –
places the data byte on the data bus; the
microprocessor samples it before T3.
5 During T2 of the write cycle, the –
microprocessor puts the data byte on the
bus, asserts WR, and the memory stores
the byte.

Definition – Memory Read Cycle: The 8085 asserts MEMR; the addressed memory drives its output buffer and places the selected
byte on the data bus for the CPU to latch.

Definition – Memory Write Cycle: The 8085 asserts MEMW; the addressed memory enables its input buffer and latches the data
byte presented on the bus.

🧩 Address Decoding Techniques

1. Absolute Decoding
All high‑order address lines that are not needed by the memory are decoded, producing a unique CS for one address range.
Example – 4 K EPROM (2732)
Required lines: A0‑A11 (12 lines) → 4 K locations.
Decoded lines: A15‑A12 → 4‑bit decoder (74LS138).

A15 A14 A13 A12 = 0000 → CS active (EPROM selected)

Address range = 0000H … 0FFFH

2. Partial (Linear‑Select) Decoding

Some high‑order lines are left don’t‑care, giving multiple address windows (foldback/mirror memory). Reduces hardware but creates
foldback ranges.
Example – 2 K RAM (6116)
Connected lines: A0‑A10 (11 lines) → 2 K locations.
Decoded lines: A15‑A14 plus a decoder enable → output O1 (MSEL).
Address range: 8800H … 8FFFH (primary)
Foldback ranges: 8800H‑887FH, 8880H‑88FFH, … , 8F00H‑8FFFH (same physical RAM).

3. Decoder‑Based Schemes
 Decoder Inputs Outputs Typical Use
NAND gate A15‑A12 (all high) CS active low Simple 4‑line absolute decode
3‑to‑8 (74LS138) A15‑A12 + enable lines O0‑O7 active low Up to 8 chips, absolute or
partial decode

Note – The enable pins of 74LS138 (E1, E2 = active low, E3 = active high) must be wired appropriately (e.g., A15 to E3, A14‑A12 to
inputs, others grounded).

📚 8155/8156 Memory Section

The 8155 provides 256 × 8 RAM, two programmable I/O ports, and a timer.
Its internal latch demultiplexes AD7‑AD0; no external ALE latch is needed.

The diagram shows the internal RAM array, latch, and the 5 control/status lines (IO/M, ALE, RD, WR, RESET) that replace external
demultiplexing.
Key signals generated internally
MEMR = IO/M ∧ RD
MEMW = IO/M ∧ WR
Address range (default configuration) → 2000H … 20FFH (primary).
Because A10‑A0 are free, the don’t‑care lines A10‑A2 can assume any combination, producing foldback ranges 2100H‑27FFH that
map to the same 256 bytes.

🔌 Interfacing I/O Devices

Technique Address Space Control Signals Typical Use
Peripheral‑Mapped I/O 8‑bit Port # (00‑FFH) IOR, IOW (generated from Simple peripherals, limited to
IO/M ∧ RD/WR) 256 ports
Memory‑Mapped I/O 16‑bit address (any location in MEMR, MEMW Larger address space, shared
0000‑FFFFH) with RAM/ROM

1. Output Port (Peripheral‑Mapped)

Block diagram

A7‑A0 → Decoder (e.g., 8‑input NAND) → IOW (WR ∧ IO/M) → Device‑Select Pulse → Latch (74LS373) → LEDs
The decoder generates a low pulse only when the address matches the port number (e.g., 01H). The IOW pulse enables the latch,
capturing the accumulator data.

2. Input Port (Peripheral‑Mapped)

Tri‑state buffer (e.g., 74LS244) is enabled by IOR (RD ∧ IO/M).
Switches are tied high (logic 1) when open; closing a switch pulls the line low (logic 0).

3. Example: 7‑Segment LED (Common‑Anode)

Address: F5H
Data byte for digit “7”: $78H (segments A, B, C on → logic 0).

The circuit uses a 74LS138 decoder, a 74LS20 NAND for address enable, and a 74LS02 NOR to combine the decoder output with the
IOW pulse, driving a 74LS373 latch that drives the LED segments.
Key points
Decoder input: A2, A1, A0 = F5H (1111 0101).
Active‑low output O5 combined with IOW → latch enable.
Latch output drives the segment lines (logic 0 lights a segment on a common‑anode display).

🖥 8085 Instruction Set Overview

1. Data‑Transfer (Copy)
Mnemonic Operands Description Flags
MOV Rd,Rs Register → Register 1‑byte copy —
MVI R,byte Immediate → Register 2‑byte load —
IN port → Accumulator 2‑byte input —
OUT port Accumulator → 2‑byte output —
LDA addr → Accumulator 3‑byte direct memory load —
STA addr Accumulator → 3‑byte direct memory store —
LDAX B/D → Accumulator (indirect) 1‑byte —
STAX B/D Accumulator → (indirect) 1‑byte —
MOV A,M → Accumulator (HL points) 1‑byte —
 MOV M,R Accumulator ← Register (HL 1‑byte —
points)

2. Arithmetic
Mnemonic Operands Description Affected Flags
ADD R Accumulator + Register 1‑byte S, Z, CY, AC, P
ADI byte Accumulator + Immediate 2‑byte S, Z, CY, AC, P
SUB R Accumulator – Register 1‑byte S, Z, CY, AC, P
SUI byte Accumulator – Immediate 2‑byte S, Z, CY, AC, P
INR R Register + 1 1‑byte S, Z, AC, P (CY unchanged)
DCR R Register – 1 1‑byte S, Z, AC, P (CY unchanged)

Note – Carry (CY) serves as carry for addition and borrow for subtraction.

3. Logic
Mnemonic Operands Description Flags
ANA R Accumulator ∧ Register 1‑byte S, Z, P (CY = 0)
ANI byte Accumulator ∧ Immediate 2‑byte S, Z, P (CY = 0)
ORA R Accumulator ∨ Register 1‑byte S, Z, P (CY = 0)
ORI byte Accumulator ∨ Immediate 2‑byte S, Z, P (CY = 0)
XRA R Accumulator ⊕ Register 1‑byte S, Z, P (CY = 0)
XRI byte Accumulator ⊕ Immediate 2‑byte S, Z, P (CY = 0)
CMA Accumulator ← ~Accumulator 1‑byte No flags affected

4. Rotate
Mnemonic Effect CY Updated
RLC 8‑bit left rotate; D7 → Do CY ← D7
RAL 9‑bit left rotate; D7 → CY, CY → Do CY ← D7
RRC 8‑bit right rotate; Do → D7 CY ← Do
RAR 9‑bit right rotate; Do → CY, CY → D7 CY ← Do

5. Branch (Jump)
Mnemonic Condition Target (16‑bit)
JMP addr Unconditional —
JC addr CY = 1 —
JNC addr CY = 0 —
JZ addr Z=1 —
JNZ addr Z=0 —
JP addr S = 0 (positive) —
JM addr S = 1 (negative) —
 JPE addr P = 1 (even parity) —
JPO addr P = 0 (odd parity) —

6. Machine Control
Mnemonic Effect
HLT Processor halts; all buses high‑Z
NOP No operation (useful for timing)

🔄 Programming Techniques – Loops, Counters, Indexing

1. Continuous Loop

START: ; <– label

; … (task)
JMP START ; unconditional jump back

2. Conditional Loop with Counter

MVI B,05H ; B = loop count (5)

LOOP: ; <– label
; … (task)
DCR B ; B = B‑1
JNZ LOOP ; repeat while B ≠ 0

Explanation – The Zero flag is set when a register becomes zero; JNZ (Jump if Not Zero) continues the loop until the counter
expires.

3. Indexed Memory Access

LXI H,DATA_START ; HL points to first byte

MVI C,0AH ; C = number of bytes (10)
NEXT: MOV A,M ; A ← [HL]
; … process A …
INX H ; HL ← HL + 1 (next address)
DCR C
JNZ NEXT

The HL pair acts as a memory pointer (index). INX H increments it automatically.

📂 Example Programs
A. Read Switches (Port 00H) and Mirror to Output (Port 01H)

; -------------------------------------------------
; Read 8‑switch input at 00H and display same pattern at 01H
; -------------------------------------------------
IN 00H ; A ← switches
OUT 01H ; display on LEDs
HLT
B. Add Two Registers, Test Carry, Display Result

; -------------------------------------------------
; D = 9BH, E = A7H → add, show overflow flag
; -------------------------------------------------
MVI D,9BH
MVI E,A7H
MOV A,D
ADD E ; A = D+E, CY set if overflow
JNC NO_CARRY
MVI A,01H ; overflow → display 01H
NO_CARRY:
OUT 00H
HLT

C. Block Transfer (50H‑5FH → 70H‑7FH) – 16 Bytes

; -------------------------------------------------
; Copy block of 16 bytes from 50H..5FH to 70H..7FH
; -------------------------------------------------
LXI H,5050H ; HL → source (50H)
LXI D,7070H ; DE → destination (70H)
MVI B,10H ; B = 16 bytes
COPY: MOV A,M ; A ← [HL]
MOV M,A ; [DE] ← A
INX H
INX D
DCR B
JNZ COPY
HLT

D. Seven‑Segment Display – Show Digit “7” (Port F5H)

; -------------------------------------------------
; Load pattern for ‘7’ (segments A,B,C on) → port F5H
; -------------------------------------------------
MVI A,78H ; 0111 1000 → common‑anode
OUT F5H
HLT

E. Sorting Three Bytes (Bubble Sort)

; -------------------------------------------------
; Sort three bytes at 50H‑52H into ascending order
; -------------------------------------------------
LXI H,5050H ; HL → first byte
MVI D,00H ; D = flag (0 = no swap)
MVI C,02H ; C = compare count (N‑1)
PASS: MOV A,M ; A ← [HL]
INX H
CMP M ; compare with next byte
JC NO_SWAP
; swap required
MOV B,M
MOV M,A
DCX H
MOV M,B
INX H
MVI D,01H ; indicate a swap occurred
NO_SWAP:
 DCR C
JNZ PASS
MOV A,D
RRC ; move flag into CY
JC PASS ; repeat if any swap
HLT

📊 Flag‑Status Tables (Selected Operations)

Operation Result (A) S Z CY P
ADD A,B 4AH 0 0 1 0
(93H + B7H)
ADI 01H 00H 0 1 1 1
(FFH + 01H)
SUB B (A=97H, 32H 0 0 0 0
B=65H)
CMP M (A=78H, – – – 1 (A<M) –
M=80H)
ORA A (A=00H) 00H 0 1 0 1

📐 Memory‑Mapping Summary
Chip Size Address Lines Decoding Method Primary Range Foldback / Mirror
Used Ranges
2732 EPROM 4K ×8 A0‑A11 3‑to‑8 (74LS138) 0000H‑0FFFH –
on A15‑A12
6116 RAM 2K ×8 A0‑A10 NAND + A15‑A14 8800H‑8FFFH 8800‑887F, 8880‑88F
enable (partial)
8155 RAM 256 × 8 A0‑A7 Direct (CS tied to 2000H‑20FFH 2100‑27FF (mirror)
A0‑A7)
I/O Port (OUT) – 8‑bit port # 8‑input NAND + e.g., 01H 00H‑03H (if A4‑A3
IOW don’t‑care)

🛠 Debugging Techniques
Technique How to Use
Single‑Step Execute one instruction, inspect registers after each step.
Register‑Examine After a breakpoint or single‑step, view A, B, C, D, H, L, PC, Flags.
Breakpoint (RST) Insert RST xx at a location; the monitor halts there for inspection.
Diagnostic Loop Example: START: MVI A,55H / STA 2000H / JMP START –
provides a steady WR pulse to probe decoder outputs.

Common Pitfalls – Forgetting to clear the accumulator before an addition, not updating the HL pointer after MOV A,M, using the
wrong flag with a conditional jump, or mis‑wiring the decoder enable lines.

📑 Quick Reference – Frequently Used Mnemonics

 LXI rp,addr – Load 16‑bit immediate into register pair (rp = BC, DE, HL, SP).
INX rp / DCX rp – Increment/Decrement 16‑bit register pair (affects no flags).
LDAX B/D, STAX B/D – Indirect memory access via BC or DE (only accumulator).
CPI byte – Compare immediate with accumulator (sets flags, does not modify A).
JC/JNC/JZ/JNZ – Conditional jumps based on CY or Z.

📚 Summary
Memory interfacing relies on proper address decoding (absolute vs. partial) and generation of MEMR/MEMW from
RD/WR combined with IO/M.
The 8155 integrates RAM, I/O ports, and a timer with internal demultiplexing, simplifying external wiring.
Peripheral‑mapped I/O uses 8‑bit port numbers; memory‑mapped I/O shares the full 16‑bit address space and uses the
same control signals as RAM/ROM.
The 8085 instruction set provides a compact set of operations for data movement, arithmetic, logic, rotation, and
flow‑control; mastering flag effects is essential for branching and conditional loops.
Programming techniques (loops, counters, indexing) are built around the HL pointer and register‑pair arithmetic (INX/DCX).
Effective debugging combines single‑step execution, register inspection, and breakpoints to isolate and fix logic errors.
---## 📊 Counters & Time Delays
Key Concepts
A counter is built by loading a count into a register and using INR (increment) or DCR (decrement) inside a loop.
A time‑delay loop loads a count into a register (or register pair) and decrements it until zero; the total delay depends on the
number of T‑states per instruction and the system clock period.

1️⃣ Simple 8‑bit Delay (Figure 8.2)

Step Instruction T‑states Comment
Load count MVI C,FFH 7 Load 255 (FFH) into C
Decrement DCR C 4 Decrease C
Test & loop JNZ LOOP 10/7 Jump back if C ≠ 0 (10 T when
jump taken, 7 T when
fall‑through)
Delay calculation (2 MHz clock, T = 0.5 µs)
[ TL = T \times (\text{Loop T‑states}) \times N = 0.5\mu s \times 14 \times 255 = 1785\mu s \approx 1.8\text{ ms} ]
Adjusted for the final non‑taken jump (‑3 T‑states):
[ T_{LA}=1785\mu s - 1.5\mu s = 1783.5\mu s ]
Add the outside‑loop MVI (7 T):
[ T_{\text{total}} = 7\times0.5\mu s + 1783.5\mu s = 1787\mu s \approx 1.8\text{ ms} ]

2️⃣ 16‑bit Delay Using a Register Pair

Instruction Operand T‑states Purpose
LXI B,2384H – 10 Load BC with 0x23 (high) and
0x84 (low)
DCX B – 6 Decrement BC (16‑bit)
MOV A,C – 4 Move low byte to A (sets flags)
ORA B – 4 OR high & low bytes → Zero
flag set only when BC = 0
JNZ LOOP – 10/7 Loop while BC ≠ 0
Delay (using 0.5 µs clock):
[ TL = 0.5\mu s \times 24 \times 0x2384 = 0.5\mu s \times 24 \times 9092 \approx 109\text{ ms} ]

3️⃣ Nested Loops (Figure 8.3)

Outer loop uses register B as a count (e.g., 0x38).
Inner loop uses C (e.g., 0xFF).

MVI B,38H ; outer count

LOOP2: MVI C,FFH ; inner count
LOOP1: DCR C
JNZ LOOP1 ; inner delay
DCR B
JNZ LOOP2 ; outer delay

Total delay (2 MHz clock):

[ TL_{inner}=1.7835\text{ ms} ] [ TL_{outer}=56,(TL_{inner}+0.0105\text{ ms})\approx 100.46\text{ ms} ]

📚 Stack & Subroutines

Definition – A stack is a set of memory locations used for temporary storage. The stack pointer (SP) always points to the topmost
occupied location.

1️⃣ Stack Operations

Mnemonic Effect Stack‑Pointer Change
PUSH Rp Store register pair (high byte first) SP ← SP‑2
POP Rp Retrieve register pair (low byte first) SP ← SP+2
SPHL Copy HL into SP (no flag change) –
PCHL Load PC from HL (jump) –
Example – Storing HL at address 2099H:

LXI SP,2099H ; SP = 2099H

LXI H,42F2H ; HL = 42F2H
PUSH H ; [2098]=42, [2097]=F2, SP=2097H

After a matching POP H, HL is restored and SP returns to 2099H.

2️⃣ Subroutine Template

CALL SUBRT ; main program
...
SUBRT: ; subroutine entry
PUSH B
PUSH D
... ; body
POP D
POP B
RET ; return to caller

CALL pushes the return address (PC of the next instruction).

RET pops that address back into PC.
3️⃣ Multiple‑Calling & Nesting
Multiple‑calling: the same subroutine is invoked from several points; each call pushes a new return address.
Nesting: a subroutine calls another subroutine; each call creates a new stack frame.

🔢 Code Conversion & 16‑bit Operations

1️⃣ BCD‑to‑Binary (Section 10.1)
Algorithm (2‑digit BCD)
1. Separate high and low nibbles:
ANI 0Fh → low BCD digit (C)
RRC (twice) → high BCD digit (B)
2. Multiply high digit by 10 (repeated addition or shift‑add).
3. Add low digit.

; Input: BCD in accumulator, output: binary in A

MOV B,A ; save BCD
ANI 0Fh ; low digit → A
MOV C,A ; C = low
MOV A,B
ANI F0h
RRC ; bring high nibble down
RRC
MOV B,A ; B = high
MVI D,0Ah ; D = 10
LXI H,0 ; accumulator = 0
HLT ; placeholder

(Full subroutine shown in the transcript.)

2️⃣ Binary‑to‑BCD (Section 10.2)

Repeated subtraction of 100, then 10, then remaining units.
Uses DAA after each addition to adjust BCD digits.

3️⃣ BCD ↔ Seven‑Segment Code (Section 10.3)

BCD Common‑Cathode Code (Hex)
0 3F
1 06
2 5B
3 4F
4 66
5 6D
6 7D
7 07
8 7F
9 6F
Lookup subroutine (LEDCOD) loads the base address of the table, adds the BCD digit, and fetches the segment pattern.

4️⃣ Binary‑to‑ASCII Hex (Section 10.4)

 ; Convert low nibble of A to ASCII
ANI 0Fh
CPI 0Ah
JC DIGIT0_9
ADI 07h ; A–F => add 7
DIGIT0_9:
ADI 30h ; add '0'

5️⃣ 16‑bit Arithmetic

Instruction Effect
DAD B HL ← HL + BC (carry → CY)
DCX D DE ← DE – 1 (no flags)
INX H HL ← HL + 1
ADC M A ← A + (M) + CY
Example – Adding two 16‑bit numbers (BC + DE):

MOV A,C
ADD E
MOV C,A
MOV A,B
ADC D
MOV B,A ; result in BC

🔔 Interrupts (Chapter 12)

Interrupt – An asynchronous request from a peripheral that forces the CPU to suspend the current flow, execute an interrupt service
routine (ISR), then resume.

1️⃣ Types
Type Maskable? Vector Address Trigger
TRAP No 0024H Level & edge
RST 7.5 Yes (via SIM) 003CH Edge
RST 6.5 Yes (via SIM) 0034H Level
RST 5.5 Yes (via SIM) 002CH Level
INTR Yes (EI) External hardware supplies an Level
RST (0‑7) via INTA

2️⃣ Enabling / Disabling

EI – Set Interrupt Enable flip‑flop.
DI – Clear Interrupt Enable.
SIM – Load accumulator; bits D2‑D0 control masking of RST 7.5‑5.5 (0 = enabled). Bit D3 must be 1 for mask bits to be
effective.
RIM – Reads current mask status and pending interrupt flags into A.

3️⃣ Interrupt Sequence (8‑bit RST)

1. Detect INTR high while IE = 1.
2. Complete current instruction.
 3. Disable IE, assert INTA.
4. External hardware places RST n opcode on the data bus.
5. CPU pushes PC (next instruction address) onto the stack (2 bytes).
6. PC ← vector address (00n0H).
7. ISR executes; must end with EI (re‑enable) and RET.

4️⃣ Software Breakpoint (using RST 5)

BRKPNT: ; placed at desired break location
PUSH PSW
PUSH B
PUSH D
PUSH H
CHKKEY:
CALL KBRD ; get key in A
CPI 0Ah ; 'A' key?
JNZ NOT_A
; display A and flags
LXI H,0007H
DAD SP ; HL points to saved A
MOV A,M
OUT PORTI
DCX H
MOV A,M
OUT PORT2
JMP CHKKEY
NOT_A:
CPI 00h ; Zero key?
JNZ CHKKEY
POP H
POP D
POP B
POP PSW
RET

The routine saves all registers, polls the keyboard, displays A/flags on two ports, and restores state on the zero key.

5️⃣ Programmable Interrupt Controller (8259A)

Handles 8 IRQ lines, vectors to any address (not limited to page 00).
After an IRQ, the CPU receives a 3‑byte CALL (opcode CDh + low‑addr + high‑addr) generated by the 8259A on INTA.

6️⃣ Direct Memory Access (DMA – 8257)

Peripheral asserts HOLD → CPU finishes current cycle, releases address/data buses, asserts HLDA.
DMA controller takes control, moves data between memory and I/O without CPU intervention, then de‑asserts HOLD.

⚡ Digital‑to‑Analog (D/A) Converters (Chapter 13)

D/A Converter – A circuit that produces an analog voltage or current proportional to a binary digital word.

1️⃣ Basic Parameters

Parameter Meaning
Resolution Smallest step = Full‑Scale / (2ⁿ − 1) (e.g., 8‑bit, 0‑10 V → 39 mV
per LSB)
Full‑Scale Output (FSO) Maximum analog output, usually Full‑Scale − 1 LSB
Settling Time Time for output to stay within ±½ LSB of final value after code
change
 Monotonicity Output never decreases when code increases (typical spec
≤ ±½ LSB)

2️⃣ R‑2R Ladder Network

Uses only two resistor values (R and 2R) to create binary‑weighted currents.
Scales easily to 8‑, 10‑, 12‑bit DACs.

Figure 13.1 – (a) Block diagram of a 3‑bit DAC; (b) Linear relationship between digital input and analog output.
3️⃣ Interfacing an 8‑bit DAC (1408)
Hardware (Figure 13.5a)
Address decoder: 8‑input NAND + NAND‑AND with IOW.
Latch (74LS373) holds data bus during write.
DAC pins: A7…A0 (MSB → LSB), reference current source (Vref, 2 mA).
Analog output equation
[ I_o = I_{ref},\frac{D_7 2^7 + D_6 2^6 + \dots + D_0}{2^8} ]
For full‑scale (D7…D0 = 11111111):
[ I_o = 2\text{ mA}\times\frac{255}{256}=1.992\text{ mA} ]
With load resistor R_L = 5 kΩ:
[ V_o = I_o \times R_L = 1.992\text{ mA} \times 5\text{ kΩ}=9.961\text{ V} ]
Sample program – continuous ramp (output to port FFH)

ORG 2000H
LXI SP,2100H ; stack
MVI A,00H
OUT FFH ; first value
MVI B,FFH
RAMP: INR A
OUT FFH
DCR B
JNZ RAMP
HLT
END

4️⃣ Bipolar DAC (±5 V)

Use a reference of ±5 V and a signed binary code (two's complement).
Example input 1000 0000b (‑128) → V_out = -5 V.
📑 Summary Table of Important Instructions
Mnemonic Bytes T‑states Affected Flags Typical Use
MVI r,imm 2 7 – Load immediate
INR r 1 4 Z,S,P,AC Increment
DCR r 1 4 Z,S,P,AC Decrement
DAD rp 1 10 CY 16‑bit add
DCX rp 1 6 – 16‑bit decrement
INX rp 1 5 – 16‑bit increment
ADD r/m 1 4 Z,S,P,CY,AC 8‑bit add
ADC r/m 1 4 Z,S,P,CY,AC Add with carry
SUB r/m 1 4 Z,S,P,CY,AC 8‑bit subtract
SBB r/m 1 4 Z,S,P,CY,AC Subtract with borrow
CALL addr 3 17 – Subroutine call
RET 1 10 – Return
PUSH rp 1 11 – Save registers
POP rp 1 10 – Restore registers
EI 1 4 – Enable interrupts
DI 1 4 – Disable interrupts
RST n 1 11 – 1‑byte call (vector = n*8)
SIM 1 4 – Set interrupt mask
RIM 1 4 – Read interrupt
mask/status
DAA 1 4 Z,S,P,CY,AC Decimal adjust after
BCD add

📚 Quick Reference for Common Conversions

Decimal → BCD (packed) Binary → BCD (unpacked) ASCII Hex → Binary
0x45 → 45h (0100 0101) Use ANI 0Fh / RRC ×2 CPI 0Ah; if ≥ A add 7, then add 30h
BCD 72 → Binary 0x48 Multiply high digit by 10, add low See Section 10.4 code
Binary 9Fh → ASCII "9F" Convert each nibble separately ADI 30h (0‑9) or ADI 37h (A‑F)

🎯 How to Study This Material

1. Understand the timing model – T‑states × clock period = real‑world delay.
2. Practice writing loops – start with a simple 8‑bit delay, then extend to register‑pair loops.
3. Master stack discipline – always pair every PUSH with a matching POP in subroutines.
4. Implement the conversion subroutines – start with BCD‑to‑binary, then add the reverse and the ASCII helpers.
5. Simulate interrupts – use the RST‑based breakpoint example to see how the stack saves the return address.
6. Build a DAC interface on a breadboard or simulator; verify the calculated analog voltage against a multimeter.

End of Study Guide.## 📐 Interfacing the 1408 D/A Converter

Key concepts
 Unipolar range – output voltage varies from 0 V to a positive maximum.
Bipolar range – output voltage varies from –V_max to +V_max.
Circuit details (Fig. 13.5)
Component Value / Connection
R_B 5 kΩ (sets bipolar offset)
V_Ref Connected to reference source
R₁₄ 2.5 kΩ (current‑sense)
V_EE –15 V
V_CC +15 V
Bipolar output equation
[ I_{o}' = \frac{V_{Ref} - I_{o} \cdot R_{B}}{R_{B}} \qquad\text{(when }V_{Ref}=5\text{ V, }R_{B}=5\text{ kΩ)} ]
For zero input (all bits = 0):
[ V_{o}=0;\text{V} ]
For full‑scale input (1000 0000₂):
[ V_{o}=+5;\text{V} ]

🤖 Microprocessor‑Compatible D/A Converters

Device Features Typical Control Signals
AD558 On‑chip latch & output op‑amp; single CS, CE
supply 4.5–16.5 V
AD7522 10‑bit, double‑buffered, input latch, hold LBS, HBS, LDAC
register
Typical program (8085) to generate a ramp

; Load accumulator with first value

MVI A,00H ; A = 0
DTOA: OUT FFH ; Send to DAC
MVI B,COUNT ; B = delay count
DELAY: DCR B
JNZ DELAY
INR A ; Next value
JMP DTOA ; Loop forever

Delay loop guarantees the DAC’s settling time and lets the ramp slope be adjusted by changing COUNT.

📊 Interfacing the ADC0801 (8‑bit A/D Converter)

Pin summary
Pin Function
VIN(+), VIN(–) Differential analog inputs
V_REF/2 (pin 9) Sets full‑scale range
CLK IN External clock (100 kHz–800 kHz)
 CS, WR, RD Chip‑select, write, read
INTR Active‑low interrupt when conversion complete
Data bus (D0–D7) 8‑bit digital result
Timing (Fig. 13.13 b)
1. CS & WR go low → latch reset, output tri‑stated.
2. WR rises → conversion starts.
3. When conversion ends, INTR goes low.
4. RD reads data; INTR resets.
Example program (status‑check method)

; Initialize ports
MVI A,20H ; Control word: ports A & B as inputs, C as status
OUT 20H
; Start conversion
MVI A,08H ; Set PC4 = 1 (START pulse)
OUT 23H
; Wait for data ready
WAIT: IN 20H
ANI 02H ; Mask BFA (Port A Buffer Full)
JZ WAIT ; Loop until BFA = 1
; Read result
IN 21H ; Data from port A
; (Optional) stop timer, etc.
HLT

🛠️ 8155 Programmable I/O with Timer

Internal block (Fig. 14.6)
Block Purpose
Control Register (addr 20H) Sets I/O direction, timer mode, interrupts
Port A (21H), Port B (22H), Port C (23H) 8‑bit I/O (C can be split into upper/lower 4‑bits)
Timer LSB (24H), MSB (25H) 14‑bit down‑counter, four modes

Control‑word format (Fig. 14.8)

D7 D6–D5 D4 D3–D2 D1 D0
I/O / BSR Port A direction Port B direction Port C mode Timer command Timer mode
D7 = 1 → I/O mode; D7 = 0 → Bit‑Set/Reset (BSR) mode.
Example: 03H → Port A = output, Port B = output, Port C = ALT 1 (simple I/O).
Example: Seven‑Segment Display (Ports A & B as outputs)

MVI A,03H ; Control word: both ports = output

OUT 20H ; Write to control register
MVI A,55H ; Example pattern for segment display
OUT 21H ; Port A
MVI A,AAH
OUT 22H ; Port B
HLT

Timer‑generated 100 µs pulse (Mode 1, 3 MHz clock)

 1. Calculate count
[ f_{clk}=3\text{ MHz} \Rightarrow T_{clk}=333\text{ ns} ]
Desired half‑period = 50 µs → count = 150 000 ≈ 025EH.
2. Load registers

MVI A,5EH ; LSB

OUT 24H
MVI A,02H ; MSB (0x025E)
OUT 25H
MVI A,C3H ; Control word: start timer (bits D7‑D6 = 11)
OUT 20H
HLT

🖥️ 8255 Programmable Peripheral Interface (PPI)

Port layout
Port Size Typical use
A 8 bits General‑purpose I/O
B 8 bits General‑purpose I/O
C 8 bits (or two 4‑bit halves) Handshake or control signals
Control Register 8 bits Sets mode & direction

Control‑word format (Fig. 15.4)

D7 D6 D5 D4 D3 D2 D1 D0
Mode select Port A Port B Port C upper Port C lower Mode
(1 = I/O, 0 = direction direction (00 = Mode 0,
BSR) 01 = Mode 1,
1X = Mode 2)
Mode 0 – simple input/output, no handshaking.
Mode 1 – handshaking (STB, IBF, INTR, ACK).
Mode 2 – bidirectional I/O on Port A only.

Example: Keyboard → Seven‑Segment (Mode 0)

; Initialize: Port A = input, Port B = output

MVI A,90H ; 1001 0000b → A in, B out, C upper/lower = output
OUT FFH ; Control register (addr FFH)
; Main loop
LOOP: IN 80H ; Read keyboard (Port A)
CALL ENCODE ; Convert key code to 0‑F
OUT 81H ; Display on seven‑segment (Port B)
JMP LOOP

BSR example – set PC7 (bit 7 of Port C) high:

MVI A,0F8H ; D7=0 (BSR), bits 7‑5 = 111 → set PC7

OUT FFH
⏱️ 8254 Programmable Interval Timer
Three independent 16‑bit counters (0, 1, 2).
Mode Behavior
0 Interrupt on terminal count (OUT high after count)
1 One‑shot (OUT low during count, high after)
2 Rate generator (OUT high, pulse low for one clock at terminal
count)
3 Square‑wave generator (OUT toggles every half‑count)
4 Software‑triggered strobe
5 Hardware‑triggered strobe

Control word (Fig. 15.24)

Bits Meaning
D7‑D6 Counter select (00 = 0, 01 = 1, 10 = 2)
D5‑D4 Read/Write latch command
D3‑D1 Mode (M2 M1 M0)
D0 BCD/Binary (0 = binary)

Example: 1 kHz square wave on Counter 1 (2 MHz clock)

1. Count:
[ f = 2\text{ MHz},; f_{out}=1\text{ kHz} \Rightarrow N = \frac{f}{f_{out}} = 2000 = 0x07D0 ]
2. Program

MVI A,76H ; Control word: select Counter 1, mode 3

OUT 83H ; Control register (addr 83H)
MVI A,0DH ; LSB of 0x07D0
OUT 81H ; Counter 1 LSB
MVI A,07H ; MSB
OUT 81H ; Counter 1 MSB
HLT

🔀 8259 Programmable Interrupt Controller (PIC)

Register Purpose
IRR (Interrupt Request Register) Holds pending IRQs
ISR (In‑Service Register) Tracks currently serviced IRQs
IMR (Interrupt Mask Register) Masks individual IRQ lines
Priority Resolver Determines highest‑priority pending IRQ

Initialization Command Words (ICWs)

ICW Bits Meaning
 ICW1 1 1 0 0 0 1 0 0 (example) Single/multi 8259, vector interval (4 or 8),
edge/level
ICW2 High‑order 8 bits of interrupt vector (e.g.,
20H → vectors 0x20–0x27)
ICW3 (optional) Master/Slave wiring
ICW4 (optional) 8086/8085 mode, Auto EOI, etc.

Operational Command Words (OCWs)

OCW1 – mask bits (write to IMR).
OCW2 – End‑of‑Interrupt (EOI) commands.
OCW3 – Read IRR/ISR status.
Fully nested priority example

DI ; Disable interrupts while programming

MVI A,76H ; ICW1: single 8259, 4‑byte vectors, edge‑triggered
OUT 80H ; Port 80H = ICW1
MVI A,20H ; ICW2: vector base = 0x20
OUT 81H ; Port 81H = ICW2
EI ; Enable interrupts

📡 8237 DMA Controller

Channel Address Register (MAR) Count Register (CR)
0‑3 00H‑07H 08H‑0FH
Key signals
HRQ – DMA requests control of the bus.
HLDA – CPU acknowledges HRQ.
DREQₙ / DACKₙ – Peripheral request/acknowledge per channel.
AEN / ADSTB – Latch high‑order address byte.
MEMR / MEMW – Memory read/write during transfer.

Example: Transfer 1 KB from memory 0x4000 to floppy (Channel 3)

; 1. Disable DMA
MVI A,04H ; Command: disable, demand mode
OUT 08H

; 2. Set Channel 3 address (0x4000)

MVI A,00H
OUT 06H ; MAR low byte
MVI A,40H
OUT 06H ; MAR high byte

; 3. Set count = 0x03FF (1023 bytes)

MVI A,FFH
OUT 07H ; Count low
MVI A,03H
OUT 07H ; Count high

; 4. Mode register: demand, read, auto‑init, increment

MVI A,40H
OUT 0BH

; 5. Enable DMA, start transfer

 MVI A,80H
OUT 08H
HLT

📡 Serial I/O Fundamentals (Asynchronous)

Parameter Typical value
Baud 110 – 9600 bits/s (asynchronous)
Start bit 0 (active low)
Stop bits 1 or 2 (logic 1)
Parity None / Even / Odd
Data bits 7 or 8
Mark = logic 1 (idle line).
Space = logic 0 (active).
Transmission sequence (Fig. 16.2 b):
Start → D0 → D1 → … → D7 → Parity? → Stop(1/2)
Reception waits for a Start transition, then samples each bit in the middle of its period.

🖧 8251A USART (Asynchronous Mode)

Block diagram (Fig. 16.13)
Block Function
Control Register (16 bits) Mode word + command word
Status Register TXRDY, RxRDY, Overrun, Framing error
Data Buffer Bidirectional (Tx/Rx)
Transmitter Parallel‑to‑serial, adds Start/Stop/Parity
Receiver Serial‑to‑parallel, validates framing
Clock inputs TxC / RxC Divide system clock (1, 16, 64× baud)

Mode word (asynchronous)

Bit Setting Meaning
D7‑D6 00 1 stop bit
D5‑D4 01 7 data bits
D3 0 No parity
D2‑D0 000 9600 baud (depends on TxC)

Command word
Bit Setting Meaning
D7 1 Enable transmitter
D6 1 Enable receiver
D5 0 No interrupt on TXRDY
 D4 1 Interrupt on RxRDY
D3‑D0 0000 No special functions

Initialization sequence

; Reset USART (CS low, then high)

MVI A,00H
OUT 80H ; Control register (addr FFH)
; Write mode word
MVI A,0CH ; 0000 1100b → 7‑bit, 1‑stop, no parity, 9600 baud
OUT 80H
; Write command word (enable TX & RX)
MVI A,60H ; 0110 0000b → TXEN=1, RXEN=1
OUT 80H

Transmit a character (using the data buffer at FEH)

; Wait until transmitter ready

TXWAIT: IN 80H ; Read status
ANI 02H ; TXRDY flag
JZ TXWAIT
MVI A,'A' ; Character to send
OUT FEH ; Write to data buffer

Receive a character

; Wait for receiver ready

RXWAIT: IN 80H
ANI 01H ; RXRDY flag
JZ RXWAIT
IN FEH ; Read received byte into A

🖥️ 8085 Serial Lines (SID / SOD)

Instruction Purpose Effect on SID/SOD
SIM Serial OUT (SOD) Outputs Carry (CY) on SOD when D6=1
RIM Serial IN (SID) Places SID bit into D7 of accumulator
Transmit subroutine (SOD, 11 bits including start/stop)

SODATA:
MVI C,0BH ; 11‑bit count
XRA A ; Clear Carry (SOD idle = Mark)
NXTBIT:
MVI A,80H ; D7=1 → enable SOD
RAR ; Carry → D7, D6←D7
SIM ; Output D7 on SOD
CALL BITTIME ; Delay = 1/baud (e.g., 0.833 ms @1200 baud)
STC ; Set Carry = 1 (stop bits)
MOV A,B ; Load ASCII character
RAR ; Shift next bit into Carry
MOV B,A ; Save updated pattern
DCR C
 JNZ NXTBIT
RET

Receive subroutine (SID)

SIDATA:
RIM ; Read SID → D7
RAL ; Move D7 to Carry
JC SIDATA ; Not a start bit → retry
CALL HALFBIT ; Wait half‑bit time
MVI C,09H ; 9 bits (start + 8 data)
NXTBIT:
CALL BITTIME
RIM
RAL ; Store bit in Carry
DCR C
JNZ NXTBIT
RET

📚 Summary Tables
Control‑Word Examples
Device Address Control Word (hex) Mode / Function
8155 20H 03H Ports A & B = output (ALT 1)
8155 20H 0BH Set PC4 (INTEA) high (BSR)
8255 FFH 90H Port A = input, Port B = output
(Mode 0)
8255 FFH B4H Port A = input (handshake),
Port B = output (handshake)
8254 83H 76H Counter 1, Mode 2, binary
8254 83H 14H Counter 0, Mode 2 (rate
generator)
8251 FFH 0CH Mode: 7‑bit, 1‑stop, no parity,
9600 baud
8251 FFH 60H Command: TX + RX enabled
8259 80H 76H ICW1: single PIC, 4‑byte
vectors, edge‑triggered
8259 81H 20H ICW2: vector base = 0x20

Baud‑Delay Calculation
[ \text{Bit time (µs)} = \frac{1,000,000}{\text{Baud}} ]
Baud Bit time
110 9 090 µs
300 3 333 µs
1200 833 µs
9600 104 µs
19 200 52 µs
📌 Frequently Used Instructions (8085 Assembly)
; I/O
OUT port ; Write accumulator to I/O port
IN port ; Read from I/O port into accumulator

; Register pairs
LXI H,addr ; Load HL with address
INX H ; HL←HL+1
DCX B ; BC←BC‑1

; Loops & delays

DCR B
JNZ label

; Bit manipulation
RRC / RAR ; Rotate right (carry ↔ D7)
RLC / RAL ; Rotate left (carry ↔ D0)
STC ; Set carry
CMC ; Complement carry
ANI mask ; AND immediate
ORI mask ; OR immediate
```## 📡 RS‑232 Drivers/Receivers

> **MAX232** is a specialized RS‑232 line driver/receiver that eliminates the need for external +12 V supplie

- **Key Features**
- Generates ±10 V internally using a voltage doubler and inverter.
- Provides two drivers and two receivers (four total channels).
- Compatible with TTL logic levels, simplifying system power budgets.

![74LS138 3‑to‑8 Decoder used in the address‑decoding network for RS‑232 interfacing]([Link]
*The 74LS138 decoder routes address lines to select peripheral devices such as the MAX232.*

---

## 📋 8251A USART Initialization

The 8251A (Universal Synchronous/Asynchronous Receiver/Transmitter) must be programmed before data exchange.

### 1️⃣ Mode Word (CAH)

| Bit | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|-----|----|----|----|----|----|----|----|----|
| **Function** | **M** – Async/Sync | **C** – Char length | **A** – Stop bits | **H** – Parity | **–** | **–**

- Example: `CAH = 0xCA` → Asynchronous, 8‑bit chars, 1 stop bit, no parity, baud factor = 16 (TxC/16).

### 2️⃣ Command Word (11H)

| Bit | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|-----|----|----|----|----|----|----|----|----|
| **Function** | **X** – Reserved | **X** – Reserved | **X** – Reset | **D4** – Ignore errors | **D6** – Disa

- `11H` enables both transmitter and receiver while ignoring error conditions.

### 3️⃣ Status Word (01H)

| Bit | D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 |
|-----|----|----|----|----|----|----|----|----|
| **Flag** | **–** | **–** | **–** | **–** | **–** | **TXEMPTY** | **–** | **TXRDY** |

- **TXRDY** (D0) indicates the transmitter is ready to accept the next byte.
- **TXEMPTY** (D2) shows if the output register is empty (used in half‑duplex modes).
 ---

## 🖥️Data Transmission to a CRT Terminal

Below is a concise 8085 assembly routine that follows the initialization steps above and sends a message store

```asm
; -------------------------------------------------
; Initialize 8251A
; -------------------------------------------------
MVI A, CAH ; Load Mode Word (CAH)
OUT FFH ; Write to control register (port FFh)

MVI A, 11H ; Load Command Word (enable TX/RX)

OUT FFH ; Write to command register

; -------------------------------------------------
; Transmit Message
; -------------------------------------------------
LXI H, XX70H ; HL points to message start
MOV C, M ; First byte = character count
INX H ; Point to first character
TX_LOOP:
MOV A, M ; Load character
OUT FEH ; Send to transmitter (port FEh)
DCR C
JNZ TX_LOOP ; Loop until all chars sent
HLT

Note: The routine polls the TXRDY flag before each OUT FEH in a production version to avoid overrunning the transmitter buffer.

🗂️ Intel Hex File Format

An Intel Hex record consists of six ASCII fields, each represented as two‑character hex codes.
Field Description Example (Record 1)
Start Code : (colon) marks the beginning of a record. :
Record Length Number of data bytes (00‑10H). 0A (10 bytes)
Load Offset 16‑bit address where data is placed. 2000
Record Type 00 = data, 01 = End‑of‑File, others for 00
extended segments.
Data Actual data bytes (up to 16). 32 OE A2 79 80 32 50 20 76 DD
Checksum Two’s complement of the sum of all DD
preceding bytes (excluding the colon).
Checksum Calculation

Sum = RecordLength + LoadOffsetHi + LoadOffsetLo + RecordType + Σ(DataBytes)

Checksum = ( ( (Sum ^ 0xFF) + 1 ) & 0xFF )

If the total (including checksum) modulo 256 equals zero, the record is error‑free.

📥 Download (Receiver) Program Flow

The receiver program processes Intel Hex records and stores them in RAM. The high‑level flow is:
 1. Initialize 8251A for reception (reset, then load mode & command words).
2. Wait for start code (:) – ignore any other characters.
3. Read record length, address, type – each as two ASCII hex characters → binary.
4. Read data bytes (as many as the length field).
5. Update checksum accumulator while converting ASCII to binary.
6. Read and verify checksum byte; if non‑zero, raise an error.
7. If record type = 00 (data) → store bytes at the specified address.
8. If record type = 01 (EOF) → finish download.

Sub‑routines (illustrated in the textbook)

Sub‑routine Purpose
RDASKY Enable DTR, read a character from the USART, then disable DTR.
ASCBIN Convert a single ASCII hex digit to a 4‑bit binary value and add
to checksum.
HEXBYTE Call RDASKY twice, convert both nibbles via ASCBIN, combine
into one byte.
CHKSUM Read the final checksum byte and compare with the accumulated
sum.
ERROR Display an error message (implementation depends on the
hardware).

DTR (Data Terminal Ready) is used as a handshake signal: it is asserted before a character is read, then de‑asserted to pause the
sender.

🖥️ Scanned Multiplexed Seven‑Segment Display

A multiplexed display shares segment lines (Port A) and digit‑select lines (Port C) of an 8255A.
Port A (0x80) – drives the seven segment lines (a‑g, DP).
Port C (0x82) – selects which digit (common cathode) is active.
Refresh Loop (pseudo‑code)

; Assume segment codes for 0‑9, A‑F are stored in a table SEG_TAB
; Digit enable patterns: 0x01, 0x02, 0x04, 0x08, 0x10, 0x20

DISPLAY_LOOP:
MVI B, 6 ; six digits to scan
LXI D, MESSAGE_PTR ; point to the message buffer
NEXT_DIGIT:
MOV A, M ; fetch character code
CALL LOOKUP_SEGMENT ; A = segment pattern
OUT 80H ; output to Port A
MOV A, B ; digit selector = 1 << (B‑1)
OUT 82H
CALL DELAY_1MS
XRA A ; clear segments
OUT 80H
DCR B
JNZ NEXT_DIGIT
JMP DISPLAY_LOOP

The rapid on/off of each digit makes the human eye perceive a steady display.
The block diagram shows how the 8255A interfaces to the segment (SN 75491) and digit (SN 75492) drivers.

⌨️ Matrix Keyboard Interface

A 20‑key (5 × 4) matrix uses rows (outputs) and columns (inputs).
Rows → Port C (output).
Columns → Port B (input).
Scanning Algorithm

;-------------------------------------------------
; Scan matrix and return ASCII code in A
;-------------------------------------------------
SCAN_KEY:
MVI A, 7FH ; 0111 1111 – ground first row
OUT 82H ; drive row 0 low
IN 81H ; read columns
ANI 0Fh ; mask upper bits
CPI 0Fh
JZ SCAN_KEY ; no key in this row, continue
; Convert column/row to ASCII (lookup table)
CALL COLROW2ASCII
RET

Key‑debounce is performed by a 10 ms delay routine (DBONCE) that loops on a software counter.

The early terminal image illustrates the kind of display that the keyboard would control.

🖥️ Single‑Board Microcomputer Design (8085)

Major Sub‑systems
Block Primary IC Function
CPU 8085A Executes instructions, generates control
signals.
Memory 2764 EPROM (8 KB) + 6264 SRAM (8 KB) Stores monitor, user program, and data.
I/O Port Expander 8255A Drives scanned display, reads keyboard,
provides user LEDs.
Serial Port 8251A (or MAX232) RS‑232 communication with a CRT
terminal.
Address Decoder 74LS138 Maps I/O and memory spaces.
Drivers SN 75491 (segment) & SN 75492 (digit) Provide sufficient current for LED
segments.

Memory Map (example)

Address Range Device Notes
0000‑1FFF EPROM System monitor (ROM).
2000‑3FFF SRAM Read/Write data memory.
80‑83h 8255A ports 80h = Port A (segments), 81h = Port B
(keyboard cols), 82h = Port C (digit select),
83h = Control.
FFh 8251A control Write mode/command words.
FEh 8251A data Transmit/receive data bytes.
Initialization Sequence (at 0040h)

MVI A, 10000110B ; 8255A control word: Mode 0, A & C output, B input

OUT 83H
LXI SP, 3FFFH ; Stack pointer at top of SRAM
MVI A, CAH ; 8251A mode word (as above)
OUT FFH
MVI A, 11H ; 8251A command word (enable TX/RX)
OUT FFH
EI ; Enable interrupts (RST 6.5 for keyboard)

Main Loop (pseudo‑code)

1. Refresh scanned display (call display routine).
2. Check for interrupt flag – if set, jump to keyboard ISR.
3. Continue looping – the CPU remains responsive to user input while the display is refreshed.
Keyboard ISR (RST 6.5)
Read ASCII code via RDASKY.
Distinguish function keys (e.g., MEMEX, NEXT, EXEC, MON) from hex digits.
Update display buffer, memory address register (DE), or data register (C).
Return with EI to re‑enable interrupts.

🧠 Memory Interfacing & Wait‑State Calculations

When the memory access time exceeds the CPU’s tAD (address‑to‑data valid), the READY line forces the 8085 to insert wait states
(TW).
Device Access Time (ns) 8085 tAD (ns) Extra Time Needed Wait States Required
2764 EPROM (450 ns) 450 575 (for 3 MHz) 125 0 (already satisfied)
Faster 8085A‑2 (350 ns) 450 350 –100 1 (adds one wait state)
Circuit for a Single Wait State
1. ALE → D‑flip‑flop 1 (sets READY low).
2. Clock → D‑flip‑flop 2 (generates a one‑cycle pulse).
3. The pulse holds READY low for exactly one machine cycle, extending tAD.
The diagram demonstrates how a flip‑flop pair creates a single wait state.

🖥️ 8086/8088 Architecture Overview

Key Differences
Feature 8086 8088
Data Bus 16 bits (full‑word transfers) 8 bits (high‑order byte transferred
separately)
Address Bus 20 bits (non‑multiplexed) 20 bits (multiplexed with data bus)
BHE Bus High Enable – selects high‑order byte Used as status line (SS0).
Maximum Mode vs Minimum Mode Requires external bus controller (8288) in Typically used in minimum mode
maximum mode. (single‑CPU system).
Bus Demultiplexing (Minimum Mode)

ALE ──► 373 latch ──► A0‑A15 (address)

└─► Status latch ──► BHE, M/IO, RD, WR, etc.
The 8086 uses the ALE signal to latch address bits while the bus is multiplexed.
Segmentation
Physical address = (Segment << 4) + Offset.
Register Role
CS Code Segment (base for instruction fetch).
DS Data Segment (default for most data accesses).
SS Stack Segment (base for stack operations).
ES Extra Segment (used by string instructions).
IP Instruction Pointer (offset within CS).
BP, SI, DI Additional offsets for complex addressing.

🚀 32‑bit & 64‑bit High‑Performance Processors

80386 / 80486
Feature 80386 80486
Address Bus 32 bits (4 GB physical) 32 bits (4 GB physical)
 Modes Real (1 MB) / Protected (4 GB) Same, plus paging.
Cache None (external only) 8 KB unified on‑chip cache.
Math Unit External (8087) Integrated FPU (≈3× faster).
Pipeline 2‑stage (fetch‑decode) 5‑stage (highly pipelined).

Intel Pentium (Superscalar)

Dual execution units → up to two instructions per clock.
Branch prediction reduces pipeline stalls.
Separate 8 KB I‑cache and 8 KB D‑cache.
Floating‑point unit with 7‑stage pipeline (10× faster than 486 FPU).

RISC Trend
Characteristic Typical RISC (e.g., ARM, MIPS)
Instruction Set < 100 simple, fixed‑length ops.
Addressing Modes 2‑3 simple modes (load/store).
Registers 32‑64 general‑purpose registers.
Execution One instruction per cycle (ideal).
Design Goal Simplicity → higher clock rates & lower power.

🤖 Single‑Chip Microcontrollers
Intel MCS‑51 (8051)
Core: 8‑bit CPU, 4 KB ROM/EPROM, 128 B RAM, 4×8‑bit I/O ports.
Timers: Two 16‑bit programmable timers.
UART: Full‑duplex serial with 8‑bit data, stop bits, parity.
Interrupts: 5 sources (2 external, 2 timer, 1 serial).

Motorola MC68HC11
Core: 8‑bit CPU, 8 KB ROM, 512 B EEPROM, 256 B RAM.
Peripherals: 8‑bit A/D converter (8 channels), 2×16‑bit timers, SCI (serial), SPI.
Operating Modes: Single‑chip (on‑chip RAM only) or expanded (external memory via multiplexed address/data bus).
Both families integrate most peripherals on‑chip, making them ideal for dedicated control tasks.

🌡️ Temperature Sensors (LM135 / LM335)

Parameter LM135 LM335
Output 10 mV / K (linear) 10 mV / K (linear)
Operating Range –55 °C to +150 °C –40 °C to +100 °C
Supply 4.5 V – 18 V 4.5 V – 18 V
Calibration 1‑point slope adjustment (potentiometer). 1‑point slope adjustment; optional 2‑point
calibration.
Typical Accuracy ±1 °C after 1‑point calibration. ±1 °C after 1‑point calibration.
Typical Application (voltage‑to‑temperature conversion)
 VOUT (V) = 10 mV × T(K) → T(°C) = (VOUT / 0.01) – 273.15

A simple resistor divider can be used to read the sensor with a 10‑bit ADC, then apply the formula in firmware.

📐 Key Concepts Recap

USART Initialization – mode, command, and status words configure async communication.
Intel Hex – ASCII‑encoded records with checksum for reliable data transfer.
Multiplexed Displays – share segment lines; refresh quickly to avoid flicker.
Matrix Keyboard Scanning – row‑grounding + column reading, with debounce.
Memory Mapping – use decoders (e.g., 74LS138) to assign address ranges to ROM, RAM, and I/O.
Wait States – generated via the READY line when peripheral latency exceeds CPU timing.
Segmentation (8086/8088) – combine a 16‑bit segment with a 16‑bit offset to form 20‑bit addresses.
Protected Mode – enables paging, larger address spaces, and memory protection.
RISC vs CISC – trade‑offs between instruction set complexity and execution speed.
Microcontroller Integration – on‑chip ROM, RAM, timers, UART, ADC/DAC simplify hardware design.
These notes capture the essential hardware and software techniques required for serial I/O, memory interfacing, display handling, and
📡
system‑level microprocessor design.## 8237A DMA CONTROLLER
Key Concepts
The 8237A multiplexes higher‑order address bits onto the data bus (DB0‑DB7) and latches them onto an external latch
during the S1 state.
AEN (Address Enable) activates a three‑state buffer so the latched address appears on the system address bus A0‑A15.
ADSTB (Address Strobe) is the falling edge that loads the latched address.

Definition – S1 state: a short internal state used only when the high‑order address (A8‑A15) must be updated, saving 255 clocks for
every 258 transfers.

🧩 Registers Overview
Register Size Function Access
Current Address (CA) 16 bits Holds the active transfer Read/Write (8‑bit halves)
address;
auto‑increments/decrements
after each byte/word.
Current Word Count (CWC) 16 bits Number of transfers left (actual Read/Write (8‑bit halves)
transfers = programmed + 1).
Decrements after each
transfer; generates TC when it
rolls from 0 → FFFFh.
Base Address (BA) 16 bits Saved copy of the original Write‑only (cannot be read)
address; used by
Auto‑Initialize after EOP.
Base Word Count (BWC) 16 bits Saved copy of the original Write‑only
count; used by Auto‑Initialize.
Command Register (CR) 8 bits Controls the controller Write‑only; cleared by Reset
(enable/disable, or Master Clear
memory‑to‑memory mode,
timing, priority mode).
Mode Register 6 bits per channel Sets transfer type (verify, Write‑only
write, read, block, demand,
cascade) and address
increment/decrement.
 Request Register 4 bits Holds pending DMA requests Read/Write
(software‑set or external
DREQ).
Mask Register 4 bits Masks/unmasks channels; a Read/Write
set bit disables that channel.
Status Register 4 bits Shows which channels have Read‑only
reached TC or have pending
requests.
Temporary Register 8 bits Holds the last byte transferred Read‑only
in a memory‑to‑memory
operation.

🔄 Transfer Timing (Figure 11)

The waveform shows the relationship of CLK, AEN, ADSTB, DB0‑DB7, and A0‑A7 during a DMA cycle.
The S1 state occurs only when A8‑A15 need updating, giving a saving of 255 clock cycles per 258 transfers.

🛠 PROGRAMMING NOTES
1. Never re‑program a channel while a DMA request is active – either disable the controller (CR bit 2 = 1) or mask the
channel.
2. After power‑up, initialise all Mode registers even for unused channels.
3. Auto‑Initialize takes effect only after an EOP (End‑of‑Process) signal.
4. For Block/Demand modes, the address sequence is linear; the high‑order latch changes only on a carry/borrow from
A7 → A8.

🖥 8259A PROGRAMMABLE INTERRUPT CONTROLLER (PIC)

Definition – Interrupt Request Register (IRR): 8‑bit register that records which IRQ lines are requesting service, independent of the
mask.

Definition – In‑Service Register (ISR): 8‑bit register that records which IRQs are currently being serviced.

📦 System Block Diagram

The diagram illustrates the flow of interrupt requests (IR0‑IR7), the priority resolver, mask logic, and the three‑state bus buffers that
place the vector on the data bus during an INTA cycle.
📌 Pin Description (excerpt)
Pin Symbol Function
1 CS Chip Select (active LOW) – enables
command/status register access
2 WR Write strobe (active LOW) – writes
command/ICW/OCW
3 RD Read strobe (active LOW) – reads
status/IRR/ISR/IMR
4 A0 Address line – selects command vs. data
registers
5‑12 D0‑D7 Bidirectional data bus
13 INT Interrupt output to CPU (active HIGH)
14 IR0‑IR7 External interrupt request inputs
15 CAS0‑CAS2 Cascade lines for multi‑PIC configurations
16 SP/EN Dual‑function: slave‑program enable
(buffered mode) or master/slave select
📑 Register Sets
Register Address (A1‑A0) Bits Description
ICW1 00 8 Starts initialization; sets
edge/level sense, IC4 flag, etc.
ICW2 01 8 Sets high‑order interrupt
vector (A8‑A15) for this PIC
ICW3 10 (if needed) 8 Master: bitmask of slaves;
Slave: ID of this PIC
ICW4 11 (if IC4=1) 8 Sets mode: buffered,
special‑nested, AEOI,
microprocessor type
OCW1 00 8 Mask register – 1 = masked
OCW2 01 8 Controls EOI, rotate, specific
level
OCW3 10 8 Enables special mask mode,
selects status register
(IRR/ISR)
OCW4 11 (optional) 8 Additional control in some
implementations

⚙️ Operating Modes
Mode Description
Fully Nested (default) Fixed priority 0 (high) → 7 (low). An ISR bit stays set until an EOI
is issued.
Rotating Priority After each interrupt the priority rotates so the serviced level
becomes the lowest.
Special Mask Mode (SMM) Allows the mask register to block lower‑priority requests while
higher‑priority ISR bits remain set.
Poll Mode CPU manually polls the PIC; the next RD is treated as an
interrupt acknowledge.

🔁 Interrupt Sequence (8085 / 8080)

1. IRQ line goes HIGH → sets the corresponding IRR bit.
2. PIC asserts INT (HIGH) to the CPU.
3. CPU acknowledges with INTA pulse.
4. PIC places the CALL opcode (11001101b) on the data bus (first INTA).
5. Second INTA delivers the vector low byte; third INTA (if required) delivers the high byte.
6. ISR bit set; if AEOI is enabled, a non‑specific EOI is automatically performed after the last INTA pulse.
⏱ Timing Example (Figure 10)
The diagram shows setup and hold times for edge‑triggered mode, including the “LATCH ARMED” and “EARLIEST IR CAN BE
REMOVED” markers.
📝 Command Word Tables
Command Register (CR) Bit Map
Bit 7 6 5 4 3 2 1 0
Name M M (Enable) CH CH IF E (Enable C N (Normal
(Memory‑to‑Memory) (Channel 0 (Channel 0 (Interrupt Force)controller) (Compressed timing)
hold) enable) timing)
Mode Register (per channel) – Bits 5‑0
Bits 5‑4 3 2‑1 0
Transfer Type 00 = Verify 01 = Write 10 = Read 11 = Illegal
Auto‑Init 0 = disabled 1 = enabled
Address Increment 0 = increment 1 = decrement
Mode Select 00 = Demand 01 = Single 10 = Block 11 = Cascade

⌨ 8279 PROGRAMMABLE KEYBOARD/DISPLAY INTERFACE

Definition – FIFO: an 8‑byte first‑in‑first‑out buffer that stores scanned keycodes (or sensor data) until the CPU reads them.

📐 Pin Configuration
Pins 1‑20 show data lines (DB0‑DB7), control lines (CS, A0, RD, WR), clock, reset, and the multiplexed scan/return lines (S0‑S3, R0‑R7).
🏗 Internal Block Diagram
8279 Internal Block Diagram

The block diagram details the I/O control logic, timing registers, scan counter, FIFO/Sensor RAM, and the display RAM interface.
📋 Registers & Commands
Register / Command Function Example Code (binary)
Mode Set Select keyboard/display mode, data 00 0 0 0 → Scanned Keyboard, 2‑Key
length, scan type Lockout
Read FIFO / Sensor RAM Reads next byte from FIFO (keyboard) or 0100 0000b
sensor RAM
Write Display RAM Writes a character to the current display 1000 0AIb (AI = auto‑increment)
address
Clear Display Clears all display RAM to a blank code 1100 1 0 0
Set Clock Prescaler Sets internal scan frequency (divide 0101 PPPPPb (PPPPP = 2‑31)
external clock)
Read Status Word Returns FIFO status (full, empty, error) 0010 0000b

⌨ Keyboard Modes
Mode Description
Scanned Keyboard – 2‑Key Lockout Encoded (8×8) or decoded (4×8) matrix; only two simultaneous
keypresses are allowed.
Scanned Keyboard – N‑Key Rollover Unlimited simultaneous keypresses; each key is debounced and
queued.
Scanned Sensor Matrix No debounce; raw logic levels of each switch are stored directly
in Sensor RAM.
 Strobed Input External device supplies data on the return lines; a rising edge on
CNTL/STB stores the byte in FIFO.

📺 Display Modes
Mode Addressing Auto‑Increment Example Use
Left Entry Address 0 → 15 (or 0 → 7) maps Optional (AI) Simple scrolling from left to
directly to display positions right.
Right Entry First character appears at the Optional (AI) Calculator‑style entry.
rightmost digit; subsequent
chars shift display left.
Auto‑Increment After each write, the display AI = 1 Continuous string output
address pointer advances without re‑specifying address.
automatically.
Blanking BL bits per nibble suppress – Turn off unused digits.
output of that digit.

📊 Example Command Sequence (Write “HELLO” to a 5‑digit display, left‑entry)

; Assume 8‑bit data bus, CS=0, A0=1 for command
MVI A, 0x20 ; Function Set: 8‑bit, 2‑line, 5×7 font
OUT 0x01 ; Write command to 8279
MVI A, 0x01 ; Set Display RAM address = 0 (leftmost)
OUT 0x01
MVI A, 'H' ; ASCII for H = 0x48
OUT 0x01
MVI A, 'E' ; 0x45
OUT 0x01
MVI A, 'L' ; 0x4C
OUT 0x01
MVI A, 'L' ; 0x4C
OUT 0x01
MVI A, 'O' ; 0x4F
OUT 0x01
HLT

🧮 8085 INSTRUCTION SET – QUICK REFERENCE

Note – All opcodes are shown in hex, the number of bytes, machine‑cycles, and T‑states are given for the original 8085.

Mnemonic Operand Bytes M‑Cycles T‑States Hex

NOP – 1 1 4 00
LDA addr16 3 4 13 3A
STA addr16 3 4 13 32
MOV Rd,Rs 1 1 4 40‑7F
MVI Rd,byte 2 2 7 06‑3E
LXI Rp,addr16 3 3 10 01‑3A
INX Rp 1 1 6 03‑13‑23‑33
DCX Rp 1 1 6 0B‑1B‑2B‑3B
ADD Rs 1 1 4 80‑87
 ADI byte 2 2 7 C6
SUB Rs 1 1 4 90‑97
SUI byte 2 2 7 D6
INR R 1 1 4 04‑0C‑14‑1C
DCR R 1 1 4 05‑0D‑15‑1D
JMP addr16 3 3 10 C3
JC addr16 3 3/2 10/7 DA
JNC addr16 3 3/2 10/7 D2
CALL addr16 3 5 18 CD
RET – 1 3 10 C9
EI – 1 1 4 FB
DI – 1 1 4 F3
HLT – 1 1+ 5+ 76
RLC – 1 1 4 07
RRC – 1 1 4 0F
RAL – 1 1 4 17
RAR – 1 1 4 1F
CMA – 1 1 4 2F
STC – 1 1 4 37
CMC – 1 1 4 3F
PCHL – 1 1 6 E9
XCHG – 1 1 4 EB

🔧 Common Instruction Groups

Group Typical Use
Arithmetic ADD, ADI, SUB, SUI, INR, DCR, INX, DCX
Logical ANA, ANI, ORA, ORI, XRA, XRI, CMA
Branching JMP, JC, JNC, JZ, JNZ, CALL, RET, RST
Stack Operations PUSH, POP, XTHL, SPHL
I/O IN, OUT
Control EI, DI, HLT, NOP

🧪 Example: Subtract Two Memory Bytes (addresses 2051h & 2052h)

ORG 2030H ; program start
LDA 2051H ; A ← [2051h] (minuend)
MOV B, A ; B ← A
LDA 2052H ; A ← [2052h] (subtrahend)
SUB B ; A ← A – B
STA 2053H ; store result
HLT
END
Result: If [2051h]=9Fh and [2052h]=25h, the subtraction yields 86h (two’s‑complement negative), setting Sign and Carry flags.

🖥 8085 SIMULATOR & ENVI85 (Software Development Flow)

1️⃣ Installation & Launch
Insert the supplied CD, run [Link].
Destination folder can be C:\8085.
Shortcut appears under Start → Programs → Infosolutions → Microprocessor Simulator 8085.

2️⃣ Loading a Program

1. File → Open Code File – select a .asm or .hex file.
2. Set I/O port options if the program uses OUT/IN (e.g., port 01h).

3️⃣ Assembling (ENVI85)

Press F5 in the editor.
Errors are shown with the line number; fix and press F5 again.
Successful assemble creates <filename>.hex and <filename>.prn.

4️⃣ Simulation
Function Key Action
F1 Run the program from the start address (default 0100h).
F3 Single‑step one instruction (observe registers, flags).
F5 View register window (PC, SP, flags, registers).
F6 Set a breakpoint at a given address.
F2 Restart (reset PC, registers, and memory).
F10 Exit the simulator and return to the editor.

5️⃣ Example Simulation Walk‑through

ORG 2000H
MVI A, 32H ; Load 0x32 into accumulator
MVI B, 48H ; Load 0x48 into B
ADD B ; A ← A + B → 0x7A, flags cleared
OUT 01H ; Display 0x7A on simulated port 01h
HLT
END

After F1 (Run), the Simulator window shows A=7Ah, B=48h, port 01h = 7Ah.
F3 (Step) highlights each instruction in violet as it executes; registers that change turn violet, unchanged ones stay white.

📊 QUICK REFERENCE TABLES

1️⃣ DMA REGISTER DESCRIPTIONS (8237A)
Register Size Reset Value Remarks
Current Address 16 bits 0 Auto‑increment/decrement
after each transfer
Current Word Count 16 bits 0 Transfer count =
programmed + 1
 Base Address 16 bits N/A Loaded together with Current
Address (write‑only)
Base Word Count 16 bits N/A Loaded together with Current
Word Count (write‑only)
Command Register 8 bits 0 Bits: M (mem‑to‑mem), EN
(controller enable), C
(compressed timing), N
(normal timing), etc.
Mode Register 6 bits/channel 0 Transfer type, address
direction, auto‑init, mode
(demand, block, cascade)
Request Register 4 bits 0 Software set/clear request bits
Mask Register 4 bits 0 1 = masked (disabled)
Status Register 4 bits 0 TC flags for each channel
Temporary Register 8 bits 0 Holds last byte of a
memory‑to‑memory transfer

2️⃣ PIC COMMAND WORDS (8259A)

OCW Bits (7‑0) Function
OCW1 M7‑M0 Interrupt mask bits (1 = masked)
OCW2 R SL EOI L2 L1 L0 Rotate/Specific/EOI control
OCW3 ESMM SMM RR RIS Enable/Select Special Mask Mode, Read
Register Select (IRR/ISR)
ICW1 LTIM IC4 SNGL ADI ... Edge/Level trigger, need ICW4,
single‑chip, address interval
ICW2 A7‑A0 High‑order vector base
ICW3 S7‑S0 Master‑slave configuration
ICW4 BUF M/S AEOI uPM Buffered mode, master/slave, automatic
EOI, microprocessor mode

3️⃣ 8279 COMMAND CODES (binary)

MSB‑LSB Description
000 DD KKK Set Display Mode (DD) and Keyboard Mode (KKK). Example:
000 01 100 → 8‑bit display, right entry, N‑key rollover keyboard.
001 AAA Set Clock Prescaler (PPPPP = AAA).
010 AAA Read FIFO / Sensor RAM (AAA = address).
011 AAA Write Display RAM (AAA = address, AI controlled by bit 4).
100 0 00 B C Clear Display (blank code = B, clear all = C).
101 0 0 0 0 Reset (internal reset).

📚 SUMMARY OF KEY POINTS

DMA (8237A) uses a latch to extend the 8‑bit data bus for high‑order address bits, saving clock cycles by updating the latch
only when needed.
PIC (8259A) provides up to 8 interrupt levels (expandable to 64 via cascade), with flexible priority schemes and automatic or
software‑controlled End‑of‑Interrupt handling.
 Keyboard/Display (8279) off‑loads scanning, debouncing, and display refresh from the CPU; supports multiple keyboard
modes and left/right entry display formats.
The 8085 instruction set is compact; most operations fit in 1‑2 bytes and execute in 4‑7 T‑states. Understanding flag effects
(S, Z, AC, P, CY) is essential for correct arithmetic and branching.
Simulators (Micro‑3, ENVI85) let you write, assemble, and step through code, view registers, and test I/O ports without
hardware.

All timing values, register maps, and command encodings are taken directly from the source documentation.