Introduction to VLSI Technology

 The discussion begins by defining an integrated circuit and contrasting it with discrete
circuits, which consist of separate components like capacitors and transistors.

 Integrated circuits house all components, including active and passive elements, on a
single substrate.

 The complexity of integrated circuits is categorized into small scale integrated circuits
(SSI), medium scale integrated circuits (MSI), large scale integrated circuits (LSI),
and very large scale integrated circuits (VLSI), with VLSI containing millions of
transistors.

Materials and Properties of VLSI Chips

 More than 95 percent of today's VLSI chips are made from silicon, a Group IV
element semiconductor known for its desirable properties.

 Silicon is typically used in the form of single crystal silicon, which is essential for the
performance of integrated circuits.

 Active elements in circuits can be bipolar junction transistors (BJTs) or MOSFETs,

with BJTs favored for high-speed applications and MOSFETs for high packing
density.

 The evolution of VLSI technology has led to the integration of BJT and MOSFET
technologies, resulting in BIMOS or BICMOS technology.

Course Structure and Objectives

 The course will be organized to first cover BJT and MOSFET technologies, focusing
on the processing steps required to realize each type of transistor.

 Students will learn about the processing steps necessary for the fabrication of these
active elements in integrated circuits.

 The lecture will start with the BJT technology as it is the older of the two
technologies.

Fabrication of Bipolar Junction Transistors

  The process of fabricating a silicon bipolar junction transistor begins with selecting a
p-type single crystal substrate with specific resistivity.

 The substrate must be single crystal with a defined orientation, typically grown to
ensure specific electrical properties.

 Doping the silicon substrate with boron is necessary to achieve the desired p-type
characteristics.

 The first processing step in VLSI technology involves crystal growth, which is crucial
for the performance of the final device.

Oxidation Process in VLSI

 The next step after obtaining the silicon substrate is to grow an oxide layer on its
surface, which is essential for insulation and dielectric properties.

 Silicon readily oxidizes in an oxygen-rich environment, forming silicon dioxide,

which is used as an insulating layer.

 The oxide layer also has masking properties, allowing selective doping of the
substrate by protecting certain areas from dopants.

Photolithography Technique

 Photolithography is employed to selectively remove the oxide layer from specific

regions of the silicon substrate.

 This process involves coating the oxidized silicon with a photo-sensitive material
called photo resist, which reacts to UV light.

 A mask with transparent and opaque patterns is used to expose the photo resist to UV
light, allowing selective removal of the oxide beneath the exposed areas.

 After removing the desired portions of the oxide, etching is performed to further
define the regions for doping.

Doping and Epitaxy in Transistor Fabrication

 Doping is achieved through diffusion, where n-type dopants are introduced into the
exposed regions of the silicon substrate.
  Buried layer diffusion is a specific technique used to create an n-plus layer beneath
the epitaxial layer, which acts as the collector of the transistor.

 Epitaxy involves growing a thin n-type layer on the substrate, facilitating the
formation of the transistor's collector region.

 The process of isolation between transistors is crucial, often achieved using reverse-
biased pn junctions to prevent current leakage between adjacent devices.

Final Steps in Transistor Fabrication

 The base and emitter regions are realized through further doping, with the base being
doped before the emitter due to the latter's higher doping concentration.

 Contact metallization is the last step, where metal contacts are established for the
base, emitter, and collector regions, typically using aluminum.

 The metallization process also requires selective deposition techniques to ensure

proper electrical contacts are formed.

 Doping can be performed through diffusion or ion implantation, with the latter
providing greater flexibility in the doping process.

MOSFET Fabrication Process

 MOSFET fabrication requires only four processing steps: field oxidation, source and drain
doping, gate oxidation, and contact metalization, making it simpler than bipolar junction
transistor fabrication.

 The gate oxide is critical for MOSFET performance, requiring stringent quality control and
a separate processing step from the field oxide.

 Gate oxide thickness is much less than field oxide thickness, directly impacting
the threshold voltage and requiring precise control for optimal device performance.

Threshold Voltage Control

 Threshold voltage depends on factors like gate oxide thickness, substrate doping
concentration, gate metal, and oxide charges.
  Ion implantation is a sophisticated doping technique used for local substrate doping
concentration alteration, enabling precise threshold tailoring in modern MOSFET
fabrication.

 Threshold tailoring implant is performed only in the channel region of the MOSFET,
allowing for specific threshold voltage values unachievable with less advanced doping
techniques.

Advanced Fabrication Techniques

 In polysilicon gate technology, gate oxidation precedes source and drain doping,
enabling self-aligned source and drain without an additional mask.

 Polysilicon gate technology has advanced to allow fabrication of MOSFETs with

proper threshold control, surpassing earlier metal gate technology limitations.

Critical Factors in MOSFET Performance

 MOSFET performance is determined by factors including substrate type, source and
drain doping, gate oxide thickness, and contact metalization.

 Gate oxide quality directly impacts MOSFET performance and requires careful
control for optimal results.

 Lateral encroachment of source and drain doping into the channel region is more
significant for deeper junctions and can be reduced using shallower junctions.

 Unwanted charges in the gate oxide, such as positive ions like sodium and potassium,
can affect threshold voltage and should be minimized during oxidation.

Crystal Structure and Properties

 Silicon has a diamond crystal structure with two interpenetrating fcc sublattices of
identical silicon atoms, a lattice constant of 5.43 Å, and a tetrahedral radius of 1.18 Å.

 The zinc blende structure has a packing density of 34%, while the fcc lattice is much
more densely packed at over 70%, with a nearest neighbor distance of a√2 and
a tetrahedral radius of a/2√2.

Doping and Impurities

 The misfit factor (Δ) is defined as (r0 - rimp) / r0, where r0 is the tetrahedral radius of
silicon and rimp is the tetrahedral radius of the impurity atom.
  Arsenic and phosphorus have a misfit factor of 0, making them ideal for n-type
doping in silicon, while antimony has a misfit factor of 0.15.

 Boron has the largest misfit factor due to its smaller tetrahedral radius of 0.8 Å,
making it more challenging to achieve high carrier concentrations in p-type silicon.

 The ease of doping silicon is directly related to the misfit factor, with n-type
doping being generally easier than p-type doping due to the closer match in tetrahedral
radii.

Crystal Structure and Planes

 The packing density of (100), (110), and (111) planes in silicon crystal is 2/a^2, 2√2/a^2,
and 4/√3a^2 respectively, influencing key properties.

 Separation between adjacent parallel planes in silicon crystal is given by a/√(h^2 + k^2 +
l^2), where h, k, and l are Miller indices.

 The atomic density of (100), (110), and (111) planes in silicon crystal is 2/a^2, 2√2/a^2,
and 4/√3a^2 respectively, with (111) having the highest density.

Crystallographic Calculations
 Angle between two planes in silicon crystal: cos(θ) = (U1U2 + V1V2 + W1W2) / √(U1^2 +
V1^2 + W1^2) * √(U2^2 + V2^2 + W2^2).

 Line of intersection between two planes: u = V1W2 - V2W1, v = W1U2 - W2U1, w = U1V2 -
U2V1.

Manufacturing and Properties

 Growing silicon crystals in the (111) direction is cheaper than (100) or (110), making
(111) wafers more readily available for bipolar junction transistors.

 The (111) plane has the least spacing between adjacent planes, making it difficult to
etch and grow crystal but giving it the highest tensile strength and modulus of
elasticity.
 (111)plane meets (100) plane at 54.74° and (110) plane at 70.53°, resulting in
non-90° angles when cleaving silicon.

Oxidation and Processing

 (111)plane has the lowest atomic density, making it the fastest to oxidize, resulting in
thicker oxides compared to (100) planes under identical conditions.
  Oxide thickness depends on crystal orientation, with (111) planes growing thicker
oxides than (100) planes during wafer oxidation.

Practical Implications

 The (111) plane is the natural cleavage plane for silicon due to its high tensile strength
and modulus of elasticity.

 Crystal orientation significantly affects wafer processing, including oxidation rates,

etching behavior, and mechanical properties.

Crystal Defects and Electronic Properties

 Point defects like vacancies and interstitials significantly impact electronic properties,
with vacancies requiring 1-2 eV activation energy to break 4 bonds and interstitials
occupying empty spaces in the lattice.

 Interstitial defects, such as lithium in silicon, can act as electronically active

donors without forming bonds, due to their monovalent nature.

 Vacancies act as acceptors (accepting 1-4 electrons), while interstitials act

as donors (giving 1-4 electrons), creating deep energy levels within the band gap.

Crystal Growth and Defect Control

 The Zokasi technique for growing single crystal silicon uses a seed
crystal and temperature gradient, producing fewer defects than the Bridgman technique.

 Silicon crystal growth technology has advanced to eliminate area dislocation and area
defect problems, ensuring materials are suitable for integrated circuit fabrication.

 Area defects (twinning, grain boundaries) and volume defects (precipitates) are
undesirable and cause material rejection in IC fabrication.

Defect Applications and Implications

 Deep energy levels from point defects can control minority carrier lifetime, enabling the
creation of fast switching devices like diodes.

 Impurities like gold and platinum are deliberately introduced to create deep levels, reducing
minority carrier lifetime for fast switching applications.
  Dislocations, one-dimensional defects formed by excessive sheer stress, require more
energy to create than point defects and significantly affect electronic properties.

Silicon Processing and Defect Formation

 Dislocations in silicon can form due to thermal stress, constriction during solidification,
or excessive impurity atoms, leading to premature breakdown and leakage.

 Silicon crystal growth involves carbothermic reduction of silicon dioxide with carbon to
form polycrystalline silicon, followed by controlled melting and solidification.

 For applications requiring long minority carrier lifetimes, it's crucial to ensure the absence
of deep levels in the silicon material.

Crystal Growth Techniques

 Zoraki technique produces silicon crystals with significantly fewer dislocations and
defects compared to the Bridgeman technique, making it the preferred method for high-
quality single crystal growth.

 The pool rate in crystal growth is inversely proportional to crystal diameter, with a 75mm
diameter crystal requiring a pull rate of only 1.5mm/min to maintain low defect density.

 Latent heat of solidification is the primary mechanism for heat transfer in crystal growth,
accounting for almost all heat loss due to typically small thermal gradients.

Dopants and Impurities

 The segregation coefficient (K0) of a dopant is the ratio of its solid

solubility to equilibrium solubility in the melt, with most common impurities
having K0 < 1.

 Oxygen incorporation during crystal growth can lower breakdown

voltage and increase leakage current, as oxygen has a segregation coefficient
> 1.

 Oxygen concentration in Zoraki-grown crystals ranges from 5x10^17 to 10^18

per cm^3, with 95% in interstitial sites and 5% forming donor-like complexes.

Crystal Defects and Treatment

 SiO4 complexes form at 450-500°C and can be dissolved by heating the

crystal above 600°C, a common practice to reduce donor complexes.
  The Bridgeman technique has a drawback of charge expansion on
solidification, creating stress and dislocations due to the confining quartz boat
boundary.

Zoraki Crystal Growth System

 The Zoraki crystal growth system consists of four subsystems: furnace, crystal
pulling mechanism, ambient control, and control system.

 The furnace in the Zoraki system is a quartz envelope with gas inlets/outlets
and a graphite heater typically heated by RF.

 Pool rate in the Zoraki technique must be carefully adjusted to avoid melting
the seed crystal, considering factors like latent heat, thermal conductivity, and
thermal gradients.

 The Zoraki technique requires control of numerous parameters to produce

high-quality single crystals, making it more complex than the Bridgeman
technique.

Crystal Growth Techniques

 Czochralski (CZ) technique produces high-quality silicon crystals with lower

defect density than Bridgman method, but still faces challenges due to oxygen
contamination leading to precipitates and dislocations.

 Zone refining further purifies CZ-grown crystals by repeatedly melting and

solidifying small portions, reducing oxygen content by 10-100 times and
minimizing dissolved impurities.

 Float Zone (FZ) crystals offer superior resistivity, lower oxygen content,
and higher breakdown voltage (>1000V), making them ideal for power device
applications.

Epitaxial Growth

 Epitaxy enables growth of thin crystalline layers on bulk substrates, allowing

for homoepitaxy (same material) or heteroepitaxy (different materials) with
minimal lattice and thermal mismatches.
 Strained layer epitaxy in heteroepitaxy produces thin layers with different
lattice structures, resulting in unique properties useful in compound
semiconductor technology.

 Vapor phase epitaxy is widely used in VLSI, utilizing gas reactants to deposit
material on substrates, with boundary layer thickness crucial for controlling
growth rate and uniformity.

Advanced Techniques and Considerations

  Molecular beam epitaxy (MBE) employs physical evaporation without chemical
reactions, offering a sophisticated method for precise thin layer growth.

 In-situ cleaning is critical before epitaxy to prevent contamination, ensuring

high-quality epitaxial layers and optimal device performance.

 Liquid phase epitaxy involves cooling a solution to precipitate material onto a

substrate, but is less suitable for silicon due to dissolution difficulties.

Impurity Management

 Gettering removes metallic contamination from semiconductor active regions

using induced dislocations or oxygen precipitates as impurity sinks.

 Vapor phase epitaxy's stagnant layer near the substrate creates

a concentration gradient of reactants, affecting the flux and growth rate of the
epitaxial layer.

 Homoepitaxy (silicon on silicon) is the primary method in VLSI for growing thin
layers with varied doping concentrations while maintaining consistent material
properties.

Chemical Vapor Deposition Process

 Vapor phase epitaxy is a chemical vapor deposition process where silicon

tetrachloride or chlorosilanes are reduced by hydrogen to
form silicon and hydrochloric acid on the sample surface, requiring surface
catalysis for the reaction to occur.

 Optimization of temperature and pressure is crucial in epitaxy, balancing

improved surface mobility and crystal quality against increased thermal
stress and dopant intermixing.

Low Pressure Chemical Vapor Deposition

 LPCVD operates at 20-200 mTorr, allowing for increased gas flow

velocity and temperature stability while minimizing boundary layer
thickness and convection effects.
 Silicon tetrachloride is the most stable precursor,
but chlorosilanes like SiH3Cl3 and SiH2Cl2 offer advantages
in temperature and efficiency of deposition.

 Growth rate is sensitive to silicon tetrachloride concentration, with increased

concentrations leading to higher rates but potential etching beyond a mole
fraction of 0.28.

Surface Preparation and Doping

  Surface preparation is critical, requiring in-situ
cleaning and etching techniques to ensure a damage-free and oxide-
free surface for high-quality epitaxial layers.

 Doping during epitaxy uses hydrides of desired dopants

(e.g., boron, phosphorus, arsenic) to introduce them into the growing layer.

Challenges and Advanced Techniques

 Autodoping is a significant problem, causing unintentional doping due to

dopant diffusion from the substrate during high-temperature processing.

 SF6 is a newer etching agent offering advantages over hydrogen

chloride (HCl), being non-toxic and usable at lower
temperatures (around 1200°C).

Deposition Mechanisms

 Chlorosilane reactions are reversible and can occur anywhere in the chamber,
while silylene reactions are non-reversible and produce abrupt layers at lower
temperatures (around 500°C).

Epitaxy Types and Applications

 Silicon epitaxy can be performed using chemical vapor deposition (CVD)

or physical vapor deposition (PVD) techniques, with applications in creating
high-quality semiconductor layers.

Autodoping and Junction Shift

 Autodoping occurs when the epitaxial layer gets inadvertently doped during
growth, limiting its thickness due to solid-state diffusion and gas-phase
autodoping.

 Junction shift results from misalignment of metallurgical and electrical

junctions, caused by gas-phase autodoping and solid-state diffusion of P-type
dopants from the substrate.

 Lateral autodoping modulates doping concentration adjacent to the substrate,

potentially causing electrical shorts between devices if not properly isolated.

Pattern Shift and Growth Control

  Pattern shift and distortion occur due to crystal growth dependence on
orientation, caused by exposure of multiple crystal planes during epitaxial
growth.

 High deposition temperatures (>1000°C) minimize pattern shift by

increasing surface mobility, resulting in isotropic growth rates and uniform
crystal quality.

 Operating in the low growth rate region (e.g., reduced SiCl4 concentration)
leads to better crystal quality and isotropic growth rates, minimizing pattern
shift.

Defects and Selective Epitaxy

 Stacking faults, the most common defects in epitaxial layers, are caused
by native oxide patches on the substrate surface, disrupting epitaxial growth.

 Selective epitaxy achieves island-like epitaxial regions with automatic device

isolation by covering unwanted areas with SiO2 or polycrystalline Si.

Simulation and Optimization

 Computer simulations isolate effects of gas-phase autodoping and solid-state

diffusion on junction shift, showing both contribute to autodoping effects.

 Misorienting the substrate by 2-4° on (111) wafers minimizes pattern shift,

while (100) substrates require careful control of epitaxial growth parameters.

 Reducing chlorine and operating at lower pressure minimize pattern shift by

allowing faster venting of chlorine and HCl, reducing anisotropic growth.

 A transition layer forms between bulk and epitaxial regions due to autodoping
effects, limiting epitaxial layer thickness and affecting doping concentration.

Advanced Semiconductor Fabrication

 Molecular Beam Epitaxy (MBE) enables precise control of dopant

incorporation and growth rates as low as 0.01 micrometers per
minute under ultra-high vacuum conditions of 10^-8 to 10^-10 Torr.

 MBE eliminates autodoping and boundary layer problems present in vapor

phase epitaxy, allowing for thin layer growth with accurate doping and
thickness control.
  The heart of the MBE system is the ultra-high vacuum pumping system,
combining turbomolecular, cryo, and ion sublimation pumps to minimize
contamination and collision issues.

Characterization Techniques

 Reflection High-Energy Electron Diffraction (RHEED) assesses crystal quality

by focusing an electron beam at a 1° grazing angle onto the growing layer
surface.

 X-ray Photoelectron Spectroscopy (XPS) determines layer composition by

measuring the energy distribution of electrons emitted when bombarded with
x-rays.

 Mass spectrometry monitors gas composition, dopant levels, and layer

quality in real-time during the MBE process.

Doping and Processing

 Iron implantation offers better control over doping profiles compared to effusion
cell doping by bombarding the substrate with iron ions.

 Oxidation of silicon grows a thin layer of silicon dioxide by reacting the

substrate with oxygen or steam, crucial for subsequent processing steps.

 Deionized water with resistivity > 10 megaohms is essential for cleaning

wafers, as it lacks ionic impurities detrimental to device performance.

System Design and Functionality

 MBE systems often incorporate a load lock chamber for substrate introduction
and a multi-chambered system for in situ cleaning and characterization.

 Effusion cells with small openings create jets of evaporated dopants,

controlled by microprocessors to regulate layer thickness and dopant
incorporation.

 MBE's ultra-high vacuum environment enables integration of sophisticated

characterization techniques for real-time monitoring and quality control.

Oxidation Kinetics
 The Deal-Grove model explains silicon thermal oxidation kinetics by predicting
oxidation rates based on three fluxes: gas phase mass transfer, diffusion
through oxide layer, and reaction at silicon-oxide interface.
  Thermal oxidation of silicon produces the best quality oxide in VLSI
technology due to contamination remaining on the outer surface, preserving
the critical silicon-oxide interface.
Oxide Growth Factors
 Oxide growth rate is determined by the availability of oxidizing species at the
silicon-oxide interface, controlled by the diffusion coefficient through the oxide
layer.
 The process is diffusion-limited when the diffusion coefficient is low
and reaction-limited when it's high, affecting the overall oxidation rate.
Oxide Thickness Calculation
 Oxide thickness increases with time according to the oxide growth rate
equation, derived from solving the differential equation with initial conditions
and Deal-Grove model constants.
 The number of oxidant molecules incorporated per unit volume of oxide
relates to the flux of oxidizing species at the silicon-oxide interface, governed
by the Deal-Grove model.
Oxidation Kinetics
 The Deal-Grove linear parabolic equation (x² + ax = bt + toa) predicts linear
growth for short oxidation times and parabolic growth for long times, with
constants a = 2D/(k+1/h) and b = 2DCsN1.
 Wet oxidation is much faster than dry oxidation due to higher equilibrium
concentration of oxidizing species (Cs = 310^19 vs 5.210^16) and
larger number of oxidant molecules per unit volume of oxide (N1).
 Oxidation rate constants B and B/A increase with temperature due to diffusion
coefficient D and reaction rate constant KS, while A decreases.
Oxidation Types and Applications
 Dry oxidation is used for gate oxidation where quality is prioritized over
quantity, resulting in controlled thinner growth of oxide with better quality.
 Oxide thickness less than 270 angstroms cannot be adequately explained by
the Deal-Grove model, posing a challenge for growing thin gate oxides (<100
angstrom thickness).
 Dry oxidation exhibits a non-zero intercept on the oxide thickness axis,
indicating a finite initial oxide thickness not predicted by the Deal-Grove
model.
Doping Effects on Oxidation
  Heavily boron-doped silicon oxidizes faster than moderately doped silicon at
all temperatures due to diffusion of oxidizing species through borosilicate
glass.
 Heavily phosphorus-doped silicon oxidizes faster only at lower temperatures
due to reaction rate increase at the silicon-silicon dioxide interface.
Oxidation Parameters
 Wet oxidation grows thicker oxide faster than dry oxidation at the same
temperature, with higher growth rates at higher temperatures.
 The linear rate constant (B/A) and parabolic rate constant (B) for oxide growth
depend on the type of oxidation, temperature, and equilibrium concentration
of oxidizing species.
 Oxide growth rate is faster in wet oxidation than in dry oxidation due to higher
equilibrium concentration of oxidizing species (Cs) and larger number of
oxidant molecules per unit volume of oxide (N1).
 The Deal-Grove model challenges include explaining very thin oxide growth
and the non-zero intercept observed in dry oxidation.

Dopant Behavior and Oxidation Effects

 Segregation coefficient (K) determines whether dopants prefer to stay

in silicon or move into silicon dioxide, with K > 1 favoring silicon and K < 1
favoring silicon dioxide.

 Boron (K < 1) aids oxidation by increasing its presence in silicon dioxide,

resulting in faster oxide growth at all temperatures.

 Phosphorus (K > 1) causes a pileup at the silicon-silicon dioxide interface,

leading to thicker oxide growth at lower temperatures.

Oxidation Processes and Characteristics

 Thermal oxidation in a quartz furnace is a critical VLSI step, affecting

oxide quality, thickness, and ultimately circuit performance.
 High pressure oxidation enables thicker oxides, reduces thermal
budget and stress, increases throughput, and saves money.

 Wet oxidation produces thicker, crystalline oxides with more defects, while dry
oxidation yields denser, higher quality amorphous oxides.

Charge-Related Non-Idealities
  Interface trapped charges in the silicon-silicon dioxide interface significantly
impact MOSFET characteristics, arising from mechanical damage or broken
bonds.

 Fixed oxide charges, located ~100 Å from the interface, are

predominantly positive and result from incomplete oxidation.

 Oxide trapped charges can occur due to radiation exposure, hot electron
injection, or mobile ionic contamination.

Mobile Ionic Charges and Their Effects

 Mobile ionic charges (e.g., sodium, potassium) can move throughout the oxide,
affecting device characteristics and detectable through C-V analysis.

 Gallium (K > 1), an extremely fast diffuser, causes depletion at the interface
and a sharp concentration drop in the oxide during oxidation.

 Contamination sources for mobile ionic charges include the human

body and deionized water, emphasizing the need for strict cleanliness in
fabrication.

Oxidation Techniques and Effects

 Chlorine oxidation can fix mobile ionic charges in oxide layers by

forming sodium chloride and potassium chloride, reducing their detrimental
effect on device performance.

 Chlorine oxidation reduces oxide oxidation induced stacking faults by

creating silicon vacancies at the surface, allowing interstitial silicon atoms to be
absorbed.

 Chlorine oxidation should be used in very small quantities (<10^15/cm^2) to

avoid hogen pitting and severe surface damage.

 TRI chloroethylene (TCE) is a safer alternative to chlorine gas and hydrogen

chloride for chlorine oxidation, as it's a liquid that can be bubbled with oxygen.

Oxidation Processes and Measurements

 Anodic oxidation is a room temperature process for silicon wafer oxidation,

useful for diagnostic purposes like determining doping profile without affecting
it.

 In N-type silicon, light or a large voltage is applied to create holes for anodic
oxidation, as holes are minority carriers.
  Anodic oxide thickness is directly proportional to applied voltage (3 angstroms
per volt), allowing accurate determination of oxide thickness.

 Plasma oxidation uses oxygen plasma instead of liquid electrolyte,

producing better oxide properties than anodic oxidation but still inferior
to thermal oxide.

Oxide Characteristics and Measurements

 Oxide thickness can be estimated by its color,

appearing blue or pink depending on thickness, using silicon
dioxide's refractive index (1.46).

 Capacitance technique measures oxide thickness and evaluates quality by

assessing fixed oxide charge, oxide trap charge, mobile ionic charge,
and interface state density.

Post-Oxidation Processes

 Nitrogen flushing for 15-20 minutes after oxidation removes traces of oxygen,
preventing incomplete oxidation and high density of fixed oxide charges.

 Chlorine oxidation improves carrier lifetime by forming compounds with deep

impurities like gold and platinum, which can negatively impact carrier lifetime.

Fundamental Concepts
 Diffusion is the process of introducing controlled impurities into semiconductors
at high temperatures, governed by concentration gradients and point defects.

 Substitutional impurities like P, As, and Sb are electronically active donors in Si,
replacing host atoms and donating electrons to the conduction band.

 Interstitial C mechanism explains B movement in Si, where the dopant starts

interstitially, displaces a host atom, and occupies a substitutional site.

Diffusion Mechanics
 The diffusion coefficient (D) is expressed as D = d0 * e^(-EA/kT), where EA indicates
the ease of dopant movement within the semiconductor.
 Fick's First Law of diffusion states J = -D(dN/dx), relating flux (J) to the concentration
gradient (dN/dx) and diffusion coefficient (D).

 Interstitial dopants diffuse faster than substitutional ones due to unhindered

movement through interstitial spaces, resulting in higher diffusion coefficients.

Advanced Diffusion Concepts

  Fick's Second Law relates the rate of change in dopant concentration to the second
derivative of the concentration profile and diffusion coefficient.

 In infinite source diffusion, surface concentration remains at the solid solubility limit,
producing a complementary error function profile.

 Junction depth in infinite source diffusion is determined by the intersection of the

complementary error function profile and the background doping concentration.

Practical Applications
 The total amount of impurity introduced during infinite source diffusion depends on
the integral of the doping concentration profile over the crystal volume.

 Diffusion length, given by √(Dt), measures dopant penetration and is crucial in

determining junction depth.

 Interstitial dopants like Li, Na, He, and Ar are donors in Si, moving through interstitial
spaces more rapidly than substitutional dopants.

Diffusion Dynamics
 Junction depth increases with √(DT) while surface concentration decreases
with 1/(√t), illustrating the inverse relationship between depth and concentration over
time.

 The diffusion coefficient D can be modeled as constant or concentration-dependent,

based on the ratio of intrinsic carrier concentration to impurity concentration.

Practical Diffusion Process

 Practical diffusion involves two steps: predeposition (infinite source diffusion)
and drive-in (constant total impurity case), with specific formulas for impurity
amount and surface concentration.

 Junction depth formulas vary based on D's dependence on doping

concentration: 1.616√(Dt) for D∝n, 1.19√(Dt) for D∝n^2, and 0.87√(Dt) for D∝n^3.

Diffusion Coefficient Complexity

 The diffusion coefficient D may have multiple components, including concentration-
independent and concentration-dependent terms, with dominance varying by depth
and doping levels.

 As D's power dependence on doping concentration increases, the junction becomes

shallower and the profile steeper, affecting the overall diffusion characteristics.