Q.

Six-stage Instruction pipeline:

1. Fetch instruction (FI): Read the next expected instruction into a buffer.
2. Decode instruction (DI): Determine the opcode and the operand specifiers.
3. Calculate operands (CO): Calculate the effective address of each source
operand.
4. Fetch operands (FO): Fetch each operand from memory.
5. Execute instruction (EI): Perform the indicated operation.
6. Write operand (WO): Store the result in the specified memory location.
A six-stage pipeline can reduce the execution time for 9 instructions from 54
time units to 14 time units.

Note: For 5-stage instruction pipeline, skip the ‘Calculate operands’ stage.
DEPENDENCIES

 Data Dependence.
 Control Dependence.
 Resource Conflict
DATA DEPENDENCIES
A data dependency is a situation in which
a program statement (instruction) refers to the data
of a preceding statement.
Three cases are exist…

True Data Dependence (flow dependence –

read after write)
Output Dependence (write after write)
Anti Dependence (write after read)
TRUE DATA DEPENDENCY
 True data dependency is where one instruction depends
on the final outcome of a previous instruction.
 Also known as flow dependency or read after write
dependency
 Consider the code:
ADD r1,r2 (r1 =r1+r2;)
MOV r3,r1 (r3 = r1;)
 Can fetch and decode second instruction in parallel
with first
 Can NOT execute second instruction until first is
finished
OUTPUT DEPENDENCY
This type of dependency occurs when two instructions both
write a result.
If an instruction depends on the intermediate result, problems
could occur
Also known as write-write dependency

R3 = R3 + R5; (I1)
R4 = R3 + 1; (I2)
R3 = R5 + 1; (I3)
R7 = R3 + R4; (I4)
I2 depends on result of I1 and I4 depends on result of I3 –
true data dependency
If I3 completes before I1, result from I1 will be written lost –
output (write-write) dependency
 ANTIDEPENDENCY(WRITE AFTER READ)

 Called Antidependency because it is the exact opposite of

data dependency

 Data dependency: instruction 2 depends on data from

instruction 1

 Antidependency: instruction 1 depends on data that could

be destroyed by instruction 2
CONTROL DEPENDENCY

S1. if (a == b)
S2. a = a + b
S3. b = a + b
RESOURCE CONFLICT

 Two or more instructions requiring

access to the same resource at the same
time
-- e.g. functional units, registers, bus
 Similar to true data dependency, but it is
possible to duplicate resources
Q. Pipeline Hazards:
1. A pipeline hazard occurs when some portion of the pipeline is delayed because conditions do not
permit continued execution. It is also referred to as a pipeline bubble.
2. There are three types of hazards: resource, data, and control.
3. Resource hazards:
a. A resource hazard occurs when two (or more) instructions that are already in the pipeline need
the same resource. The result is that the instructions must be executed in serial rather than
parallel for a portion of the pipeline. A resource hazard is sometime referred to as a structural
hazard.
b. Consider an example: assume five-stage pipeline, in which each stage takes one clock cycle and
main memory has a single port so that all instruction fetches and data reads and writes has to be
performed one at a time. In this case, an operand read to or write from memory cannot be
performed in parallel with an instruction fetch. Therefore, the fetch instruction stage of the
pipeline has to be idle for one cycle before beginning the instruction fetch for next instruction.
4. Data hazards:
a. A data hazard occurs when two instructions in a program are to be executed and both access a
particular memory operand. If the two instructions are executed in sequence, no problem
occurs but if the instructions are executed in a pipeline, then the program may produce an
incorrect result because of the use of pipelining.
b. As an example, consider the following instruction sequence:
ADD AX, BX
SUB CX, AX
The first instruction adds the contents of the registers AX and BX and stores the result in AX. The
second instruction uses the contents of AX obtained from first instruction.
c. Thus, in the absence of special hardware and specific avoidance algorithms, such a data hazard
results in inefficient pipeline usage.
d. There are three types of data hazards:
i. Read after write (RAW), or true dependency: A hazard occurs if the read takes place before the
write operation is complete.
ii. Write after read (WAR), or antidependency: A hazard occurs if the write operation completes
before the read operation takes place.
iii. Write after write (WAW), or output dependency: A hazard occurs if the write operations of two
instructions take place in the reverse order of the intended sequence.
5. Control (Branch) hazards:
a. A control hazard occurs when the pipeline makes the wrong decision on a branch prediction and
therefore brings instructions into the pipeline that must subsequently be discarded.
b. A variety of approaches have been taken for dealing with conditional branches:
i. Multiple streams: Replicate initial pipeline stages and allow the pipeline to fetch both instructions,
making use of two streams.
ii. Prefetch branch target: When a conditional branch is recognized, the target of the branch is
prefetched, in addition to the instruction following the branch. This target is then saved until the
branch instruction is executed. If the branch is taken, the target has already been prefetched.
iii. Loop buffer: A loop buffer is a small, very-high-speed memory maintained by the instruction fetch
stage of the pipeline and containing the n most recently fetched instructions, in sequence. If a
branch is to be taken, the next instruction is fetched from the buffer.
iv. Branch prediction: Various techniques can be used to predict whether a branch will be taken.
1. Predict never taken
2. Predict always taken
3. Branch history table, etc.
v. Delayed branch: It is possible to improve pipeline performance by automatically rearranging
instructions within a program, so that branch instructions occur later than actually desired.
Q. Amdahl’s law:

Amdahl’s law was first proposed by Gene Amdahl in 1967 and deals with the
potential speedup of a program using multiple processors compared to a single
processor. Consider a program running on a single processor such that a fraction
(1 - f) of the execution time involves code that is inherently sequential, and a
fraction f that involves code that is infinitely parallelizable with no scheduling
overhead. Let T be the total execution time of the program using a single
processor. Then the speedup using a parallel processor with N processors that
fully exploits the parallel portion of the program is as follows:

Speedup = Time to execute program on a single processor/Time to execute

program on N parallel processors

Amdahl’s law can be generalized to evaluate any design or technical improvement

in a computer system. Consider any enhancement to a feature of a system that
results in a speedup. The speedup can be expressed as

Speedup = Performance after enhancement/Performance before enhancement

Suppose that a feature of the system is used during execution a fraction of the
time f, before enhancement, and that the speedup of that feature after
enhancement is SUf. Then the overall speedup of the system is
Introduction
• Multi-core processors represent a major
evolution in computing technology.

•They are several mostly independent cores

which work together in parallel

•This important development is coming at a time

when businesses and consumers are require it
benefits offered by these processors due to the
exponential growth of digital data and the
globalization of the Internet.

•performance and productivity benefits beyond the

capabilities of today’s single-core processors.
History
•The first commercial dual core processor was
IBM's Power 4 processor for it's RISC servers in
2001.

•The first dual core processor for home use was

Intel's Pentium Processor Extreme Edition 840,
released in early April 2005.

•Less than two weeks later AMD brought their

Opteron 800 Series and Athlon 64 X2
processors to market.
Why multi-core pocessor-?
Once upon a time, when human realized that
in a normal atmosphere ,it is not possible to
increase the CPU’s clock speed after above
standard level (generally at a frequency about
4Ghz the CPU would get too hot and take a
lot of electricity). Because of too much heat
generated by CPU both Intel & AMD faced
problem. High clock speed means high heat
& resulted boom the CPU.
 Faster processing is the basic reason ,so
that’s why technology shifted towards the
Multicore processor rather than increase the
clock frequency. It was decided to put more
than one processor on a single die. That is
what we call two core or dual core .
What do you mean by Multi core?
•A multi-core microprocessor is one which combines
two or more independent processors into a single
package, often a single integrated circuit.
•A dual core device
contains only two
independent
microprocessors.
If multi means two or more, what types are
there?
A dual-core A quad-core
processor processor
contains two contains four
cores. cores.

A processor with all cores on a

single die is called a monolithic
processor.
Multi core architecture
Comparison of Different Architectures

CPU State

Execution
unit Cache

Single Core
Architecture

11
Comparison of Different Architectures

CPU State CPU State

Execution Execution
unit Cache Cache
unit

Multiprocessor
Comparison of Different Architectures

CPU State CPU State

Execution
unit Cache

Hyper-Threading Technology

13
Comparison of Different Architectures

CPUa State CPU State

Execution Execution
unit Cache unit Cache

Multi-Core Architecture

14
Comparison of Different Architectures

CPU State CPU State

Execution Execution
unit unit

Cache

Multi-Core Architecture with Shared Cache

15
Comparison of Different Architectures

CPU State CPU State CPU State CPU State

Execution Execution
unit Cache unit Cache

Multi-Core with Hyper-Threading Technology

16
Threading & Non-threading
technology
Single Core vs. Multicore
Performance Analysis
Advantages

•Multi-tasking productivity

• it will work faster for certain programs

•PC security

•Cool and quiet

•The signals between different CPUs travel shorter

distances, therefore they degrade less

•More features can be added to the computer

Disadvantages

•They do not work at twice the speed as a normal

processor. They get only 60-80% more speed.

•The speed that the computer works at depends on

what the user is doing with it.

•They cost more than single core processors.

•They are more difficult to manage thermally than

lower-density single-core processors.
Applications

• Video editing
• Encoding .
• 3D gaming.
• Powerful graphics solution
•Optimized productivity titles, such as
AVG's virus-scanning software.

The full effect and the advantage of having

a multi-core processor, when it is used
together with a multithreading operating .
Multicore Challenges

Having multiple cores on a single chip gives some

challenges .

• Power and temperature management

• Memory/cache coherence is another challenge

•And finally, using a multicore processor to its full

potential is another issue