SLG4CG47815

GreenPAK ™
LTC2930 replacement

General Description Pin Configuration

Renesas SLG4CG47815 is a low power and small form
24 23 22 21 20 19
device. The SoC is housed in a 3mm x 3mm STQFN
package which is optimal for using with small devices.
1 18

Features
2 17
• Low Power Consumption
• RoHS Compliant / Halogen-Free
• 24-pin STQFN: 3.0 mm x 3.0 mm x 0.55 mm, 0.4 mm 3 16
Pitch
4 15

Output Summary 5 14
4 Outputs - 3-State Output 1X
8 Outputs - Analog Input/Output
6 13
1 Output - Open Drain NMOS 1X
7 8 9 10 11 12

ST FN 24
Top ie

Pin Name
Pin # Pin name Pin # Pin name
1 NC 13 NC
2 V2 14 NC
3 V1 15 GND
4 VDDA 16 VDD
5 NC 17 NC
6 NC 18 V6
7 PIN 7 19 V4
8 PIN 8 20 V5
9 PIN 9 21 NC
10 PIN 10 22 NC
11 PIN 11 23 PIN 23
12 PIN 12 24 V3

SLG4CG47815_DS_r011 Rev 0.11

SLG4CG47815_GP_r002 Preliminary Revised 06/25/2024
 SLG4CG47815
LTC2930 replacement

Block Diagram

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 SLG4CG47815
LTC2930 replacement

Pin Configuration
Pin Pin Name Type Pin Description Internal Resistors
1 NC -- Keep Floating or connect to GND --
2 V2 Analog Input/Output Analog input / 1x 3-State Output floating
3 V1 Analog Input/Output Analog input / 1x 3-State Output floating
4 VDDA PWR Supply Voltage --
5 NC -- Keep Floating or connect to GND --
6 NC -- Keep Floating or connect to GND --
7 PIN 7 Analog Input/Output Analog input/output / Analog input/output floating
8 PIN 8 Analog Input/Output Analog input/output / Analog input/output floating
9 PIN 9 Analog Input/Output Analog input/output / Analog input/output floating
10 PIN 10 Analog Input/Output Analog input/output / Analog input/output floating
11 PIN 11 Analog Input/Output Analog input/output / Analog input/output floating
12 PIN 12 Analog Input/Output Analog input/output / Analog input/output floating
13 NC -- Keep Floating or connect to GND --
14 NC -- Keep Floating or connect to GND --
15 GND GND Ground --
16 VDD PWR Supply Voltage --
17 NC -- Keep Floating or connect to GND --
18 V6 Analog Input/Output Analog input/output / Analog input/output floating
19 V4 Analog Input/Output Analog input / 1x 3-State Output floating
20 V5 Analog Input/Output Analog input/output / Analog input/output floating
21 NC -- Keep Floating or connect to GND --
22 NC -- Keep Floating or connect to GND --
23 PIN 23 Digital Output Open Drain NMOS 1X floating
24 V3 Analog Input/Output Analog input / 1x 3-State Output floating

Ordering Information
Part number Type
SLG4CG47815 24-pin STQFN - Tape and Reel (TBD units)

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 SLG4CG47815
LTC2930 replacement

Absolute Maximum Conditions

Parameter Min Max Unit
VDD and VDDA Voltage to GND -0.5 7.0 V
GPI0, GPIOs 0, 1, 2, 3, 4, VDD + 0.5,
-0.5
5, 6, 7, 8, 9 up to 7.0
OA0+, OA0-, OA0_OUT,
OA1+, OA1-, OA1_OUT,
DC Input Voltage V
RH0_A/GPI1, VDDA + 0.5,
-0.5
RH0_B/GPI2, up to 7.0
RH1_A/GPI4,
RH1_B/GPI3
VDD DC Current -- 90 mA
VDDA DC Current -- 180 mA
GND DC Current -- 145 mA
Push-Pull 1x -- 12
GPIO DC Current OD 1x -- 12 mA
Analog Switch Mode -- 130
Logic Input Pin Current -- 1 mA
Input Leakage Current -- 1 μA
Storage Temperature Range -65 +150 °C
Junction Temperature -- +150 °C
ESD Protection (Human Body Model) 2000 -- V
ESD Protection (Charged Device Model) 1300 -- V
Moisture Sensitive Level 1

Electrical Characteristics
Symbol Parameter Condition Min Typ Max Unit
VDD VDD Supply Voltage Range 3 3.3 3.6 V
VDDA VDDA Supply Voltage Range 3 3.3 3.6 V
Operating Ambient
TA -40 25 85 °C
Temperature Range
Input Capacitor at VDD and
CVDD 0.1 -- -- µF
VDDA Pins
CIN Input Capacitance -- 4 -- pF
IQ Quiescent Current Static inputs and floating outputs -- 40 -- μA
Maximal Voltage Applied to
VO any Pin in High Impedance TBD TBD TBD V
State
Push-Pull 1X, VDD = 3.3 V ± 10 %, IOH
VOH HIGH-level Output Voltage 3.04 -- -- V
= 3 mA
Push-Pull 1X, VDD = 3.3 V ± 10 %, IOL
-- -- 0.195 V
= 3 mA
VOL LOW-level Output Voltage
Open Drain NMOS 1X, VDD = 3.3 V ±
-- -- 0.088 V
10 %, IOL = 3 mA

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 SLG4CG47815
LTC2930 replacement

HIGH-level Output Pulse Push-Pull 1X, VDD = 3.3 V ± 10 %,

IOH 8.01 -- -- mA
Current VOH = 2.4 V
Push-Pull 1X, VDD = 3.3 V ± 10 %,
5.87 -- -- mA
LOW-level Output Pulse VOL = 0.4 V
IOL
Current Open Drain NMOS 1X, VDD = 3.3 V ±
14.22 -- -- mA
10 %, VOL = 0.4 V
tSU Startup Time From VDD rising past VTH_PON -- 2.5 6.3 ms
VTH_PON Power-on Threshold VDD required to start up the device 1.62 1.84 2.05 V
VTH_POFF Power-off Threshold VDD to turn off the device 1.02 1.34 1.60 V
Note 1: No hysteresis.

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 SLG4CG47815
LTC2930 replacement

Package Top Marking

Datasheet Programming Lock

Checksum Part Code Revision Date
revision Code Number Status
0.11 002 U 0xEB307765 06/25/2024

Memory Lock Options

Option Status
Registers Unlocked

The IC security bit is locked/set for code security for production unless otherwise specified. The
Programming Code Number is not changed based on the choice of locked vs. unlocked status.

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 SLG4CG47815
LTC2930 replacement

Package Dra ing and Dimensions

ST FN 24 3.0 mm x 3.0 mm x 0.55 mm, 0.4 mm Pitch WB

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 SLG4CG47815
LTC2930 replacement

Tape and Reel Specifications

Max Units Reel & Leader min Trailer min
Nominal Tape Part
Package # of Hub
Package Length Length Width Pitch
Type Pins per Reel per Box Size Pockets Pockets
Size mm mm mm mm mm
mm
STQFN- 3.0 x 3.0 x
24 TBD TBD 330/102 100 400 100 400 12.5 8.0
24 0.55

Carrier Tape Dra ing and Dimensions

Index Index
Pocket Pocket Index Index
Pocket Pocket Hole to Hole to Tape
BTM BTM Hole Hole
Package Depth Pitch Tape Pocket Width
Length Width Pitch Diameter
Type mm mm Edge Center mm
mm mm mm mm
mm mm
A0 B0 K0 P0 P1 D0 E F W
STQFN- 0.75 ± 1.5 +0.1 / 12.15 ±
3.3 ± 0.1 3.3 ± 0.1 4.0 ± 0.1 4.0 ± 0.1 1.75 ± 0.1 5.5 ± 0.05
24 0.05 -0.0 0.1

Recommended Reflo Soldering Profile

Refer to the IPC/JEDEC standard J-STD-020 for relevant soldering information. This document can be downloaded from
[Link]

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 SLG4CG47815
LTC2930 replacement

Layout Consideration
The SLG4CG47815 has two supply input pins (VDD and VDDA) and one ground pin (GND) as analog and digital ground
signals are internally connected. Separating the analog supply voltage (V DDA) from the digital supply (VDD) helps to
minimize cross-coupling of noise generated by the digital part of the device.

■ Analog (VDDA) Domain: Operational Amplifiers, bias generators (for VREF of OpAmp and MS-ACMP), VREF of OpAmp,
digital rheostats, and low-power bandgap.
■ Digital (VDD) Domain: MS-ACMP (Chopper ACMP), VREF of MS-ACMP, TS_OUT buffer, sink/source buffer, analog
switch, OSC0 (2 kHz/10 kHz), OSC1 (25 MHz), I2C macrocell, the NVM logic, multi-function macrocells, and
combination-function macrocells.

It is strongly recommended to connect unused digital input pins to GND.

The following suggestions allow to minimize the impacts of the digital domain noise onto the analog domain:

■ Decrease the slew-rate of digital input signals if possible.

■ Use proper grounding scheme with bypass capacitors on VDDA and VDD pins.
■ Assign GPIO0 – GPIO9 for digital signals first, then use other pins in case more digital IOs are needed.

PCB Layout Example

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 SLG4CG47815
LTC2930 replacement

Recommended Land Pattern

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 SLG4CG47815
LTC2930 replacement

Datasheet Revision History

Date ersion Change
06/19/2024 0.10 New Design
06/25/2024 0.1 Change vref to 512mV

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