Fall Semester 2025-26
Digital System Design With FPGA Lab
Report
Task -2
Digital System Design with FPGA lab
Name: SIVANANDHAM K
Reg No:25MVD0145
AIM:
PROCEDURE:
STATE DIAGRAM:
STATE TABLE:
VERILOG CODE:
a) Behavioral modeling
module fsm(
input in,
input clk,
input rst,
output reg y,
output [6:0] seg1,
output [6:0] seg2
);
parameter two = 4'b0001,
five1 = 4'b0010,
n = 4'b0011,
v = 4'b0100,
d = 4'b0101,
zero = 4'b0110,
one = 4'b0111,
four = 4'b1000,
five2 = 4'b1001,
ideal = 4'b0000;
reg [3:0] current, next;
// Sequential block
always @(posedge clk) begin
if (rst)
current <= ideal;
else
current <= next;
end
// Next state logic
always @(*) begin
next = current;
case(current)
ideal : next = in ? two : ideal;
two : next = in ? five1 : ideal;
five1 : next = in ? n : ideal;
n : next = in ? v : ideal;
v : next = in ? d : ideal;
d : next = in ? zero : ideal;
zero : next = in ? one : ideal;
one : next = in ? four : ideal;
four : next = in ? five2 : ideal;
five2 : next = in ? two : ideal;
default: next = ideal;
endcase
end
// Module instantiations — OUTSIDE always blocks
seven seven_seg1 (.in(current), .seg(seg1));
seven seven_seg2 (.in(current), .seg(seg2));
always @(*) begin
y = (current == five2); // example: output 'y' goes high when in state five2
end
endmodule
module seven(
input [3:0] in,
output reg [6:0] seg
);
always @(*) begin
case (in)
4'b0000: seg = 7'b000_000_0; // 0
4'b0001: seg = 7'b111_000_0; // 2
4'b0010: seg = 7'b101_101_1; // 5
4'b0011: seg = 7'b111_011_0; // n
4'b0100: seg = 7'b011_111_0; // v
4'b0101: seg = 7'b111_111_0; // d
4'b0110: seg = 7'b111_111_0; // 0
4'b0111: seg = 7'b011_000_0; // 1
4'b1000: seg = 7'b011_001_1; // 4
4'b1001: seg = 7'b101_101_1; // 5
default: seg = 7'b000_000_0; // Default 0
endcase
end
endmodule
b) Dataflow
module seqckt(input clk, rst,output y,
output [6:0] seg1,
output [6:0] seg2);
reg a,b,c,d,e;
wire d0,d1,d2,d3,d4;
always @ (posedge clk)
if (rst ==1)
begin
a<=0;
b<=0;
c<=0;
d<=1;
e<=0;
end
else
begin
a<=d0;
b<=d1;
c<=d2;
d<=d3;
e<=d4;
end
assign d0 = c&(~e);
assign d1 = (b&(~c))| ((~a)&(~b)&(c)&e);
assign d2 = ((~c)&e) | ((~b)&d) | (c&(~e));
assign d3 = (b&(~e)) | ((~b)&c&e);
assign d4 = (~e) | d;
assign y = {a,b,c,d,e}
seven seven_seg1 (.in(y), .seg(seg1));
seven seven_seg2 (.in(y), .seg(seg2));
endmodule
module seven(
input [4:0] in,
output reg [6:0] seg
);
always @(*) begin
case (in)
5'b10000: seg = 7'b111_111_1; // 0
5'b00010: seg = 7'b001_001_0; // 2
5'b00101: seg = 7'b010_010_0; // 5
5'b01010: seg = 7'b000_100_1; // n
5'b01011: seg = 7'b100_000_1; // v
5'b01101: seg = 7'b100_001_0; // d
5'b00000: seg = 7'b000_000_1; // 0
5'b00001: seg = 7'b100_111_1; // 1
5'b00100: seg = 7'b100_110_0; // 4
5'b10101: seg = 7'b010_010_0; // 5
default: seg = 7'b000_000_0; // Default 0
endcase
end
endmodule
FPGA OUTPUT:
CONCLUSION:
The FSM was designed and implemented to display my register number 25MVD0145
on the seven-segment display. It works like a counter, moving from one state to the next to
show each digit/character in sequence. The experiment shows that FSMs can be used
effectively to control displays in digital circuits.