Experiment No: 04
Experiment Name: Design and Verification of a 4-Bit
Parity Generator and Parity Checker.
Objectives:
1. To develop and verify the operation of a 4-bit Parity Generator using
XOR gates.
2. To construct and test a 4-bit Parity Checker using XOR gates.
3. To gain an understanding of the concept of parity in error detection and
correction mechanisms.
Description:
1. Parity Concept: Parity is an error-detection technique used in digital systems. It involves
adding an additional parity bit to a binary message to ensure the total count of 1s in the
message (including the parity bit) adheres to a predefined rule.
Types of Parity:
Even Parity: The total count of 1s (including the parity bit) is even.
Odd Parity: The total count of 1s (including the parity bit) is odd.
2. 4-Bit Parity Generator: A Parity Generator is responsible for creating a parity bit based
on input data to maintain the required parity type (even or odd).
Boolean Expression for Even Parity Bit: P = A ⊕ B ⊕ C ⊕ D where A, B, C, and D are the four
input bits, and P is the generated parity bit.
Truth Table for Parity Generator:
A B C D Parity Bit (P) (Even
Parity)
0 0 0 0 0
0 0 0 1 1
0 0 1 0 1
0 0 1 1 0
0 1 0 0 1
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 0
1 0 1 1 1
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
3. 4-Bit Parity Checker:
A Parity Checker is used to verify received data by checking whether the
parity condition is met. If there is a mismatch, an error is detected.
Boolean Expression for Even Parity Checker: Error = A ⊕ B ⊕ C ⊕ D ⊕ P
Boolean Expression for Even Parity Checker:
Error=A⊕B⊕C⊕D⊕P
Truth Table for Parity Checker (Even Parity):
Error (A ⊕ B ⊕ C ⊕ D
⊕ P)
B P (Received
A C D Parity Bit)
0 0 0 0 0 0
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 0
0 1 0 0 1 0
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 0
1 0 1 0 0 0
1 0 1 1 1 0
1 1 0 0 0 0
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 0
If Error = 1, it means an error is detected in the received data.
Materials Used:
Breadboard
ICs (7486 for XOR gates)
LEDs (to display output)
Connecting wires
Power supply (5V)
Input switches.
Procedure:
The circuits were designed and built starting with the
Parity Generator, where XOR gates were used to generate
the parity bit based on the input values. Next, the Parity
Checker was constructed using XOR gates to verify the
received data and detect potential errors. Binary inputs
(A, B, C, D, and P) were applied using logic switches,
while LEDs were used to indicate the presence of errors.
Various input combinations were tested, and the outputs
were compared against theoretical results to validate
accuracy.
Figure:
Figure 1: 4-bit-even-parity-
generator.
Figure 2 : 4-bit Parity Checker
Conclusion:
This experiment successfully demonstrated the design and functionality of
the 4-bit Parity Generator and Parity Checker. The Parity Generator
effectively calculated the correct parity bit for all possible input
combinations, ensuring even parity. Similarly, the Parity Checker accurately
detected errors by verifying the computed parity bit against the received
one.
Minor discrepancies caused by wiring issues were resolved during the
experiment. This study emphasized the importance of parity in error
detection and its significance in ensuring reliable digital communication
systems.