Fr. Conceicao College of Engineering, Bandra(W).

Module:1 8The Intel Microprocessor 8086 Architecture

Memory Banking

* Microprocessors 1
 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture
• In any processor , there is memory. This memory is stored in locations. Each
location can hold one byte( 8-bits ) of data. Memory banking in 8086 is ,
having divided the memory into two banks ( two parts ).
• Why can one location store only one byte?
Minimum byte operation needs 1 byte. So it is preferred to assign minimum
memory to one location, so that memory is not wasted.
If each location can hold 2 bytes( 16-bits ) of memory,
• When processor performs 16-bit operations it is good
• But when the processor performs 8-bit operation, then the remaining 8 bits
are wasted.
• Even if it is a 64-bit intel processor, each location can hold 8 bits of memory
only.
• Whenever 16-bit data is stored in locations, it is stored in two consecutive
memory locations, lower byte is stored in lower address and higher byte is
stored in higher address. This concept of lower byte lower location, higher
byte in higher location is known as little Endian rule.
• If each location can store 8-bits how can the processor perform 16-bit
operation?
• By memory banking.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture
• Memory Banking:
• Here we shall consider an 8086 processor which can hold 1MB of memory
due to its 20 address lines ( 220 = 1MB ) So this 1MB memory is divided
into two parts ( two banks ), where one bank consists of all even addresses
and the other bank consists of odd addresses.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture
• Purpose of memory banking:
• As the 16-bit data is stored in 2 locations, lower byte in lower address and
upper byte in next consecutive address location.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture
• The data stored here is 1345H. This is representation of data in
hexadecimal form. So whenever the processor needs to fetch this , it first
gives the address to the address bus and fetches 45H and then it gives the
next address, then it fetches 13H. So overall a 16-bit processor needs 2
cycles to perform a 16-bit operation, which is completely a wrong concept.
This thing led to memory banking.
• If the memory can be divided into two parts, with some algorithm, two
8-bit datas can be fetched in one cycle.
• As Even bank starts from 00000H and goes up to FFFFEH , it stores the
lower byte so also known as lower bank. Odd bank locations start from
00001H and go upto FFFFFH , this stores higher byte , thus also known
as Higher bank in 8086.
• How does banking work?
• There are totally 20 address lines in 8086, that can access the locations.
Each location is decided by these 20 address lines ( A0 , A1 ……. A19 ).

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture

• If observed, for every consecutive location starting from even location, there
is only change in address ( A0 is only different ).
• For Eg:
• Locations 0H and 1H are consecutive and have the same address except A0.
• Locations 3H and 4H are consecutive but their addresses don’t have that
similarity.
• Aligned data:
• Locations 0H and 1H is the example of aligned data. 8086 can fetch this type of
data in one cycle.
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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 8The Intel Microprocessor 8086 Architecture
• Misaligned data:
• Locations 3H and 4H are the example of misaligned data, 8086
needs 2 cycles to fetch this type of data.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 The Intel Microprocessor 8086 Architecture
• Now we would learn how we can access 16-bit aligned data in one cycle.
• If A0 address line is discarded, 8086 sends a 19-bit address, there are two
locations, one location in higher bank and other location in lower with the
same address, in this way 8086 can fetch 16 bit data in one cycle. But if
A0 is always discarded, 8086 can only perform 16-bit operations, and
cannot perform 8-bit operations.
• So we need that
• 8086 can be able to select lower bank only for 8-bit operations.
• 8086 can be able to select higher bank only for 8-bit operations.
• 8086 can be able to select both banks at single time for 16-bit operations.
• Then BHE, comes into picture. It stands for bus high enable or bank high
enable, and it is pronounced as BHE bar.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 The Intel Microprocessor 8086 Architecture

BHE bar is connected to the active low of the higher bank and A0 is connected
to the active low of lower bank.
Whenever A0 = 0, lower bank is selected
And if A0 = 1, lower bank is not selected
A0 has nothing to do with higher bank
Whenever BHE = 0, lower bank is selected
And if BHE = 1, lower bank is not selected
BHE has nothing to do with lower bank

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 The Intel Microprocessor 8086 Architecture
BHE A0 Mode
Both the banks are selected and 8086 performs
0 0
16-bit operations.
Higher bank is selected and 8086 performs 8-bit
0 1
operations with higher bank memory only.
Lower bank is selected and 8086 performs 8-bit
1 0
operations with Lower bank memory only.
Both the banks are discarded and 8086 is in idle
1 1
mode.

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 Peripheral interfacing and Memory interfacing

Memory Interfacing

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:1 Peripheral interfacing and Memory interfacing
Design a 8086 system for the following specification.
32 k bytes ROM using 16k and 128k RAM using 32k.

No. of EPROM Chips required : Required size / available = 32k /16k =2

No. of RAM Chips required : Requried size / available = 128k /32k =4

Now starting address of ROM = FFFFFH – 7FFFH = F8000H

No. of Address lines in EPROM is available size 16Kb = 24 X 210
= 214
Hence 14 address lines are required = A1 - A14

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• Ram and ROM are always placed in the total 1MB of memory.
Hence we RAM is always placed in the beginning
And ROM is always placed in the END.

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No. of Address lines in RAM is available size 32Kb = 25 X 210
= 215
Hence 15 address lines are required = A1 - A15

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A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

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Bank A A A A A A A A A A A A A A A A A A A A Address
1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
Begin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
END(E 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0FFFEH
VEN)
Begin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H
End 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0FFFFH
(odd)
Begin 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10000H
END(E 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1FFFEH
VEN)
Begin 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 10001H
End 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFFH
(odd)
ROM 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F8000H
EVEN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH
Begin 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F8001H
ODD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH
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* Microprocessors 17
 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I

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* Microprocessors 19
 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I

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21
 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I
2) Design a system with following specifications:
32K EPROM with 8K and 32K Ram with 8k
Solution:
No. of EPROM Chips required : Required size / available = 32k /8k =4
No. of RAM Chips required : Requried size / available = 32k /8k =4

No. of Address lines in EPROM is available size 8Kb = 23 X 210

= 213
Hence 13 address lines are required = A1 - A13

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I

Hence 13 address lines are required = A1 - A13

A A A A A A A A A A A A A A A A A A A A
19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Span of chip 03FFFH

Now starting address of ROM = FFFFFH – 03FFFH = FC000H

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 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I
Since there are 4 Chips the ENDing address of the next chip will be one
location above the starting address of the first chip

i.e we
FBFFFFH Hence the starting address will be FBFFFH
FC000H - 03FFFH
FFFFFH F8000H

Therefore we have 2 sets consisting of 4 chips

With start Address : F8000H END Address: FBFFFH one SET
With start Address : FC000H END Address: FFFFFH second SET

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Bank A A A A A A A A A A A A A A A A A A A A Address
1 1 Fr.
1 1Conceicao
1 1 1 1College
1 1 9of Engineering,
8 7 6 5 4 Bandra(W).
3 2 1 0
9 8 7 6 5 4 3 2 1 0
Module:3 8086 Interfacing Part-I
Begin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H
END(E 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 03FFEH
VEN)
Begin 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H
End 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 03FFFH
(odd)
Begin 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 04000H
END(E 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 07FFEH
VEN)
Begin 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 04001H
End 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 07FFFH
(odd)
ROM 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F8000H
EVEN 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FBFFEH
Begin 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F8001H
ODD 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FBFFFH
* Microprocessors 25
 Fr. Conceicao College of Engineering, Bandra(W).
Module:3 8086 Interfacing Part-I

Bank A A A A A A A A A A A A A A A A A A A A Address
1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
9 8 7 6 5 4 3 2 1 0
ROM( 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC000H
even)
begin
end 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH
ROM( 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FC001H
even)
begin
end 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH

* Microprocessors 26