Depletion-mode SiC VJFET Simplifies High Voltage SMPS

Nigel Springett, Robin Schrader, and Jeff Casady

SemiSouth Laboratories, Inc.
201 Research Blvd.
Starkville, MS, USA

1.4 Wide Bandgap Devices (Silicon Carbide)

Preferred Presentation Form: Oral Presentation

Abstract
High voltage SMPS start-up circuits required for digital control and gate driver circuits
can be composed of several lossy discrete components. To address this, the new 1700 V,
1.4 Ω depletion-mode SiC VJFET, used in a cascode configuration, will demonstrate two
operating roles in an SMPS. First the JFET will supply controller/IC start-up current to
eliminate additional start-up circuitry as well as perform as the main switching element of the
SMPS. This dual role will save space, decrease system cost, and allow for higher system
efficiency. The full manuscript will detail both operating roles complimented with schematics
and experimental results.

Synopsis
The 1700 V enhancement-mode SiC JFET has already demonstrated efficiency
improvements as the power switch in auxiliary Flyback converters [1]. The 1200 V depletion-
mode SiC JFET has also demonstrated efficient switching performance when used in a
cascode configuration [2]. Though, the need for efficient power switches is only one focus for
new power supply designs. Start-up or ‘kick start’ circuits for high voltage power supplies
can prove to be challenging to designers as these circuits are required to interface with high
voltages, sometimes >1000V, supplying start-up current to +5 to +15 V IC’s in digital control
or gate driver circuitry. These start-up circuits maybe be composed of a single resistor or
could require a combination of high voltage passive and active components when very fast
start-up conditions are necessary. The use of start-up circuit costs add the total board
space, have associate power losses, and require added attention to ensure reliability in the
event of a potential fault condition, overload condition, etc. Also, the lack of suitable high
voltage components creates extra complication usually requiring multiple components to
share the voltage. With the introduction of the new 1700 V, 1.4 Ω SiC depletion-mode
VJFET a solution exists that can solve these concerns with reduced part count. There exist
well known circuits using depletion-mode MOSFETs as a current source to deliver start-up
current to control/IC/gate drive circuits [3]. After start-up the MOSFET, like other start-up
methods, no longer functions once auxiliary supplies take control during continuous
operation. The depletion-mode JFET can be used much the same way to initially supply the
start-up current to a control IC. However, once the auxiliary supply takes over powering the
low voltage circuit the JFET does not have to be biased off during continuous converter
operation and can be used to provide a second functionality. Once the control IC has
enough voltage for start-up it begins driving the gate of a low voltage MOSFET that is
connected in a cascode configuration with the depletion-mode JFET used to supply the start-
up current for the IC. The cascode pair will then act as the main power switch for the power
converter. This dual purpose cascode combines the advantages the cascode as an efficient
power switch with the use of a depletion-mode JFET as an efficient self-biasing start-up
current source. Fig. 1 shows a power converter with a commonly used start-up approach,
similar to the approach documented by IXYS [3]. Fig. 2 shows the cascode with integrated
start-up feature. The MOSFET used in the cascode is a small device with 30 V - 40 V rating,
approximate RDS(ON) of 50 mΩ in a low cost, low power SMD package. Resistor R1 provides
extra bias to lift the gate voltage of the JFET above zero for enhanced forward conduction
performance. The JFET gate voltage is clamped by the Zener diode reference to the
MOSFET source terminal. Resistor R2 supplies the bias current to the control IC, lifting the
supply voltage above the UVLO thus turning on the IC as shown in Fig. 3. Normal operation
is shown in Fig. 4 with the gate voltage of the JFET at approximately +10 V, the drain of the
MOSFET (source of the JFET) at approximately +15 V, and the aux supply at approximately
+13 V. The supply power required by PWM controller is now delivered by the auxiliary
winding on the circuit’s main power transformer. This means that under normal continuous
operating conditions for the power converter, no current will flow through R1, and thus the
start-up components have no impact on total system efficiency. By varying the value of R2,
the start-up time can be selected. This adjustment will be independent of input voltage, as
the input voltage does not affect the current through R2. For the circuit in Fig. 1, if a fault
condition is experienced the power dissipation in the MOSFET will increase as it supplies the
start-up current to the control IC. This means that the MOSFET could require a heatsink to
prevent failure if such potential condition occurs. For the dual purpose cascode approach,
the JFET will likely already have a small heatsink installed for normal power switch operation
and thus no extra parts would be required. R1 can also be used to help with discharging the
input bulk energy storage capacitors after shut down as the current will continue to flow even
after the PWM stops running.
Figure 1. Power supply with conventional Figure 2. Power supply with dual purpose
start-up and auxiliary power circuit. cascode supplying the IC start-up current.

Figure 3. Start-up waveforms for the circuit Figure 4. Steady state operation of the
shown in Fig. 2. Ch1 - VDS, Ch2 - JFET gate, cascode in Fig. 2. Ch1 - VDS, Ch2 - JFET
Ch3 - JFET source, Ch4 - aux on control IC. gate, Ch3 - JFET source, Ch4 - aux on
control IC.
Conclusion
By using the depletion-mode JFET of the cascode as a current source for the start-up
conditions of a digital logic or gate driver IC, extra components needed for separate start-up
circuit can be eliminated with no negative effects on the performance of cascode. This will
not only reduce the overall space required for PCB layout, but also improve system efficiency.
Improved converter efficiency along with a detailed explanation of both operating roles of the
1700 V, 1.4 Ω depletion-mode SiC JFET will be discussed with full schematics and
experimental results in the final paper.

References
[1] R. Kelley et al, “1700 V Enhancement-mode SiC VJFET for High Voltage Auxiliary
Flyback SMPS,” Conf. Proc. of PCIM 2010.
[2] N. Springett, “Capacitor Clamped Cascode: normally on SiC JFETs Operate as a
Synchronous Rectifier,” Conf. Proc. of PCIM 2010.
[3] Application Note AN2528 Rev 1, “Very wide input voltage range 6 W SMPS for mete
ring,” July 2007. Available <[Link]>

Biography
Nigel Springett. After graduating from Leicester University, has been designing power
supplies for over 25 years including 15 years in pre-development looking at new topologies
and components. Having designed using most major topologies including Forward, Flyback
Active-clamp, Cuk, Phase Shift Bridge and LLC; he particularly enjoys finding the optimum
solution for the application. This is done through detailed understanding of the trade-offs
needed between cost and performance. Since working with Semisouth he has been
investigating the cascoded JFET and its various applications. In his spare time he enjoys
skiing, water sports and singing