USOO7705647B2

(12) United States Patent (10) Patent No.: US 7,705,647 B2

Dai et al. (45) Date of Patent: Apr. 27, 2010
(54) DUTY CYCLE CORRECTION CIRCUIT 6,654,900 B1 1 1/2003 Cave
6,680,637 B2 1/2004 Seo
(75) Inventors: Liang Dai, Carlsbad, CA (US); Lam V. 6,683,494 B2* 1/2004 Stanley ........................ 330, 10
Nguyen, Cupertino, CA (US) 6,967,514 B2 * 1 1/2005 Kizer et al. ................. 327/175
7,202,722 B2 4/2007 Mahadevan et al.
(73) Assignee: QUALCOMM Incorporated, San 2005/0285649 A1* 12/2005 Chun et al. ................. 327/172
Diego, CA (US) 2006/0028256 A1 2/2006 Nam et al. .................. 327/172

(*) Notice: Subject to any disclaimer, the term of this OTHER PUBLICATIONS
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days. International Search Report - PCT/US07/069883, International
Search Authority - European Patent Office - Feb. 5, 2008.
(21) Appl. No.: 11/454,426 * cited by examiner
(22) Filed: Jun. 14, 2006 Primary Examiner Cassandra Cox
(74) Attorney, Agent, or Firm Jiayu Xu
(65) Prior Publication Data
US 2007/0290730 A1 Dec. 20, 2007 (57) ABSTRACT
(51) Int. Cl. A duty cycle correction circuit capable of generating a clock
HO3K 3/07 (2006.01) signal having good (e.g., approximately 50%) duty cycle is
(52) U.S. Cl. ....................................... 327/175; 327/170 described. The duty cycle correction circuit includes a clock
(58) Field of Classification Search ....................... None deskew circuit and a duty cycle detection circuit. The clock
See application file for complete search history. deskew circuit receives an input clock signal that may have
poor duty cycle, adjusts the input clock signal based on a
(56) References Cited control, and provides an output clock signal having an adjust
U.S. PATENT DOCUMENTS able duty cycle. The duty cycle detection circuit detects error
in the duty cycle of the output clock signal and generates the
5,896,053 A * 4, 1999 Prentice ...................... 327/255 control in response to the detected error in the duty cycle. The
5.945,862 A * 8/1999 Donnelly et al. ............ 327/278 clock deskew circuit and the duty cycle detection circuit
6,084,452. A * 7/2000 Drost et al. ................. 327/175 implement a feedback loop that senses error in the duty cycle
6,198.322 B1 3, 2001 Yoshimura of the output clock signal and feeds back the control to correct
6,320,438 B1 * 1 1/2001 Arcus ......................... 327/175 the duty cycle error.
6,456,133 B1 9, 2002 Nair et al.
6,501,313 B2 * 12/2002 Boerstler et al. ............ 327/175
6,542,015 B2 4/2003 Zhou et al. 18 Claims, 7 Drawing Sheets
W

130
Vod
140
620 e
lcp

216 250
CKoutp
S2D CKoutin
Control Pct
Converter CKoutp Generator NCtrl
CKoutin

CKout 632
U.S. Patent Apr. 27, 2010 Sheet 1 of 7 US 7,705,647 B2

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00||
U.S. Patent US 7,705,647 B2
U.S. Patent Apr. 27, 2010 Sheet 4 of 7 US 7,705,647 B2

do|
08;

09%
U.S. Patent Apr. 27, 2010 Sheet 5 Of 7 US 7,705,647 B2

DD

Pct
512

CKoutn
Converter CKoutp

CKout

140C
620 -1

250
CKoutp
Control PCtrl
Generator NCtrl
CKOutn

C1

ef F.G. 6
U.S. Patent Apr. 27, 2010 Sheet 6 of 7 US 7,705,647 B2

700
710 1
-H
DCin DCOut

FIG. 7

800
1
Adjust duty cycle of an input
clock signal based on a control
to generate an output clock signal
having an adjustable duty cycle
814
Detect error in the duty cycle
of the output clock signal
816
Generate the Control in
response to the detected
error in the duty cycle

FIG. 8
U.S. Patent Apr. 27, 2010 Sheet 7 Of 7 US 7,705,647 B2

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 US 7,705,647 B2
1. 2
DUTY CYCLE CORRECTION CIRCUIT duty cycle of the output clock signal and feeds back the
control to correct the duty cycle error. These circuits may be
BACKGROUND implemented with various designs, and several exemplary
embodiments are described below.
I. Field Various aspects and embodiments of the invention are
The present invention relates generally to electronics cir described in further detail below.
cuits, and more specifically to clock generation/distribution
circuitry. BRIEF DESCRIPTION OF THE DRAWINGS
II. Background
Clock signals are commonly used in many electronics cir 10 The features and nature of the present invention will
cuits and for various purposes. For example, clock signals are become more apparent from the detailed description set forth
used to trigger synchronous circuits (e.g., flip-flops) in digital below when taken in conjunction with the drawings in which
circuits such as processors, memory devices, and so on. Clock like reference characters identify correspondingly through
signals may be generated with various types of oscillator and Out.
Supporting circuitry. 15 FIG. 1 shows a clock generation/distribution circuit with
A clock signal continually transitions between logic high duty cycle correction.
and logic low. The clock signal has a duty cycle that is deter FIG. 2 shows a clock deskew circuit and a duty cycle
mined by the time duration at logic high and the time duration detection circuit.
at logic low. It is desirable to generate the clock signal to have FIG. 3 shows an embodiment of the clock deskew circuit.
a duty cycle that is as close to 50% as possible, so that the FIG. 4 shows an embodiment of the duty cycle detection
logic high duration is close to the logic low duration. A digital circuit.
circuit may use both the rising and falling edges of the clock FIG. 5 shows another embodiment of the clock deskew
signal to trigger synchronous circuits to achieve faster oper circuit.
ating speed. A 50% duty cycle for the clock signal may then FIG. 6 shows another embodiment of the duty cycle detec
provide the synchronous circuits with maximum timing mar 25 tion circuit.
g1nS. FIG. 7 shows a linear model of the duty cycle correction
The duty cycle of a clock signal may be distorted due to circuit.
various phenomena Such as mismatches in transistor devices FIG. 8 shows a process for generating a clock signal with
used to generate the clock signal. Great care is often used in good duty cycle.
designing clock generation and distribution circuits to mini 30 FIG.9 shows a wireless device with the duty cycle correc
mize device mismatches. Unfortunately, as device size tion circuit.
shrinks in advanced integrated circuit (IC) process technolo
gies, duty cycle distortion due to random variations and DETAILED DESCRIPTION
device mismatches becomes worse. Furthermore, digital cir
cuits fabricated with advanced IC processes typically operate 35 The word “exemplary' is used herein to mean “serving as
at high speed, e.g., one giga-Hertz (GHz) or higher. The high an example, instance, or illustration.” Any embodiment or
speed corresponds to a smaller clock period, e.g., 1 nanosec design described herein as "exemplary' is not necessarily to
ond (nsec) for 1 GHz. Small circuit mismatches may then be construed as preferred or advantageous over other embodi
translate to a relatively large error in duty cycle with the ments or designs.
Smaller clock period. 40 FIG. 1 shows a block diagram of an embodiment of a clock
The clock duty cycle problem is often addressed by run generation/distribution circuit 100 with duty cycle correction.
ning an oscillator at twice the desired frequency and dividing Clock generation/distribution circuit 100 includes a clock
an oscillator output signal by two to generate a clock signal generator 110, a clock distribution network 112, and a duty
with good duty cycle. However, this approach may be unde cycle correction circuit 120. Clock generator 110 generates a
sirable or inadequate for several reasons. First, more power is 45 clock signal. CK, having a duty cycle that may or may not be
consumed to operate the oscillator and the divide-by-2 circuit close to 50%. Clock generator 110 may include an oscillator
at twice the desired frequency. Second, significant duty cycle Such as a Voltage controlled oscillator (VCO), a Voltage con
distortion may still be present in the clock signal due to trolled crystal oscillator (VCXO), a delay line oscillator, or
random device mismatches in the divide-by-2 circuit. some other type of oscillator. Clock generator 110 may also
There is therefore a need in the art for techniques to effi 50 include a phase locked loop (PLL) that generates the clock
ciently generate a clock signal with good duty cycle. signal having an accurate frequency determined by a refer
ence signal. Clock distribution network 112 may include
SUMMARY buffer circuits that receive and buffer the clock signal from
clock generator 110 and provide an input clock signal, CKin,
Techniques for efficiently generating a clock signal having 55 having a duty cycle that may or may not be close to 50%.
good (e.g., approximately 50%) duty cycle are described Duty cycle correction circuit 120 includes a clock deskew
herein. In an embodiment, a duty cycle correction circuit is circuit 130 and a duty cycle detection circuit 140. Clock
disclosed which includes a clock deskew circuit and a duty deskew circuit 130 receives the CKinsignal from clock dis
cycle detection circuit. The clock deskew circuit (a first cir tribution network 112 and a duty cycle control from duty
cuit) receives an input clock signal that may have poor duty 60 cycle detection circuit 140. In general, circuits 120 and 130
cycle, adjusts the input clock signal based on a control, and may receive the CKinsignal from clock distribution network
provides an output clock signal having an adjustable duty 112 (as shown in FIG. 1), the CK signal from clock generator
cycle. The duty cycle detection circuit (a second circuit) 110, or a clock signal from some other source. Circuit 130
detects error in the duty cycle of the output clock signal and varies the duty cycle of the CKinsignal based on the duty
generates the control in response to the detected error in the 65 cycle control and generates a differential output clock signal,
duty cycle. The clock deskew circuit and the duty cycle detec CKoutp and CKoutn, having a duty cycle close to 50%. Cir
tion circuit implement a feedback loop that senses error in the cuit 130 also generates a single-ended output clock signal,
 US 7,705,647 B2
3 4
CKout, having similar duty cycle as the differential output Clock deskew circuit 130a operates as follows. P-FETs
clock signal. Duty cycle detection circuit 140 receives the 212a and 212b determine the pull-up strength of inverters
CKoutp and CKoutn signals, detects the duty cycle of these 210a and 210c, respectively, and control the slew rate of the
signals, and generates the duty cycle control for clock deskew rising edges of the output signals from inverters 210a and
circuit 130. 210c, respectively. N-FETs 214a and 214b determine the
Clock deskew circuit 130 and duty cycle detection circuit pull-down strength of inverters 210a and 210c, respectively,
140 may be implemented with various circuit designs. Fur and control the slew rate of the falling edges of the output
thermore, circuits 130 and 140 may be fabricated with various signals from inverters 210a and 210c, respectively. As the
IC process technologies, including complementary metal Vad voltage increases, N-FETs 214a and 214b are turned on
oxide semiconductor (CMOS). CMOS uses both N-channel 10 harder, and a faster falling edge slew rate is obtained. Con
field effect transistors (N-FETs) and P-channel FETs versely, as the Vadivoltage decreases, P-FETs 212a and 212b
(P-FETs). Several exemplary embodiments of circuits 130 are turned on harder, and a faster rising edge slew rate is
and 140 are described below. obtained. By pulling down or up harder, the slew rates for the
FIG. 2 shows a circuit diagram of a clock deskew circuit rising and falling edges may be varied, and different propa
130a and a duty cycle detection circuit 140a, which are an 15 gation delays may beachieved for the rising and falling edges.
embodiment of clock deskew circuit 130 and duty cycle The duty cycle of the clock signal may thus be varied by
detection circuit 140 in FIG. 1. adjusting P-FETs 212a and 212b and N-FETs 214a and 214b
Within clock deskew circuit 130a, four inverters 210a to obtain different slew rates and hence different propagation
through 210d are coupled in series, with inverter 210a receiv delays for the rising and falling edges.
ing the CKinsignal and inverter 210d providing a deskewed The Petrl and Nctrl controls may be generated as shown in
clock signal, CKd. Pull-up P-FETs 212a and 212b have their equation (1). In this case, the same Vad voltage is applied to
Sources coupled to a power Supply Voltage, V, their gates P-FETs 212a and 212b as well as N-FETs 214a and 214b. The
coupled together and receiving a PCtrl control, and their Pctrl and Nctrl controls may also be generated as shown in
drains coupled to inverters 210a and 210c, respectively. Pull equations (2) and (3). In this case, the Petrl and Nctrl controls
down N-FETs 214a and 214b have their sources coupled to 25 are in-phase controls that are level-shifted versions of the
circuit ground, their gates coupled together and receiving an Vad voltage, which may provide better control characteris
Nctrl control, and their drains coupled to inverters 210a and tics over process, Voltage, and temperature (PVT) variations.
210c, respectively. The Petrl and Nctrl controls are one In FIG. 2, variable slew rate control is applied to inverters
embodiment of the duty cycle control from the duty cycle 210a and 210c because the output signals from these inverters
detection circuit to the clock deskew circuit. A single-ended 30 have the same polarity. Variable slew rate control may also be
to differential (S2D) converter 216 receives the CKd signal applied to inverters 210b and 210d using other controls that
and generates the differential output clock signal, CKoutpand move in the opposite direction as the Vadivoltage. In general,
CKoutn. A buffer 218 buffers the CKoutp signal and provides variable slew rate control may be applied to any number of
the single-ended output clock signal, CKout. inverters to achieve the desired amount of duty cycle adjust
Within duty cycle detection circuit 140a, a current source 35 ment.
220 has one end coupled to the supply voltage and the other Duty cycle detection circuit 14.0a operates as follows. For
end coupled to node A. A switch 230 couples between nodes the left branch, when the CKoutp signal is at logic low, switch
A and B and receives the CKoutp signal at its control input. A 230 is turned on, and current source 220 provides a current of
current source 232 and a capacitor 234 are coupled in parallel 2-Icp through switch 230. Current source 232 sinks a current
and between node B and circuit ground. A switch 240 couples 40 of Icp, and the remaining current of Icp from current Source
between nodes A and C and receives the CKoutn signal at its 220 charges capacitor 234. Conversely, when the CKoutp
control input. A current source 242 and a capacitor 244 are signal is at logic high, Switch 230 is turned off. Current source
coupled in parallel and between node C and circuit ground. 232 then discharges capacitor 234 with a current of Icp. Thus,
Node B provides an adjust voltage, Vad, used to adjust the for the left branch, capacitor 234 is charged by current source
duty cycle of the clock signal. Switch230, current source 232, 45 220 with a current of Icp when the CKoutp signal is at logic
and capacitor 234 form the left branch for current source 220. low and is discharged by current source 232 with a current of
Switch 240, current source 242, and capacitor 244 form the Icp when the CKoutp signal is at logic high. Similarly, for the
right branch for current source 220. A unity gain buffer 236 right branch, capacitor 244 is charged by current source 220
has its input coupled to node B and its output coupled to node with a current of Icp when the CKoutn signal is at logic low
C. 50 and is discharged by current source 242 with a current of Icp
A control generator 250 receives the Vad voltage and when the CKoutn signal is at logic high.
generates the Pctrl and Nctrl controls for clock deskew circuit When steady state is reached, capacitor 234 is charged 50%
130a. In one embodiment, the Pctrl and Nctrl controls are set of the time and is discharged 50% of the time (or else the
equal to the Vad voltage, as follows: Voltage on capacitor 234 would integrate and saturate at either
Pctrl=Nctrl=Vad. Eq.(1) 55 an upper or lower rail Voltage). The Voltage on capacitor 234
is varied such that the CKoutp signal has approximately 50%
In another embodiment, the Nctrl and Pctrl controls are duty cycle and charges and discharges capacitor 234 about
level-shifted versions of the Vad voltage, as follows: 50% of the time.
Pctrl=Vadi-Offset1, and Eq. (2) Duty cycle detection circuit 14.0a may be considered as a
60 current steering charge pump. The right branch is a second
Nctrl=Vadi-Offset2, Eq. (3) branch that allows current source 220 to steer its current
through either the left branch or the right branch at any given
where Offset1 and Offset2 may be any suitable non-negative moment. This current steering results in the Voltage at node A
values. Control generator 250 may be implemented with a being held relatively constant regardless of whether the
level shifter for the embodiment shown in equations (2) and 65 CKoutp signal is at logic high or logic low. Capacitors 234
(3). The Pctrl and Nctrl controls may also be generated in and 244 may have the same or different capacitance values,
other manners. and their exact values are not critical. Although not shown in
 US 7,705,647 B2
5 6
FIG. 2 for simplicity, parasitic capacitors are present at vari P-FET 434a and N-FET 434b have their gates coupled to the
ous circuit nodes and can affect the charging and discharging drain of P-FET 430, which provides the Vad voltage for
of capacitor 234 via a phenomenon commonly referred to as control generator 250. P-FET 444a and N-FET 444b have
charge sharing. Since node C is not connected within a feed their gates coupled to the drain of P-FET 440.
back loop, the Voltage at this node may drift into saturation at In the embodiment shown in FIG. 4, P-FET 420 and
either the upper or lower rail voltage. Buffer 236 maintains N-FETs 432 and 442 correspond to current sources 220, 232
the Voltage at node C equal to the Voltage at node B and and 242, respectively, in FIG. 2. P-FETs 430 and 440 corre
prevents node C from drifting into Saturation. spond to switches 230 and 240, respectively. FETs 434a and
As shown in FIG. 2, clock deskew circuit 130a and duty 434b form capacitor 234, and FETs 444a and 444b form
cycle detection circuit 14.0a implement a feedback loop that 10 capacitor 244.
senses distortion or error in the duty cycle of the CKoutp N-FETs 422, 432 and 442 form a current mirror, and each
signal and feeds back the duty cycle control to correct the of these N-FETs has a device size of M. The Vbias voltage
distortion. Duty cycle detection circuit 14.0a detects the duty determines the amount of current (Icp) flowing through
cycle of the CKoutp signal and generates a charging/discharg N-FET 422. This same amount of current (Icp) flows through
ing current that is proportional to the detected error in the duty 15 each of N-FETs 432 and 442 (because the N-FETs have the
cycle. This charging/discharging current is integrated by same device size) as well as through P-FET 424 (because of
capacitor 234 to generate the Vad voltage. Clock deskew the circuit connection). P-FETs 420 and 424 also form a
circuit 130a uses the Pctrl and Nctrl controls, which are current mirror. Since P-FET 424 has a device size of M
generated from the Vad voltage, to adjust the slew rate of the whereas P-FET 420 has a device size of 2M, the amount of
inverters 210a and 210c to correct the duty cycle error. current flowing through P-FET 420 is twice the amount of
FIG. 3 shows a schematic diagram of a clock deskew current flowing through P-FET 424.
circuit 130b, which is an embodiment of clock deskew circuit FIG. 5 shows a circuit diagram of a clock deskew circuit
130a in FIG. 2. Within circuit 130b, each of inverters 210a 130C, which is another embodiment of clock deskew circuit
through 210d is formed with a P-FET312 and an N-FET 3.14. 130 in FIG. 1. Clock deskew circuit 130c may be used for
P-FET312 and N-FET 314 have their gates coupled together 25 low-voltage applications since only three FETs are stacked
and forming the input of the inverter and their drains coupled and connected between the Supply Voltage and circuit ground.
together and forming the output of the inverter. The source of In contrast, clock deskew circuit 130b in FIG. 3 has four
P-FET 3.12a for inverter 210a is coupled to the drain of stacked FETs.
pull-up P-FET 212a, and the source of P-FET 3.12b for Within clock deskew circuit 130C, inverters 510a and 510b
inverter 210c is coupled to the drain of pull-up P-FET 212b. 30 are coupled in parallel and receive the CKinsignal at their
The source of N-FET 3.14.a for inverter 210a is coupled to the inputs. A pull-up P-FET 512 has its source coupled to the
drain of pull-down N-FET 214a, and the source of N-FET supply voltage, its gate receiving the Petrl control, and its
314b for inverter 210c is coupled to the drain of pull-down drain coupled to inverter 510a. A pull-down N-FET 514 has
N-FET 214b. P-FETs 212a and 212b control the pull up its source coupled to circuit ground, its gate receiving the
strength of inverters 210a and 210c, respectively. Corre 35 Nctrl control, and its drain coupled to inverter 510b. Inverters
spondingly, N-FETs 214a and 214b control the pull down 510a and 510b may each be implemented with a P-FET and
strength of inverters 210a and 210c, respectively. Although an N-FET as shown in FIG.3. The drain of pull-up P-FET 512
not shown in FIG. 3, inverters 210b and 210d may couple would then be coupled to the source of the P-FET for inverter
directly between the Supply Voltage and circuit ground. 510a. The drain of pull-down N-FET 514 would be coupled to
Single-ended to differential converter 216 includes two 40 the Source of the N-FET for inverter 510b.
paths for the CKoutn and CKoutp signals. The path for the An output circuit includes P-FETs 516 and 520 and
CKoutn signal includes three inverters 320a, 320b and 320c N-FETs 518 and 522. P-FETS 516 and 520 have their sources
coupled in series. Inverter 320a receives the deskewed clock coupled to the Supply Voltage and their gates coupled to the
signal, CKd, and inverter 320c provides the CKoutn signal. outputs of inverters 510a and 510b, respectively. N-FETs 518
The path for the CKoutp signal includes an inverter 322a, a 45 and 522 have their sources coupled to circuit ground, their
delay circuit 324, and an inverter 322b coupled in series. gates coupled to the outputs of inverters 510b and 510a,
Inverter 322a receives the CKd signal, and inverter 322b respectively, and their drains coupled to the drains of P-FETs
provides the CKoutp signal. Delay circuit 324 provides a 516 and 520, respectively. The drains of FETs 520 and 522
delay to match the delay of inverter 320b and may be imple provide the deskewed clock signal, CKd.
mented, e.g., with a capacitor connected to the output of 50 P-FET 512 determines the pull up strength of inverter 510a
inverter 322a. and controls the slew rate of the rising edges of the output
FIG. 4 shows a schematic diagram of a duty cycle detection signal from inverter 510a. N-FET 514 determines the pull
circuit 140b, which is an embodiment of duty cycle detection down strength of inverter 510b and controls the slew rate of
circuit 14.0a in FIG. 2. Within circuit 140b, N-FETs 422,432 the falling edges of the output signal from inverter 510b.
and 442 have their sources coupled to circuit ground and their 55 Inverters 510a and 510b drive the gates of N-FET 522 and
gates coupled together and receiving a bias Voltage, Vbias. P-FET 520, respectively. The duty cycle of the CKd signal
P-FETs 420 and 424 have their sources coupled to the supply may be varied by adjusting P-FET 512 and N-FET 514 to
Voltage and their gates coupled together and further to the obtain different slew rates and hence different propagation
drain of N-FET 422. P-FETS 430 and 440 have their sources delays for the rising and falling edges. P-FET 516 and N-FET
coupled together and to the drain of P-FET 420, their sources 60 518 match the output loads of inverters 510a and 510b.
coupled to the drains of N-FETs 432 and 442, respectively, With the Pctrl and Nctrl controls defined as shown in either
and their gates receiving the CKoutp and CKoutn signals, equation (1) or equations (2) and (3), decreasing the Vad
respectively. Unity gain buffer 236 has its input coupled to the voltage results in P-FET 512 turning on harder and N-FET
drain of P-FET 430 and its output coupled to the drain of 514 turning on Softer. This then results in a faster rising edge
P-FET 440. P-FETs 434a and 444a have their sources and 65 slew rate for inverter 510a and a slowerfalling edge slew rate
drains coupled to the supply voltage. N-FETs 434b and 444b for inverter 510b. The converse is true for increasing Vad
have their sources and drains coupled to circuit ground. voltage. The duty cycle of the CKd signal may thus be varied
 US 7,705,647 B2
7 8
by adjusting the Vad voltage, which varies the Petrl control mer 710, again element 730 that models clock deskew circuit
for P-FET 512 as well as the Nctrl control for N-FET 514. 130, and an integrator 740 that models duty cycle detection
In FIG. 5, inverters 510a and 510b and FETs 512 through circuit 140.
522 may be considered one stage. Multiple stages (e.g. 2, 4, The CKinsignal received by clock deskew circuit 130 has
6, 8 or some other number of stages) may be coupled in series a duty cycle of DCin, and the CKout signal provided by clock
to provide the desired amount of duty cycle adjustment. The deskew circuit 130 has a duty cycle of DCout. DCin and
deskewed clock signal from the last stage may be provided to DCout may each be given in terms of absolute time deviation
converter 216. from 50% duty cycle. Summer 710 subtracts a duty cycle
FIG. 6 shows a circuit diagram of a duty cycle detection adjustment, DCad, from DCin and provides DCout, which
circuit 140c, which is another embodiment of duty cycle 10 may be expressed as:
detection circuit 140 in FIG.1. Circuit 140c has fewer circuit
components than duty cycle detection circuit 14.0a in FIG. 2 DCout-DCin-DCadi=DCin-Kc. Vadi, Eq. (4)
and may be Suitable for Some applications. where Kc is a constant that is dependent on the design of the
Within circuit 140C, a current source 620 and a switch 622 clock deskew circuit. The minus sign in equation (4) ensures
are coupled in series and between the Supply Voltage and node 15
negative feedback.
B. A switch 630 and a current source 632 are coupled in series Duty cycle detection circuit 140 may be implemented with
and between node B and circuit ground. Switches 622 and an integrator that is controlled by clock phases, as shown by
630 receive the CKoutp and CKoutn signals, respectively, at
their control inputs. A capacitor 634 is coupled between node the embodiments in FIGS. 2, 4 and 6. In these embodiments,
Band circuit ground. Control generator 250 receives the Vad the output of circuit 140 ramps up linearly with a slope of
voltage at node B and generates the Petrl and Nctrl controls Icp/C1 on one clock phase and ramps down linearly with the
for the clock deskew circuit. same slope on the opposite clock phase. The slope is deter
Duty cycle detection circuit 140c operates as follows. mined by the charging/discharging current (Icp) for the
When the CKoutp signal is at logic low and the CKoutn signal capacitor used for integration and the value (C1) of the
is at logic high, switch 622 is turned on and switch 630 is 25 capacitor. If the clock duty cycle deviates from 50% by At,
turned off. Current source 620 then provides a current of Icp then the average charging/discharging current, Io, over one
through switch 622. This current charges capacitor 634. Con clock period may be expressed as:
versely, when the CKoutp signal is at logic high and the Io=(2Atfo) Icp, Eq. (5)
CKoutn signal is at logic low, switch 622 is turned off and
switch 630 is turned on. Current source 632 then sinks a 30 where fo is the clock frequency. As a continuous-time
current of Icp through switch 630. This current discharges approximation, the average value of the Vad voltage may be
capacitor 634. Thus, capacitor 634 is charged by current expressed as:
source 620 with a current of Icp when the CKoutp signal is at
logic low and is discharged by current source 632 with a
current of Icp when the CKoutn signal is at logic low. When 35
Wadi
Clay = S. C1
Eq. (6)
steady state is reached, capacitor 644 is charged about 50% of
the time and is discharged about 50% of the time.
Several embodiments of clock deskew circuit 130 and duty
cycle detection circuit 140 have been described above. Cir where S is a Laplace variable.
cuits 130 and 140 may also be implemented with other 40 The transfer function of duty cycle detection circuit 140,
designs, and this is within the scope of the present invention. Hcp(s), may then be expressed as:
In general, clock deskew circuit 130 may be any circuit that
can adjust the duty cycle of a clock signal based on a duty
cycle control. The duty cycle adjustment may be achieved by Hop(s) = Wadi o
At S. C1. 2 fo lep Eq. (7)
varying the slew rates of the rising and falling edges of invert 45 At T. S. C1
ers, as described above. The duty cycle adjustment may also
beachieved with other mechanisms, e.g., bypassing the CKin Integrator 740 receives the output clock duty cycle, DCout,
signal through multiple paths with different duty cycles and
selecting one path based on the control from the duty cycle applies the transfer function Hep(s), and provides the Vad
detection circuit. 50 voltage. Gain element 730 scales the Vad voltage by Kc and
Duty cycle detection circuit 140 may be any circuit that can provides DCad.
detect the duty cycle of the clock signal and generate the duty The closed-loop transfer function, H(s), for model 700 may
cycle control. The duty cycle detection may be achieved by be expressed as:
charging and discharging a capacitor, as described above, or
by other mechanisms. The duty cycle control may be given in 55
Eq. (8)
any form, e.g., as one or more digital signals, one or more 2. fo. Kc. Icp
Voltages, one or more currents, and so on. s+ —
The embodiments shown in FIGS. 2 through 6 correct error
in clock duty cycle using a feedback mechanism. The prob
lem of matching transistor devices in a high-speed clock path 60 The closed-loop bandwidth of H(s), BW, may be expressed
is essentially converted into a problem of matching transistor aS
devices in a low-speed charge pump. This may substantially
reduce power consumption. Furthermore, the embodiments
described above reduce the number of possible sources of BW fo. Kc. lop Eq. (9)
duty cycle error. 65 it. C1
FIG. 7 shows a diagram of a linear model 700 of duty cycle
correction circuit 120 in FIG. 1. Model 700 includes a sum
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10
For a given clock frequency, fo, and a given clock deskew controller/processor 930 directs the operation of the process
circuit gain, Kc, the desired closed-loop bandwidth may be ing units within digital section 920. A memory 932 stores data
obtained by selecting the proper charging/discharging current and program codes for the processing units. An external inter
Icp and the proper value for the capacitor C1. In one exem face unit 938 interfaces with other units external to digital
plary design, with a clock frequency of 500 MHz. Kc=1.3 5 Section 920.
insec/V, Icp=20LA, C1=2 pF, and the closed-loop bandwidth A clock generator 940 generates clock signals used by the
is approximately 2 MHz. processing units within digital section 920. Clock generator
FIG. 8 shows an embodiment of a process 800 for gener 940 may include one or more VCOs and/or PLLs to generate
ating a clock signal with good duty cycle. The duty cycle of an the clock signals. Clock generator 940 distributes clock sig
input clock signal is adjusted based on a control to generate an 10 nals to other processing units within digital section 920. The
output clock signal having an adjustable duty cycle (block clock distribution network is represented by the lines going
812). Error in the duty cycle of the output clock signal is from clock generator 940 to other processing units. Duty
detected (block 814). The control is generated in response to cycle correction circuits (DCCs) may be implemented in
the detected error in the duty cycle (block 816). controller/processor 930, memory 932, DSP core 934, pro
The duty cycle adjustment may be performed using various 15 cessor core 936, interface unit 938, and/or other units.
circuits. For example, one or more inverters may be used to The duty cycle correction circuit described herein may be
adjust the duty cycle of the input clock signal. One or more used to improve the duty cycle of a clock signal from an
pull-up transistors (e.g., P-FETs) may be used to adjust the oscillator, a PLL, a clock distribution network, or some other
rising edge slew rate of the inverters. Alternatively or addi clock source. The duty cycle correction circuit can generate
tionally, one or more pull-down transistors (e.g., N-FETs) an output clock signal having good duty cycle, e.g., close to
may be used to adjust the falling edge slew rate of the invert 50%. Duty cycle may be an important specification of the
ers. The pull-up and pull-down transistors may operate on the clock signal and may be more important for higher clock rates
same inverters (e.g., as shown in FIGS. 2 and3) or on different used in many modern day electronics devices. The duty cycle
inverters (e.g., as shown in FIG. 5). The pull-up and pull correction circuit can be conveniently implemented in any
down transistors may receive the same or different control 25 part of an integrated circuit and used to correct clock duty
Voltages. cycle wherever needed. Any number of duty cycle correction
The duty cycle error detection may also be performed using circuits may be implemented on a given integrated circuit.
various circuits. For example, a capacitor may provide a The duty cycle correction circuit described herein may
Voltage indicative of the duty cycle error, a first current Source provide various advantages. The circuit can automatically
may provide a charging current for the capacitor, and a second 30 and continuously correct errors in clock duty cycle. The cir
current source may provide a discharging current for the cuit may be powered using an available power Supply (e.g.,
capacitor. The duty cycle error detection may be achieved by the supply voltage for digital circuits) and does not require an
operating a Switch with the output clock signal and charging accurate external bias. The circuit may be implemented using
or discharging the capacitor with the Switch. An additional set standard circuit components (e.g., transistor devices) in a
of capacitor, current Source, and Switch may be used for a 35 small silicon area. The circuit also consumes relatively little
current steering charge pump design, e.g., as shown in FIGS. power.
2 and 4. The duty cycle correction circuit described herein may be
The duty cycle correction circuit described herein may be implemented in an integrated circuit (IC), an application spe
used for various electronics circuits. The use of the duty cycle cific integrated circuit (ASIC), a digital signal processor
correction circuit in a wireless communication device is 40 (DSP), a digital signal processing device (DSPD), a program
described below. mable logic device (PLD), a field programmable gate array
FIG. 9 shows a block diagram of a wireless device 900, (FPGA), a processor, a controller, a micro-controller, a
which may be may be a cellular phone, a terminal, a personal microprocessor, and other electronic units. The duty cycle
digital assistant (PDA), a handset, or Some other device. correction circuit may also be fabricated using various IC
Wireless device 900 may be able to communicate with vari 45 process technologies such as CMOS, N-MOS, P-MOS, BJT,
ous wireless communication systems such as CDMA, GaAs, and so on. The duty cycle correction circuit may also
TDMA, FDMA, GSM, OFDMA, GPS and/or other systems be implemented with discrete components.
known in the art. The previous description of the disclosed embodiments is
On the receive path, an antenna 912 receives signals trans provided to enable any person skilled in the art to make or use
mitted by base stations and/or satellites and provides a 50 the present invention. Various modifications to these embodi
received signal to a receiver (RCVR) 914. Receiver 914 pro ments will be readily apparent to those skilled in the art, and
cesses (e.g., filters, amplifies, frequency downconverts, and the generic principles defined herein may be applied to other
digitizes) the received signal and provides samples to a digital embodiments without departing from the spirit or scope of the
section 920 for further processing. On the transmit path, invention. Thus, the present invention is not intended to be
digital section 920 processes data to be transmitted and pro 55 limited to the embodiments shown herein but is to be
vides data chips to a transmitter (TMTR) 916. Transmitter accorded the widest scope consistent with the principles and
916 processes (e.g., converts to analog, filters, amplifies, and novel features disclosed herein.
frequency upconverts) the data chips and generates a modu What is claimed is:
lated signal, which is transmitted via antenna 912. 1. A device comprising:
Digital section 920 includes various processing units that 60 a first circuit configured to adjust duty cycle of an input
Support communication and/or other functions. Within digital clock signal based on a common control Voltage and
section 920, a digital signal processor (DSP) core 934 per provide an output clock signal having adjustable duty
forms processing (e.g., encoding and modulation) for the cycle; and
transmit path, processing (e.g., demodulation and decoding) a second circuit configured to detect error in the duty cycle
for the receive path, and/or processing for other applications 65 of the output clock signal and to generate the common
and functions. A processor core 936 supports various func control Voltage in response to the detected error in the
tions such as Video, audio, graphics, gaming, and so on. A duty cycle;
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11 12
wherein a third current source coupled in parallel with the second
the first circuit comprises a first inverter and a second capacitor, and
inverter configured to adjust the duty cycle of the input a second switch coupled between the first current source
clock signal, a pull-up transistor coupled to the first and the third current source and configured to receive an
inverter and configured to adjust rising edge slew rate of 5 inverted output clock signal.
the first inverter based on a first control voltage, and a 6. The device of claim 5, wherein the second circuit further
pull-down transistor coupled to the first inverter and comprises
configured to adjust falling edge slew rate of the first a buffer having an input coupled to the first capacitor and an
inverter based on a second control Voltage; and output coupled to the second capacitor.
the second circuit comprises a control generator configured 10 7. An integrated circuit comprising:
to generate the first and second control Voltages as level a first circuit configured to adjust duty cycle of air input
shifted versions of the common control voltage, the first clock signal based on a control and provide an output
control Voltage being lower than the second control Volt clock signal having adjustable duty cycle; and
age. a second circuit configured to detect error in the duty cycle
2. A device comprising: 15 of the output clock signal and to generate the control in
a first circuit configured to adjust duty cycle of an input response to the detected error in the duty cycle:
clock signal based on a common control Voltage and wherein the first circuit includes a first inverter and a sec
provide an output clock signal having adjustable duty ond inverter configured to adjust the duty cycle of the
cycle; and input clock signal; and
a second circuit configured to detect error in the duty cycle wherein the second circuit comprises:
of the output clock signal and to generate the common a first capaciter configured to provide a Voltage indicative
control Voltage in response to the detected error in the of the error in the duty cycle of the output clock signal,
duty cycle; a first current Source configured to provide a charging
wherein the first circuit comprises: current for the first capacitor, and
a first inverter and a second inverter configured to adjust the 25 a second current source configured to provide a discharg
duty cycle of the input clock signal, ing current for the first capacitor,
a pull-up transistor coupled to the first inverter and config a second capacitor,
ured to adjust rising edge slew rate of the first inverter, a third current source coupled in parallel with the second
a pull-down transistor coupled to the second inverter and capacitor,
configured to adjust falling edge slew rate of the second 30 a first switch coupled between the first current source and
inverter, and the first capacitor and configured to receive the output
an output circuit coupled to the first and second inverters clock signal, and
and configured to generate an output signal having a second switch coupled between the first current source
adjustable duty cycle. and the second capacitor and configured to receive an
3. The device of claim 2, wherein the pull-up transistor 35 inverted output clock signal, and wherein the first
receives a first control Voltage and the pull-down transistor capacitor is coupled in parallel with the second current
receives a second control Voltage, and wherein the first and SOUC.
second control voltages are level shifted versions of the com 8. The integrated circuit of claim 7, wherein the first circuit
mon control voltage. further comprises a pull-up transistor coupled to the first
4. The device of claim 2, wherein the first inverter and the 40 inverter and configured to adjust rising edge slew rate of the
pull-up transistor comprise three stacked transistors coupled first inverter.
between a power Supply Voltage and circuit ground, and 9. The integrated circuit of claim 7, wherein the first circuit
wherein the second inverter and the pull-down [Link] further comprises a pull-down transistor coupled to the first
prise three stacked transistors coupled between the power inverter and configured to adjust falling edge slew rate of the
Supply Voltage and circuit ground. 45 first inverter.
5. A device comprising: 10. The integrated circuit of claim 7, wherein the first and
a first circuit configured to adjust duty cycle of an input second circuits are implemented with N-channel field effect
clock signal based on a control and provide an output transistors (N-FETs) and P-channel field effect transistors
clock signal having adjustable duty cycle; and (P-FETs).
a second circuit configured to detect error in the duty cycle 50 11. The integrated circuit of claim 7, wherein the first
of the output clock signal and to generate the control in capacitor is implemented with at least one field effect tran
response to the detected error in the duty cycle: sistor (FET).
wherein the first circuit includes a first inverter and a sec 12. A wireless device comprising:
ond inverter configured to adjust the duty cycle of the the integrated circuit of claim 7; and
input clock signal; and 55 a clock generator configured to generate the input clock
wherein the second circuit comprises signal.
a first capacitor configured to provide a Voltage indicative 13. The integrated circuit of claim 7, wherein the first
of the error in the duty cycle of the output clock signal, inverteris coupled to at least one of (a) a pull-up transistorand
a first current source configured to provide a charging (b) a pull-down transistor, and the second inverter is coupled
current for the first capacitor, 60 to at least one of (a) a pull-up transistor and (b) a pull-down
a second current source configured to provide a discharg transistor
ing current for the first capacitor, 14. A method comprising:
a first switch coupled between the first current source and adjusting duty cycle if an input clock signal based on a
the first capacitor and configured to receive the output control to generate an output clock signal having adjust
clock signal, and wherein the first capacitoris coupled in 65 able duty cycle:
parallel with the second current source, detecting error in the duty cycle of the output clock signal;
a second capacitor, and
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13 14
generating the control in response to the detected error in means for discharging the second capacitor with a dis
the duty cycle, charging current for the first logic level of the output
wherein adjusting the duty cycle of the input clock signal clock signal.
includes adjusting rising edge slew rate or falling edge 16. A wireless device comprising:
slew rate of a first inverter and a second inverter, and a clock generator configured to generate an input clock
wherein detecting error in the duty cycle of the output clock signal; and
signal comprises: at least one duty cycle correction circuit, each duty cycle
charging a first capacitor with a charging current for a correction circuit configured to:
first logic level of the output clock signal; receive the input clock signal,
discharging the first capacitor with a discharging current 10 adjust duty cycle of the input clock signal based on a
for a second logic level of the output clock signal; control to generate an output clock signal having
charging a second capacitor with a charging current for adjustable duty cycle,
the second logic level of the output clock signal; and detect error in the duty cycle of the output clock signal,
discharging the second capacitor with a discharging cur and
rent for the first logic level of the output clock signal. 15
generate the control in response to the detected error in
15. An apparatus comprising: the duty cycle,
means for adjusting duty cycle of an input clock signal wherein adjusting the duty cycle includes adjusting ris
based on a control to generate an output clock signal ing edge slew rate or falling edge slew rate of a first
having adjustable duty cycle; inverter and a second inverter, and
means for detecting error in the duty cycle of the output wherein each duty cycle correction circuit configured to
clock signal; and detect error in the duty cycle of the output clock signal is
means for generating the control in response to the detected further configured to:
error in the duty cycle, charge a first capacitor with a charging current for a first
wherein the adjusting means includes: (1) means for logic level of the output clock signal;
adjusting rising edge slew rate of a first inverter, or 25
discharge the first capacitor with a discharging current
means for adjusting falling edge slew rate of a first for a second logic level of the output clock signal;
inverter, and (2) means for adjusting rising edge slew charge a second capacitor with a charging current for the
rate of a second inverter, or means for adjusting falling second logic level of the output clock signal; and
edge slew rate of a second inverter, and discharge the second capacitor with a discharging cur
wherein means for detecting error in the duty cycle of the 30
output clock signal comprises: rent for the first logic level of the output clock signal.
means for charging a capacitor with a charging current 17. The wireless device of claim 10, further comprising:
for a first logic level of the output clock signal; a digital signal processor (DSP) core comprising the at
means for discharging the capacitor with a discharging least one duty cycle correction circuit.
current for a second logic level of the output clock 35 18. The wireless device of claim 10, further comprising:
signal; a processor core comprising the at least one duty cycle
means for charging a second capacitor with a charging correction circuit.
current for the second logic level of the output clock
signal; and