Memory Locations,

Addresses, and
Operations
Pallavi B
Assistant Professor,
AI&ML Dept.,
B.M.S.C.E
Memory Location, Addresses,
and Operation
64bits

0 first word
● Memory consists
second word
of many millions of 8

storage cells,
•
each of which can •
•
store 1 bit.
● Data is usually i th word
accessed in n-bit
groups. n is called •
word length. •
•

last word

Figure 2.5. Memory words.

Memory Location, Addresses,
and Operation 1000

● 32-bit word length example

32 bits

b31 b30 b1 b0

•
•
•
Sign bit: b31= 0 for positive numbers
b31= 1 for negative numbers
65
(a) A signed integer
01100101

8 bits 8 bits 8 bits 8 bits

ASCII ASCII ASCII ASCII

character character character character

(b) Four characters

Memory Location, Addresses,
and Operation
● To retrieve information from memory, either for one
word or one byte (8-bit), addresses for each location
are needed.
● A k-bit address memory has 2k memory locations,
namely 0 – 2k-1, called memory space.
● 24-bit memory: 224 = 16,777,216 = 16M (1M=220)
● 32-bit memory: 232 = 4G (1G=230)
● 1K(kilo)=210
● 1T(tera)=240
Memory Location, Addresses,
and Operation
● It is impractical to assign distinct addresses
to individual bit locations in the memory.
● The most practical assignment is to have
successive addresses refer to successive
byte locations in the memory – byte-
addressable memory.
● Byte locations have addresses 0, 1, 2, … If
word length is 32 bits, they successive words
are located at addresses 0, 4, 8,…
Memory Location, Addresses,
and Operation
● Address ordering of bytes
● Word alignment
● Words are said to be aligned in memory if they
begin at a byte addr. that is a multiple of the num
of bytes in a word.
● 16-bit word: word addresses: 0, 2, 4,….
● 32-bit word: word addresses: 0, 4, 8,….
● 64-bit word: word addresses: 0, 8,16,….
● Access numbers, characters, and character
strings
Memory Operation
● Load (or Read or Fetch)
⮚ Copy the content. The memory content doesn’t change.
⮚ Address – Load
⮚ Registers can be used
● Store (or Write)
⮚ Overwrite the content in memory
⮚ Address and Data – Store
⮚ Registers can be used
Instruction and
Instruction
Sequencing
Pallavi B
Assistant Professor,
AI&ML Dept.,
B.M.S.C.E
“Must-Perform” Operations
● Data transfers between the memory and the
processor registers
● Arithmetic and logic operations on data
● Program sequencing and control
● I/O transfers
Register Transfer Notation
● Identify a location by a symbolic name
standing for its hardware binary address
(LOC, R0,…)
● Contents of a location are denoted by placing
square brackets around the name of the
location (R1←[LOC], R3 ←[R1]+[R2])
● Register Transfer Notation (RTN)
Assembly Language Notation
● Represent machine instructions and
programs.
● Move LOC, R1 = R1←[LOC]
● Add R1, R2, R3 = R3 ←[R1]+[R2]
CPU Organization
● Single Accumulator
● Result usually goes to the Accumulator
● Accumulator has to be saved to memory quite
often
● General Register
● Registers hold operands thus reduce memory
traffic
● Register bookkeeping
● Stack
● Operands and result are always in the stack
Instruction Formats
● Three-Address Instructions
● ADD R1, R2, R3 R3 ← [R1] +[ R2]
● Two-Address Instructions
● ADD R1, R2 R2 ← [R1] + [R2]
● One-Address Instructions
● ADD M AC ← AC + M[AR]
● Zero-Address Instructions
● ADD TOS ← TOS + (TOS – 1)
● RISC Instructions
● Lots of registers. Memory is restricted to Load & Store

Opcode Operand(s) or Address(es)

Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Three-Address
1. ADD A, B,R1 ; R1 ← M[A] + M[B]
2. ADD C, D,R2 ; R2 ← M[C] + M[D]
3. MUL R1, R2,X ; M[X] ← R1 * R2
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Two-Address
1. MOV A,R1 ; R1 ← M[A]
2. ADD B,R1 ; R1 ← R1 + M[B]
3. MOV C,R2 ; R2 ← M[C]
4. ADD D,R2 ; R2 ← R2 + M[D]
5. MUL R1, R2 ; R1 ← R1 * R2
6. MOV R2,X ; M[X] ← R1
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● One-Address
1. LOAD A ; AC ← M[A]
2. ADD B ; AC ← AC + M[B]
3. STORE T ; M[T] ← AC
4. LOAD C ; AC ← M[C]
5. ADD D ; AC ← AC + M[D]
6. MUL T ; AC ← AC * M[T]
7. STORE X ; M[X] ← AC
 Instruction Formats
Example: Evaluate (A+B) * (C+D)
● Zero-Address
Instruction Formats
Example: Evaluate (A+B) * (C+D)
● RISC
1. LOAD R1, A ; R1 ← M[A]
2. LOAD R2, B ; R2 ← M[B]
3. LOAD R3, C ; R3 ← M[C]
4. LOAD R4, D ; R4 ← M[D]
5. ADD R1, R1, R2 ; R1 ← R1 + R2
6. ADD R3, R3, R4 ; R3 ← R3 + R4
7. MUL R1, R1, R3 ; R1 ← R1 * R3
8. STORE X, R1 ; M[X] ← R1
Using Registers
● Registers are faster
● Shorter instructions
● The number of registers is smaller (e.g. 32
registers need 5 bits)
● Potential speedup
● Minimize the frequency with which data is
moved back and forth between the memory
and processor registers.
Addressing
Modes
Pallavi B
Assistant Professor,
AI&ML Dept.,
B.M.S.C.E
1. Implied Addressing Mode-

In this addressing mode,

● The definition of the instruction itself specify

the operands implicitly.

● It is also called as implicit addressing

mode.
1. Implied Addressing Mode-

● Examples-

● The instruction “Complement Accumulator”

is an implied mode instruction.
● In a stack organized computer, Zero
Address Instructions are implied mode
instructions.
[Link] Addressing Mode-

● The operand is specified in the instruction

explicitly.
● Instead of address field, an operand field is
present that contains the operand.
● Examples-

● ADD 10 will increment the value stored in

the accumulator by 10.
● MOV R #20 initializes register R to a
constant value 20.
Immediate Addressing
Simplest form of addressing
Operand = A
Operand is part of instruction
Operand = address field
e.g. ADD #5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range

ADD #1000,R0
[Link] Addressing Mode-

In this addressing mode,

● The address field of the instruction contains

the effective address of the operand.

● Only one reference to memory is required to

fetch the operand.

● It is also called as absolute addressing

mode.
[Link] Addressing Mode-
● Example-

● ADD X will increment the value stored in the

accumulator by the value stored at memory
location X.
● AC ← AC + [X]
Register (Direct) Addressing
• Address field refers to a register rather than a main memory
address
• EA = R
• Limited number of registers
• Very small address field needed Shorter instructions
• Faster instruction fetch
• No memory access
• Very limited address space
• Multiple registers helps performance
4. Indirect Addressing Mode-

In this addressing mode,

● The address field of the instruction specifies

the address of memory location that contains

the effective address of the operand.
● Two references to memory are required to

fetch the operand.

4. Indirect Addressing Mode-
4. Indirect Addressing Mode-
● Example-

● ADD X will increment the value stored in the

accumulator by the value stored at memory
location specified by X.
● AC ← AC + [[X]]
Register mode
[Link] Direct Addressing Mode-

In this addressing mode,

● The operand is contained in a register set.

● The address field of the instruction refers to

a CPU register that contains the operand.

● No reference to memory is required to fetch

the operand.
[Link] Direct Addressing Mode-
[Link] Direct Addressing Mode-

● Example-

● ADD R will increment the value stored in the

accumulator by the content of register R.
● AC ← AC + [R]
[Link] Indirect Addressing Mode-

In this addressing mode,

● The address field of the instruction refers to

a CPU register that contains the effective

address of the operand.
● Only one reference to memory is required to

fetch the operand.

[Link] Indirect Addressing Mode-
Register Indirect Addressing Mode-

Example-

● ADD R will increment the value stored in the

accumulator by the content of memory
location specified in register R.
● AC ← AC + [[R]]
[Link] Addressing Mode-

In this addressing mode,

● Effective address of the operand is obtained

by adding the content of program counter

with the address part of the instruction.
NOTE-

● Program counter (PC) always contains the address of

the next instruction to be executed.
● After fetching the address of the instruction, the value of
program counter immediately increases.
● The value increases irrespective of whether the fetched
instruction has completely executed or not.
[Link] Addressing Mode-

In this addressing mode,

● Effective address of the operand is obtained

by adding the content of index register with

the address part of the instruction.
[Link] Addressing Mode-
[Link]-Increment Addressing Mode-

This addressing mode is a special case of

Register Indirect Addressing Mode where-
In this addressing mode,
● After accessing the operand, the content of

the register is automatically incremented by

step size ‘d’.
● Step size ‘d’ depends on the size of operand

accessed.
● Only one reference to memory is required to

fetch the operand.

[Link]-Increment Addressing Mode-

Here,
● After fetching the operand 6B, the
instruction register RAUTO will be
automatically incremented by 2.
● Then, updated value of RAUTO will be
3300 + 2 = 3302.
● At memory address 3302, the next
operand will be found .
Auto-Decrement Addressing Mode-

This addressing mode is again a special case

of Register Indirect Addressing Mode where-
● In this addressing mode,
● First, the content of the register is
decremented by step size ‘d’.
● Step size ‘d’ depends on the size of operand
accessed.
● After decrementing, the operand is read.
● Only one reference to memory is required to
fetch the operand.
Assume operand size = 2 bytes.
Here,
● First, the instruction register
RAUTO will be decremented by 2.
● Then, updated value of RAUTO will
be 3302 – 2 = 3300.
● At memory address 3300, the
operand will be found.
1. Immediate Addressing Mode-

Syntax- # Expression
Examples-
● Load R1, #1000 is interpreted as R1 ← 1000

● ADD R2, #3 is interpreted as R2 ← [R2] + 3

2. Direct Addressing Mode-

Syntax- Constant

● Examples-

● Load R1, 1000 is interpreted as R1 ← [1000]

● ADD R2, 3 is interpreted as R2 ← [R2] + [3]
[Link] Direct Addressing
Mode-
Syntax- Rn or [Rn]

Examples-
● Load R1, R2 is interpreted as R1 ← [R2]

● ADD R1, R2 is interpreted as R1 ← [R1] + [R2]

4. Indirect Addressing Mode-

Syntax-
@Expression or @(Expression) or
(Expression)

Examples-
● Load R1, @1000 is interpreted as R1 ← [[1000]]
● ADD R1, @(1000) is interpreted as R1 ← [R1] + [[1000]]
● ADD R1, (1000) is interpreted as R1 ← [R1] + [[1000]]
[Link] Indirect Addressing Mode-

Syntax-
@Rn or @(Rn) or (Rn)

Examples-
Load R1, @R2 is interpreted as R1 ← [[R1]]
ADD R1, @(R2) is interpreted as R1 ← [R1] + [[R2]]
ADD R1, (R2) is interpreted as R1 ← [R1] + [[R2]]
6. Displacement Addressing Mode-

This addressing mode may be-

● Relative addressing mode

● Index addressing mode

● Base register addressing mode

● Syntax- disp (Rn)

6. Displacement Addressing Mode-

● Examples-

● ADD R1, 100(R2) is interpreted as R1 ←

[R1] + [100 + [R2]]
7. Auto-Increment Addressing Mode-

● Syntax- (Rn)+
● Examples-

● Load R1, (R2)+

is interpreted as R1 ← [[R2]] followed by R2 ← [R2] + d

● ADD R1, (R2)+

is interpreted as R1 ← [R1] + [[R2]] followed by R2 ←
[R2] + d
8. Auto-Decrement Addressing Mode-

Syntax-
-(Rn)
Examples-

● Load R1, -(R2) is interpreted as R2 ← [R2] – d followed

by R1 ← [[R2]]
● ADD R1, -(R2) is interpreted as R2 ← [R2] – d followed
by R1 ← [R1] + [[R2]]
Instruction set
An instruction is a set of codes that the computer
processor can understand. The code is usually in 1s
and 0s, or machine language. It contains instructions
or tasks that control the movement of bits and bytes
within the processor.
● Example of some instruction sets −

● ADD − Add two numbers together.

● JUMP − Jump to designated RAM address.

● LOAD − Load information from RAM to the CPU.