Chapter 5:
Internal memory
5.1 – Semiconductor Main Memmory
- Organization:
- DRAM and SRAM
- Types of ROM
- Chip Logic
- Chip Packaging
- Module Organization
- Interleaved Memory
Main Part:
5.1 SEMIICONDUCTOR MAIN MEMORY
First say: Early computers used ferromagnetic cores for memory, leading to the term "core
memory." Microelectronics have since replaced this with semiconductor chips, explored in
this section.
5.1.1 - Organization:
- Memory cells are the basic element of a semiconductor.
- All semiconductor memory cells share certain properties:
+ They exhibit two stable states, which can be used to present binary 1 and 0.
+ They are capable of being written into, to set the state.
+ They are capable of being read to sense the state.
- Describe the actives of a memory cell.
o Shows a memory cell with three terminals:
Select
Control
Sets or read the cell’s state
- The design and timing of the cell depend on the integrated circuit technology, but
for our purposes, cells can be selected for reading and writing.
5.1.1 - Dram and Sram:
- All memory types are random access, meaning individual memory words are
accessed via addressing logic
- Table 5.1 lists major memory types
+ RAM is the most common.
+ RAM allows easy and fast reading and writing via electrical signals.
+ The two main types of RAM in computers are DRAM and SRAM.
- Ram is divided into two types: Dynamic and static.
- Dynamic RAM (DRAM) stores data as charges on capacitors, with the presence or
absence of charge representing a binary 1 or 0. Since capacitors naturally
discharge, DRAM requires periodic refreshing to retain data.
-
- DRAM stores data as charges on capacitors, requiring periodic refresh due to
charge leakage. //
- A DRAM cell uses a transistor as a switch to read or write data. It's smaller,
cheaper, but slower than SRAM, making it ideal for main memory.
- SRAM, using flip-flop logic, holds data without refresh and is faster, making it
suitable for cache memory. Unlike DRAM, SRAM is fully digital and retains data as
long as power is supplied.
5.1.3 – Types of ROM:
ROM stores permanent, nonvolatile data that can only be read, not written.
PROM allows one-time writing after production, while EPROM can be erased with UV light and
rewritten.
EEPROM offers selective rewriting, and flash memory allows fast, block-level updates,
making it more flexible and efficient.
5.1.4 – Chip Logic:
Semiconductor memory is packaged in chips containing arrays of memory cells.
Key design considerations include speed, density, and cost, especially regarding the number
of bits read or written at once.
A 16-Mbit DRAM, for example, organizes data into four 2048 x 2048 arrays, processing 4 bits
at a time.
Addressing uses multiplexing, with 11 lines defining row and column addresses, while RAS
and CAS signals provide timing.
DRAMs require refresh operations by reading and rewriting data to prevent loss.
This design allows memory size to quadruple with each new chip generation.
5.1.5 – Chip Packaging:
Integrated circuits are packaged with pins for external connections. For example, an 8-Mbit
EPROM chip (1M x 8) has 32 pins, including:
Address lines (A0–A19): 20 pins needed for 1M words.
Data lines (D0–D7): 8 lines for output.
Power supply (Vcc) and ground (Vss) pins.
Chip enable (CE): Indicates address validity for the chip.
Program voltage (Vpp): Used during write operations.
In contrast, a 16-Mbit DRAM chip (4M x 4) has input/output data pins.
It features write enable (WE) and output enable (OE) pins to distinguish between read
and write operations.
5.1.6 – Module Organization:
Idf a RAM chip holds one bit per word, the number of chips equals the bits per word. For
256K 8-bit words, eight 256K x 1-bit chips are used, needing an 18-bit address.
For 1M words at 8 bits each, four columns of chips are employed, each with 256K words. This
configuration requires 20 address lines, with the lowest 18 routed to all chips and the
highest 2 selecting one of the columns.
5.1.7 – Interleaved Memory:
Main memory consists of DRAM chips organized into memory banks. With interleaved
memory, each bank can independently handle read or write requests, allowing a system
with K banks to service K requests simultaneously, thus boosting memory transfer rates by a
factor of K. Storing consecutive memory words in different banks further speeds up block
transfers. For more details, see Appendix G.