USN
LINGARAJAPPA ENGINEERINGCOLLEGE,BIDAR
ACA/R/ AcademicYear: 2025-26
Rev:00 Department of ECE Semester: IV
Date:28.03.2025 Section:-
TestNo:I Subject with code: BEC405C(OS)
CIE-I Question paper
Duration:1hr30min Max. Marks: 25
INSTRUCTIONS:Answer any one full question from each.
Q. No Question Statement RBTL CO PO Marks
Q1. What is an operating system? Explain the Goals of Os. L1 CO1 PO2 5
OR
Q2. List the operations of an Os. L2 CO1 PO1
5
Q3. Explain the different classes of operating system with primary concerns and key concepts. L3 CO1 PO3 5
OR
Q4. Explain different resource allocation techniques. L2 CO1 PO1 5
Q5. Explain efficiency and system performance. L2 CO1 PO2 5
OR
Q6. Give the facts of user convenience in an operating system. L2 CO2 PO1
5
Q7. What are the fundamental process states. With state transition diagram explain the state transition
for process. L2 CO2 PO2 5
OR
Q8. Explain different fields of process control block.. L2 CO2 PO1 5
Q9. What are the advantages of threads over process? Explain kernel level threads.
L3 CO2 PO2 5
OR
Q10. With the help of neat sketch explain the view of processor.
L3 CO2 PO1 5
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Dr. Sagarkumar B.
Design Of A Charge-Pump Based, Phase Locked Loop For Medical Application
Project Reference No.: 48S_BE_2309
College : Lingaraj Appa Engineering College, Bidar
Branch : Department of Electronics and Communication Engineering
Guide : Dr. Sagarkumar Buyya
Students : Mr. Sai Prassan
Mr. Vinayak Ghatge
Ms. Divya SB
Ms. Sandhyarani
Keywords: PLL, Cadense, VCO, CPPL
Introduction
The most versatile application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor,
networking, communication systems,and frequency synthesizers. Phase locked-loops (PLLs) are commonly used to generate well-
timed on-chip clocks in high performance digital systems. Modern wireless communication systems employ Phase Locked Loop
(PLL) mainly for synchronization, clock synthesis, skew and jitter reduction. Because of the increase in the speed of the circuit
operation, there is a need of a PLL circuit with faster locking ability. Many present communication systems operate in the GHz
frequency range. Hence there is a necessity of a PLL which must operate in the GHz range with less lock time. PLL is a mixed signal
circuit as its architecture involves both digital and analog signal processing units. The present work focuses on the redesign of a PLL
system using the 90 nm process technology (GPDK090 library) in CADENCE Virtuoso Analog Design Environment. Here a current
starved ring oscillator has been considered for its superior performance in form of its low chip area, low power consumption and
wide tunable frequency range. As the voltage-controlled oscillator (VCO) is the heart of the PLL, so the optimization of the VCO
circuit is also carried out using optimization technique. The charge pump with single stage differential amplifier topology gives us
best results as compared to other conventional-PLL.
Objectives:
This proposed project proposes the design of a low power frequency synthesizer PLL system that produces a
signal in GHz range with a reference input in MHz.
The proposed project is a low power charge pump phase-locked loop (CPPLL).
It combines various modern circuit techniques, whose main aim is to lower power consumption, while maintaining
good noise properties which makes this PLL a better fit for medical applications.
During the entire design, the following objectives will be met:
1. Design and implementation of Phase Frequency Detector.
2. Design and implementation of Charge Pump.
3. Design and implementation of VCO.
4. Design of a Divider.
5. Implementation of a complete PLL.
Problem Statement
The design and implementation of a charge pump based, Phase locked loop using CMOS 90nm technology for medical
applications.
Tools and Technologies Used
- Software: VM Ware
-Tool: Cadence Virtuoso
Methodology:
Figure 1: PLL Structure
The chosen architecture is the charge pump phase locked loop with frequency divided that uses a fixed, nonprogrammable
value. The block diagram of the PLL is shown in Figure below. It consists of a phase-frequency detector block (PFD) which
cooperates with a charge pump (CP) and produces a square wave with duty cycle proportional to the phase error between the
reference input (V_ref ) and the feedback output (V_fb). This signal is converted to DC value by a second order loop filer,
which consists of the charge pump and loop filter. The voltage V_ctrl is converted to current by the next block and Voltage
controlled oscillator (VCO) generates desired GHz output signal. Part of the output signal is fed back to the PFD through the
frequency divider, whose division ratio is set to different multiple values using various dividers. The overall PLL system is as
shown in the figure below The first block of the PLL system is the Phase Frequency Detector(PFD). Its main function is to
compare the phase and the frequency of the reference and the feedback signal coming from the divider, producing an “Up” or a
“Down” signal depending on if the reference signal is leading or lagging. The CP represents the charge pump, which receives
the “Up” or “Down” signal from the PFD. It charges or discharges the loop filter accordingly. An “Up” signal causes the upper
switch to switch on, causing the upper current source to charge the LF. If a “Down” signal is high, the bottom switch turns on
allowing the bottom current source to discharge the LF. The LF is a low-pass filter that serves the purpose of averaging out the
phase-error signal generated from the PFD and generating a control voltage (Vctrl) for the VCO. The PFD, the CP, and the LF
are connected and simulated together. Keeping the input and output phase in lock state also implies keeping the input and
output frequencies the same, thus a phase-locked loop can also track an input frequency. And by incorporating a frequency
divider, a PLL can generate a stable frequency that is a multiple of the input frequency. Thus we will be generating frequencies
using a reference signal that caters the need of medical applications.
Results and Conclusion:
Designing a low power PLL is very crucial in medical applications. For the medical band application, designing an PLL
that consumes minimal power is a challenging task. By using the concept of NAND based PFD, loop filter and VCO with
divider, the PLL has been designed. The design of low power ADPLL for medical based applications ensuring minimal
power consumption was the main objective of this work. Using the theory and circuits developed, a full low power PLL
was developed. The architecture was designed in the 90 nm CMOS process. Five objectives were met in the due course of
the entire project. In the first objective, a PFD circuit was designed, and its performance was assessed. In the second
objective, a charge pump was designed, third objective focused on the design of oscillators, fourth objective focused on
divider and finally fifth objective involved the integration of the entire blocks to get the full PLL for medical applications.
Future Scope:
The future scope of this project includes:
Power consumption can be further reduced by exploring alternative LC VCO and charge pump topologies.
Implementing synchronous counters and CML flip-flops in the divider can help minimize jitter in the divider path.
The PLL output frequency can be increased to a few more GHz, enhancing performance.
These improvements make the PLL a versatile block suitable for various communication-based applications
Working mode lvs Simulation/Study
The project involves the development of Simulation model
Signature of the course coordinator