Introduction to

HDL
VLSI DESIGN FLOW

The Y-chart consists of three major

domains:
• Behavioral domain
• Structural domain
• Geometrical layout domain.
RTL CODING FLOW
• RTL (Register Transfer Level) describes the data flow and control logic in terms of registers and
the transfer of data between them on clock edges.

Understand the Write the RTL Write the

Code Testbench
Specification

Implement on Synthesize the Simulate the

FPGA RTL Design

Program and
Debug
BEHAVIORAL, DATAFLOW, AND
STRUCTURAL MODELING IN VERILOG

Why Multiple Modeling Styles?

• Different abstraction levels help simplify design.

• Choice depends on:
 Designer's intent
 Reusability
 Simulation vs. Synthesis constraints
• Helps transition from algorithm → architecture → hardware
 BLOCKING STATEMENTS
The " = " represents a blocking procedural assignment.
• Evaluated and assigned in a single step.
• Execution flow within the procedure is blocked until the assignment is completed.
• Evaluations of concurrent statements in the same time step are blocked until the assignment is
completed.

Example:
NON-BLOCKING STATEMENTS
The " <= " token represents a non-blocking assignment.
• Evaluated and assigned in two steps:
a. The right-hand side is evaluated immediately.
b. The assignment to the left-hand side is postponed until all other evaluations in the current time
step are completed.
• Execution flow within the procedure continues until a timing control is encountered (flow is not
blocked).

Example:
BEHAVIORAL MODELING
• Describes the functionality of a circuit.
• Uses procedural blocks: always, initial.
• Abstracts away from gate-level implementation.
Example:

Keywords: if, case, for, while, always, initial

DATAFLOW MODELING
• Uses continuous assignments with assign.
• Focuses on how data moves between variables.
• Intermediate abstraction between behavioral and
structural.

Example:

Keywords: assign, operators (&, |, ~, etc.)

STRUCTURAL MODELING
• Describes how components (modules) are connected
together.
• Similar to schematic design using code.
• Useful when instantiating submodules or logic gates.

Example:

Keywords: module, instantiation, port mapping

 HOW TO WRITE A TESTBENCH IN VERILOG
What is a Testbench?
• A Verilog module used to verify the functionality of a design (DUT -
Design Under Test).
• Not synthesized; used only for simulation.

Key Components of a Testbench:

[Link] ports – testbenches don’t interact with external modules.
[Link] instantiation – instantiate the module you want to test.
[Link] generation – apply different inputs using initial blocks.
[Link] outputs – use $monitor, $display, or waveform viewers.
[Link] end – use $finish or $stop.
EXAMPLE:

• Use #delay to simulate time.

• Use $dumpfile/$dumpvars for waveform output (in
GTKWave).
• Use multiple initial blocks for better clarity (stimulus &
monitoring)

What does " timescale 1ns / 1ps " mean?

• 1ns: The time unit is 1 nanosecond. Delays like #10

mean 10ns.
• 1ps: The time precision is 1 picosecond. All timing
operations are rounded to the nearest picosecond.
Synthesizable Constructs in Verilog:
What Does "Synthesizable" Mean?
• Synthesizable Verilog refers to code that can be translated into Example of Synthesizable Code:
actual hardware gates and flip-flops by synthesis tools.
• These constructs are used to describe hardware behavior, not
just simulate it.
• Only synthesizable code can be implemented on an FPGA or
ASIC.

Common Synthesisable Constructs:

• always @(posedge clk) or @(negedge clk) — Sequential logic
• if, else, case — Conditional logic
• assign — Combinational logic (used with wire)
• reg, wire, input, output declarations
• for loops — With static bounds (must be fully unrollable)
• Bitwise and arithmetic operations: +, -, &, |, ^, <<, >>
Non-Synthesizable Constructs in Verilog:

What Does "Non-Synthesizable" Mean? Example of Non-Synthesizable Code:

• Non-synthesizable Verilog is used only for simulation and
testing.
• These constructs cannot be translated into real hardware and are
ignored during synthesis.

Common Non-Synthesizable Constructs:

• $display, $monitor, $finish, $stop — Simulation output and
control
• #delay — Time delays (not implementable in hardware)
• initial blocks — Used for testbench initialization
• File I/O operations — $readmemh, $fdisplay, $fopen, etc.
Sequential Circuits in Verilog:

What Are Sequential Circuits? Example of Sequential Circuits:

• Output depends on both the current input and the past inputs
(i.e., stored state).
• Require clock signals and storage elements: flip-flops or latches
Examples: Counters, Registers, State Machines.

Flip-Flop Example: D Flip-Flop

Combinational Circuits in Verilog:

What Are Combinational Circuits? Example of Combinational Circuits:

• Outputs depend only on the current inputs, not on any past
input or clock.
• Immediate logic operations like arithmetic and logic functions.
• Examples: Adders, Multiplexers, Decoders.

Full Adder Example

• A full adder takes three 1-bit inputs: A, B, and Carry-in (Cin), and
produces a 1-bit Sum and a Carry-out (Cout).
Common Data Types in Verilog:
1. wire
• Represents a combinational connection.
• Used to connect modules and assign values using assign.
• Cannot store values, only reflects the value driven on it.
2. reg
• Used to store values in sequential logic.
• Declared as reg, but doesn't imply a hardware register unless used in always
blocks.
3. parameter
• Used to define constant values that can be customized per module instance.
• Helps in configurable or reusable designs.
4. localparam
• Similar to parameter, but cannot be overridden during instantiation.
• Used for internal constants.
5. integer
• Used in testbenches or loops for counters or indexing.
• Not typically synthesized into hardware.
Verilog Code Using Common Data Types:

• Inside the original alu_example module, parameter

WIDTH = 8 is declared.
• In the top module, we override it using:

• This changes the bit-width of a, b, and out from 8 bits

(default) to 16 bits at instantiation time.
• The parameter WIDTH is customizable, and its value
can be overridden during instantiation.
• The localparam ZERO = 0 inside alu_example cannot
be changed externally — it's a fixed internal constant.
If-else Statements
Purpose:
• Conditional decision-making based on logic.
• Create priority-based logic.
• Used in both combinational and sequential circuits.

Example:
Case Statements
Purpose:
• Simplifies multi-way branching over if-else chains.
• Efficient mapping in hardware (e.g., LUTs, multiplexers).
• Ideal for finite state machines (FSMs).
• Great for implementing instruction decoders or ALUs.

Example:
While Loops
Purpose:
• Used in testbenches for simulation-only loops.
• Model indefinite waiting behavior (e.g., wait for a flag).
• Useful for stimulus generation or waveform monitoring.
• Allows verification of dynamic conditions during test.

Example:
Finite State Machines (FSMs) in FPGA
What is an FSM?
• A Finite State Machine is a digital circuit that transitions between a fixed set of states based on
inputs and clock cycles. It is widely used in control logic, protocol handling, data sequencing, and
timing-based logic.

Key Components of FSMs

• States: Named conditions representing current system behavior.
• Transitions: Movement from one state to another based on inputs.
• Inputs: Signals that influence state changes.
• Outputs: Signals determined by current state or transitions.
• Clock: FSM transitions occur on clock edges (synchronous).

FSM Types:
• Moore - Output depends only on the current state.
• Mealy - Output depends on state and input.
Example (Moore FSM)
(Continued code ….)
Example (Mealy FSM)
(Continued code ….)