Optimizing Low Side Gate Resistance for

Damping Phase Node Ringing of Synchronous

Buck Converter
Zhiyang Chen Isauro Amaro
Automotive & Power Group Automotive & Power Group
ON Semiconductor ON Semiconductor
Phoenix AZ USA Phoenix AZ USA

Abstract—This paper presents a method to optimize gate for optimizing gate resistance are derived based on
resistance of low side MOSFET in terms of damping parasitic network of capacitance, CGS, CGD, and CDS, and
phase node ringing for high efficiency synchronous buck parasitic package inductance, LD, LG and LS.,
converter. This method analyzes damping effect of low Experiment proves the optimized gate resistance helps
side gate resistance in the network of parasitic damping phase node ringing, while maintain high
capacitances of MOSFET die and parasitic inductances of converter efficiency.
MOSFET package. Optimization equations for low side
gate resistance are derived based on parasitic inductances II. OPTIMIZING LOW SIDE GATE RESISTANCE IN
and capacitances. Experiment proves the validity of this SYNCHRONOUS BUCK CONVERTER
optimization design for low side gate resistance.
Figure 1 shows a synchronous buck converter with
I. INTRODUCTION parasitics in both high side and low side MOSFET
switches.
Phase node ringing of synchronous buck converter is
caused by parasitic switching loop inductance and
parasitic capacitance of power devices [1]. The ringing
may lead to electrical over stress of high side and low
side MOSFETs, shorting through, or failure of system in
EMC regulation. Therefore, ringing of phase node in
synchronous buck converter must be controlled.
Many methods have been developed to control phase
node ringing for synchronous buck converter [2]. One
method is using large high side gate resistance, so that
turn-on of high side MOSFET is slowed down. This Figure 1 Synchronous buck converter with parasitic capacitances
method could reduce phase node ringing effectively. and inductances
However, it reduces efficiency of synchronous buck LSH and LSL are package source inductance at high
converter significantly due to significantly increased side and low side MOSFET [5]. Usually package
switching power loss of high side MOSFET. In the same inductance at drain side is much smaller than source
idea, some other methods take advantages of source inductance. Therefore, drain inductance is neglected in
inductance of high side MOSFET or boost resistance of this paper. Ltrail is inductance of PCB trail in switching
high side driver to slow down switching speed of high loop.
side MOSFET to control phase node ringing [3][4].
These methods all result in low converter efficiency.
Another method is to use RC snubber connected
between phase node and ground to damping phase node
ringing. This is the method commonly used in high
efficiency synchronous buck converter. However, RC
snubber still consumes energy during switching. The
higher capacitance is, the more energy consumed in the
RC snubber.
In this paper, an optimized design of low side gate
resistance is proposed in terms of damping phase node Figure 2 Turn-on Ringing Circuit of Synchronous buck converter
ringing. Analytic expressions are derived for low side Figure 2 shows equivalent turn-on ringing circuit of
gate resistance to damp phase node ringing, while synchronous buck converter. In high efficiency
maintain high converter efficiency. Analytic expressions
synchronous buck converter, on-state resistance of high X CDSL ⋅ XCGDL
side MOSFET is usually less than 10mΩ, which is too XCDL =
XCGSL + XCGDL + XCDSL
small to damping any phase node ringing. Therefore, on-
state resistance is not shown in Figure 2. In fact, the real X CDSL ⋅ XCGSL
X CSL =
damping resistance of phase node ringing is gate XCGSL + X CGDL + XCDSL
resistance of high side MOSFET and low side
MOSFET. To optimize damping effect of phase node 1
Here, X Ci = , i=GL, DL, SL, GSL, DSL,
ringing, it is equivalent to maximizing ratio of current ω ⋅ Ci
flowing through gate resistance to total ringing current. GDL.
For the reason that high side gate resistance has strong
effect on efficiency of synchronous buck converter, only
gate resistance of low side MOSFET is optimized in
terms of damping phase node ringing in this paper.
In Figure 2, gate branch of high side MOSFET has
three components, RGH, LGH,and Cissh. Impedance of gate
branch of high side MOSFET is shown in equation (1).
⎛ 1 ⎞
XGH = RGH + j⎜⎜ω ⋅ LGH − ⎟ (1)
⎝ ω ⋅ CISSH ⎟⎠ Figure 3 Equivalent Turn-on Ringing Circuit of low side MOSFET
Here, ringing frequency is expressed by equation (2). Equivalent damping resistance of low side ReqL is
determined also by ratio of current passing through RGL
1 to total ringing current. Impedance of gate branch CGL,
ω≈ (2) LGL and RGL and source branch CSL and LSL in Figure 3
(L SH + L SL + LTRAIL ) ⋅ (C GDL + C DSL )
are expressed by equation (6) and (7).
Then the total impedance of high side MOSFET is
expressed by equation (3). ⎛ 1 ⎞
XGL = RGL + j⎜⎜ω ⋅ LGL − ⎟ (6)
X ⋅ ω ⋅ LSH ⋅ j ⎝ ω ⋅ CGL ⎟⎠
XH = GH (3)
X GH + ω ⋅ LSH ⋅ j ⎛ 1 ⎞
X SL = j⎜⎜ω ⋅ LSL − ⎟ (7)
The equivalent damping resistance of high side gate
⎝ ω ⋅ CSL ⎟⎠
resistance ReqH is determined by the ratio of current
passing through RGH to total ringing current. The higher Then the total impedance from N1 to ground is
ratio of current pass through RGH, the higher ratio of RG expressed by equation (8).
contributes to total damping resistance. The equivalent X GL ⋅ X SL
damping resistance of high side gate resistance RGH is X N1 = (8)
X GL + X SL
derived and expressed by equation (4). The equivalent damping resistance of low side
⎛ 1 ⎞
2 MOSFET is therefore expressed by equation (9).
⎜ ⎟ 2 2
⎜ X ⎟ ⎛ jωLSH ⎞ ⎛ 1 ⎞
ReqH = RGH × ⎜ GH ⎟ = RGH ⋅⎜ ⎟ ⎜ ⎟
⎜ X + jωLSH ⎟ (4) ⎜ X ⎟ ⎛ ⎞
2
⎜ 1 ⎟ ⎝ ⎠ X SL
⎟ = RGL ⋅ ⎜⎜ ⎟
GH
Req = RGL ⋅ ⎜ GL
⎜ X ⎟ ⎜ 1 ⎟ X + X SL ⎟
⎝ H ⎠ ⎝ GL ⎠
⎜ X ⎟
⎝ N1 ⎠
Here, X means absolute value of a complex ⎛ 1 ⎞
2
(9)
⎜ ω ⋅ LSL − ⎟
⎜ ω CSL ⎟⎠
number. = ⎝ ⋅
2
In order to have equivalent damping resistance of ⎡ 1 1 ⎤
⎢ω ⋅ LGL − + ω ⋅ LSL − ⎥
gate resistance in low side MOSFET, delta connected ⎣ ω ⋅ CGL ω ⋅ CSL ⎦
RGL +
parasitic capacitances, CGSL, CGDL, CDSL, are first RGL
transformed to star connection capacitances CGL, CDL, Final equivalent ringing circuit of synchronous buck
CSL. Turn-on ringing circuit of low side MOSFET is converter at high side turn-on is shown in Figure 4.
then transformed into circuit in Figure 3. Impedances of
CGL, CSL, and CDL in Figure 3 are expressed by equation
(5).
XCGSL ⋅ X CGDL
XCGL = (5)
XCGSL + X CGDL + XCDSL
 ReqH LLOOP synchronous buck converter under test; driver board is
Phase
driver for high side and low side MOSFETs. Here, the
Node driver is NCP5901 with 12V driving voltage, which is a
commonly used driver for application in computing
ReqL devices.
DC

COSSL

Figure 4 Equivalent turn-on Ringing Circuit

Here, COSSL is output capacitance of low side
MOSFET. Loop inductance LLOOP is expressed by
equation (10).
LLOOP ≈ LSH + LSL + LTRAIL (10)
Damping time constant of circuit in Figure 4 is
expressed by equation (11).
2 ⋅ LTRAIL
τ ≈ (11)
ReqH + ReqL Figure 5 experiment setup for measuring phase node ringing
Schematic circuit of the experiment setup is shown
A. Maximize equivalent damping resistance in Figure 6. Here, all the parasitic capacitances and
Obviously, the equivalent damping resistant in inductances, like gate inductance and source inductance,
equation (9) has maximum value at the condition are included in package of high side and low side
expressed by equation (12). MOSFET. Gate resistance of high side and low side
MOSFET are also built in MOSFET package. In
1 1 experiment, the minimum gate resistance is the built-in
RGL = ω ⋅ LGL − + ω ⋅ LSL − (12) gate resistance.
ω ⋅ CGL ω ⋅ C SL
Under the condition of equation (12), the maximum In order to verify the optimized equivalent damping
equivalent damping resistance is expressed by equation resistance, waveform of phase node is first measured
(13). without any external gate resistance using driver
2
NCP5901. Then 0.2Ω external gate resistance is
⎛ 1 ⎞ connected in series with built-in gate resistance, so that
⎜ ω ⋅ LSL − ⎟
⎜ ω ⋅ C SL ⎟⎠ the equivalent damping resistance is varied from its
ReqL − max = ⎝ (13)
1 1 original value. As a consequence, the damping time
2 ⋅ ω ⋅ LGL − + ω ⋅ LSL −
ω ⋅ CGL ω ⋅ C SL constant of phase node ringing would be increased, if
To build in a gate resistance for low side MOSFET equivalent damping resistance is reduced, or be
in terms of suppressing phase node ringing, the value of decreased, if equivalent damping resistance is increased.
gate resistor must not exceed the value given by In the third step, a small capacitance is connected
equation (12). Otherwise, gate resistance will reduce between gate and source of low side MOSFET, so that
damping characteristics of phase node ringing and the driver sinking resistance is reduced by the external
reduce converter efficiency due to slower turn-on and gate source capacitance. This method varies equivalent
turn-off of low side MOSFET. Even worse, large gate damping resistance and damping time constant of phase
resistance of low side gate resistance may turn-on low node ringing too.
side MOSFET because of phase node ringing, which The specific values of parameters in Figure 6 are:
results in shorting through. Or large gate resistance of LL=1nH, RLL=2mΩ, Cout=88uF, Vout=1.2V,
low side MOSFET may take long time to turn-off low Vin=12V, fs=500kHz. In experiment, high side
side MOSFET, which may results in low side MOSFET MOSFET is NTMFS4941 for all measurements and low
is still on when high side MOSFET is turned-on. side MOSFETs are NTMFS4836, NTMFS4835 and
NTMFS4834 respectively.
III. EXPRRINMENT RESULTS AND DISCUSSIONS
Experiments are conducted to validate the damping
characteristics of low side MOSFET and optimized
damping resistance. Here the test setup has three parts:
mother board, test board and driver board. Mother board
provides stable input power and output power to
synchronous buck converter; test board is the
 Equivalent Damping Resistance of NTMFS4836, NTMFS4835 and
NTMFS4834
0.12

0.1

Equivalent Resistance (Ω)

0.08

0.06

Figure 6 circuit of experiment setup

All the switching waveforms are measured using the 0.04
Equivalent Rg of NTMFS3836
same board and all the devices have the same package. Equivalent RG of NTMFS4835
0.02
Therefore, switching loop inductance is about the same Equivalent RG of NTMFS4834
for all the experiments. From ringing period, the 0
switching loop inductance is calculated to be 2~2.5nH. 0 1 2 3 4 5
LS Gate Resistance (Ω)
Parasitic capacitances and inductances of
Figure 7 Equivalent damping resistance of NTMFS4836 at various
MOSFETs, NTMFS4941, NTMFS4836, NTMFS4835 gate resistance
and NTMFS4834, are listed in Table I.
TABLE II EQUIVALENT DAMPING RESISTANCE OF
TABLE I PARASITIC CAPACITANCES AND INDUCTANCES OF NTMFS4941+NTMFS4836 PAIR
NTMFS4836, NTMFS4835, NTMFS4834 AND NTMFS4941
RG=1.2Ω RG=2.0Ω RG=2.2Ω
NTMFS NTMFS NTMFS NTMFS
4936 4835 4834 4941 NTMFS4941 Req (Ω) 0.065 0.065 0.065
CISS(PF) 2677 3100 4500 1650 NTMFS4836 Req (Ω) 0.09 0.096 0.094
COSS(PF) 565 670 960 570 Total Req (Ω) 0.155 0.161 0.159
CRSS(PF) 307 360 500 17 Damping Time
28.3 27.3 27.6
LS(nH) 0.65 0.65 0.65 0.93 constant (ns)
LG(nH) 1.84 1.84 1.84 1.84 Here, gate resistance of low side MOSFET is
Built-in Rg (Ω) 1.2 1.3 1.4 1.1 changed varied from 1.2Ω to 2.2Ω. Phase node damping
Based on ringing frequency and parasitic inductance time constant is first decreased from 28.3ns to 27.3ns,
and capacitances in Table I, equivalent damping and after that, damping time constant increases from
resistance of low side MOSFETs, NTMFS4836, 27.3ns to 27.6ns, which means that equivalent damping
NTMFS4935 and NTMFS4834, are plotted in Figure 7 resistance of low side MOSFET first increase and later
based on equation (9). Obviously, equivalent damping decreases.
resistance of low side MOSFET is maximized when
gate resistance is around 2Ω. Gate resistance of low side TABLE III EQUIVALENT DAMPING RESISTANCE OF
MOSFET greater than 2Ω does not help damping phase NTMFS4941+NTMFS4835 PAIR
node ringing. RG=1.3Ω RG=2.1Ω RG=2.3Ω
Because of sinking resistance of low side driver, NTMFS4941 Req (Ω) 0.069 0.069 0.069
which is typically around 0.8Ω for NCP5901, gate NTMFS4835 Req (Ω) 0.084 0.094 0.094
resistance of low side MOSFET is the sum of built-in Total Req (Ω) 0.153 0.163 0.163
gate resistance of MOSFET and driver sinking Damping Time
28.70 27.00 27.00
constant (ns)
resistance. Also, the gate inductance of low side is the
Here, gate resistance of NTMFS4835 is increased
sum of parasitic gate inductance of low side MOSFET
from 1.3Ω to 2.3Ω. Equivalent damping resistance of
and inductance of PCB trail connecting low side driver
NTMFS4835 increases first then stays stable, which
and MOSFET. The PCB trail inductance of driver board
means that 2.3Ω gate resistance is the optimized gate
is limited around 0.1~0.3nH because of optimized
resistance for NTMFS4835. If gate resistance is higher
multilayer design.
than 2.3Ω, damping effect of NTMFS4835 would be
Specific data for damping resistance for MOSFET decreased.
pairs, NTMFS4941+NTMFS4836, NTMFS4941+
NTMFS4835, NTMFS4941+NTMFS4834, are TABLE IV EQUIVALENT DAMPING RESISTANCE OF
calculated in Table II, Table III, and Table IV. NTMFS4941+NTMFS4834 PAIR

Equivalent damping resistance of NTMFS4941 in RG=1.4Ω RG=2.2Ω

Table II, Table III, and Table IV are calculated from NTMFS4941 Req (Ω) 0.089 0.089
equation (4). Equivalent damping resistance of NTMFS4834 Req (Ω) 0.058 0.071
NTMFS4941 does not change when gate resistance of Total Req (Ω) 0.147 0.16
Damping Time
low side MOSFET varies. It changes only when ringing constant (ns)
33.00 30.00
frequency changes.
 Here, gate resistance of NTMFS4834 is increased Phase Node Waveform and Predicted Damping Time
from 1.4Ω to 2.2Ω. Equivalent damping resistance is Constant @ RG=2.2Ω
30
increased. Experiment of NTMFS4834 at gate resistance
higher than 2.2Ω is not shown for the reason that 25 PhaseNodeVoltage
Tau=27.6ns
shorting through is observed in experiment in this 20
condition.

Voltage (V)
15
Figure 8 to Figure 14 are experiment phase node
waveforms with high side MOSFET NTMFS4941 and 10

low side MOSFET NTMFS4836, NTMFS4835, and

5
NTMFS4834 respectively. These three low side devices
have significant ringing in phase node during high side 0
turn-on. Exponential damping curves with damping time -1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07

constant in Table II, Table III, and Table IV are plotted -5

Time (s)
in Figure 8 to Figure 14. It is clearly shown that the
Figure 10 phase node waveform of NTMFS4941+NTMFS4836 and
predicted damping constants precisely fit experiment predicted damping time constant at gate resistance @ RG=2.2Ω
data.
Phase Node Waveform and Predicted Damping Time
Constant @ RG=1.3Ω
Phase Node Waveform and Predicted Damping Time 30
Constant @ RG=1.2Ω
30
25 PhaseNodeVoltage
PhaseNodeVoltage
25 Tau=28.7ns
Tau=28.3ns 20

20
Voltage (V) 15
Voltage (V)

15
10
10
5
5
0
0 -1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07
-1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07 -5
-5 Time (s)
Time (s)
Figure 11 phase node waveform of NTMFS4941+NTMFS4835 and
Figure 8 phase node waveform of NTMFS4941+NTMFS4836 and predicted damping time constant at gate resistance @ RG=1.3Ω
predicted damping time constant @ RG=1.2Ω Phase Node Waveform and Predicted Damping Time
Constant @ RG=2.1Ω
30
Phase Node Waveform and Predicted Damping Time
Constant @ RG=2.0Ω
30 25 PhaseNodeVoltage
Tau=27ns
25 PhaseNodeVoltage 20

Tau=27.3ns
Voltage (V)

20 15
Voltage (V)

15 10

10 5

5 0
-1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07

0 -5
-1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07 Time (s)
-5 Figure 12 phase node waveform of NTMFS4941+NTMFS4835 and
Time (s)
predicted damping time constant at gate resistance @ RG=2.1Ω
Figure 9 phase node waveform of NTMFS4941+NTMFS4836 and
predicted damping time constant @ RG=2.0
 Phase Node Waveform and Predicted Damping Time Efficiency vs Gate Resistance
Constant @RG=1.4Ω 100
25
98 RG=1.2Ω
PhaseNodeVoltage RG=2.0Ω
20 96 RG=2.2Ω
Tau=33ns
94
15
Voltage (V)

92

Efficiency (%)
10 90

88
5
86

84
0
-1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07
82

-5 80
Time (s) 0 5 10 15 20 25
Gate Resistance (Ω)
Figure 13 phase node waveform of NTMFS4941+NTMFS4834 and
predicted damping time constant at gate resistance@ RG=1.4Ω Figure 15 Efficiency curves of NTMFS4836 at various gate
resistance
Phase Node Waveform and Predicted Damping Time
Constant @RG=2.2Ω IV. CONCLUSION
25
An optimized design of low side gate resistance is
20
PhaseNodeVoltage proposed in terms of damping phase node ringing for
Tau=30ns
synchronous buck converter. Analytic optimization
15 expressions are derived for low side gate resistance in
Voltage (V)

terms of damp phase node ringing. Experiment proves

10 the optimized gate resistance helps improve damping
phase node ringing, while maintain high converter
5
efficiency
0
-1.00E-08 1.00E-08 3.00E-08 5.00E-08 7.00E-08 9.00E-08 1.10E-07 1.30E-07 1.50E-07

-5 REFERENCES
Time (s)
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Efficiency of synchronous buck converter with International
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[Link]
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Boroyevich, D.; Burgos, R.; Power Electronics Conference
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Experiment results show that efficiency curves of
synchronous buck converter is not sensitive to low side
gate resistance. This is because that switching of low
side MOSFET is mainly zero voltage switching. The
slightly difference in efficiency curves is in light load
condition, where output power is low and, therefore,
slight difference in driver loss and switching loss of low
side MOSFET could make difference in total efficiency
curves.