8085 Microprocessor – Complete Explanation

1️⃣ Introduction

• Manufacturer: Intel
• Year Introduced: 1976
• Word Size: 8-bit (iska matlab ek time me 8 bits data process karta hai)
• Address Bus Size: 16-bit → Maximum 64 KB memory address kar sakta hai.
• Power Supply: +5V DC
• Clock Speed: ~3 MHz (basic model)

2️⃣ Features of 8085

1. 8-bit data bus – Ek time me 1 byte process.

2. 16-bit address bus – 0x0000 to 0xFFFF address space (64 KB memory).
3. 74 instructions & 246 opcodes – Instructions ka set jise wo execute kar sakta hai.
4. Multiplexed Address/Data Bus – AD0–AD7 lines address aur data dono ka kaam karte hain (time
sharing).
5. 5 Flags – Carry, Zero, Sign, Parity, Auxiliary Carry.
6. Serial communication pins – SID, SOD.
7. Interrupt System – 5 hardware interrupts (TRAP, RST7.5, RST6.5, RST5.5, INTR).
8. Single +5V power supply (no extra voltage required like 8080).

3️⃣ Architecture of 8085

Main blocks:

1. Accumulator (A Register) – Special register for ALU operations.

2. General Purpose Registers – B, C, D, E, H, L (paired as BC, DE, HL).
3. Program Counter (PC) – Next instruction ka address store karta hai.
4. Stack Pointer (SP) – Stack memory ka address.
5. Instruction Register & Decoder – Instruction ko read & understand karta hai.
6. Arithmetic Logic Unit (ALU) – Arithmetic & logical operations karta hai.
7. Flag Register – Result ke status ko store karta hai.
8. Timing & Control Unit – Synchronization ke liye.
9. Interrupt Control – Interrupts manage karta hai.
10. Serial I/O Control – Serial data communication.

4️⃣ Registers in 8085

Register Size Function

Accumulator (A) 8-bit ALU ka main register

B, C, D, E, H, L 8-bit each General purpose, register pairs banake use

Program Counter 16-bit Next instruction ka address

Stack Pointer 16-bit Stack ka top address

Flag Register 8-bit Carry, Zero, Sign, Parity, AC flags

5️⃣ Flags in 8085

 1. Sign Flag (S) – Negative result → 1, positive → 0
2. Zero Flag (Z) – Result zero → 1
3. Auxiliary Carry (AC) – Lower nibble carry
4. Parity Flag (P) – Even parity → 1, Odd parity → 0
5. Carry Flag (CY) – Final carry/borrow

6️⃣ Pin Diagram of 8085

• 40 pins total
• Important groups:
o Address Bus: A8–A15 (pure address), AD0–AD7 (multiplexed address/data)
o Control Signals: ALE, RD, WR, IO/M
o Power: Vcc (+5V), GND
o Interrupts: TRAP, RST7.5, RST6.5, RST5.5, INTR
o Clock: X1, X2, CLK OUT
o Serial: SID, SOD
o Reset: RESET IN, RESET OUT

7️⃣ Working Principle

1. Fetch – Instruction memory se laata hai (Program Counter ka address use karke).
2. Decode – Instruction ko decode karta hai.
3. Execute – ALU & registers use karke instruction execute hota hai.
4. Update PC – Next instruction ka address load hota hai.

8️⃣ Applications of 8085

• Small computing devices

• Traffic light control
• Washing machines (old models)
• Educational kits
• Signal processing experiments

🌸 8085 Microprocessor Pin Functions (40 Pins) 🌸

Pin No. Name Function

1, 2 X1, X2 Crystal oscillator connect karne ke liye (clock input).

3 RESET OUT Connected devices ko reset karta hai jab processor reset hota hai.

4 SOD Serial Output Data – data ko serially bhejne ke liye.

5 SID Serial Input Data – data ko serially receive karne ke liye.

6 TRAP Non-maskable, highest priority interrupt.

7 RST 7.5 Maskable interrupt (2nd highest priority).

8 RST 6.5 Maskable interrupt.

9 RST 5.5 Maskable interrupt.

Pin No. Name Function

10 INTR General interrupt request line.

11 INTA Interrupt Acknowledge signal.

12–19 AD0–AD7 Multiplexed Address/Data bus (lower order address A0–A7 or Data D0–D7).

20 Vss Ground (0V).

21–28 A8–A15 Higher order Address bus lines (for 16-bit address).

29 S0 Status signal (operation identify karne ke liye).

30 WR̅ Write signal (memory/I/O me data likhne ke liye).

31 RD̅ Read signal (memory/I/O se data read karne ke liye).

32 Vpp +12V programming supply (rarely used).

33 S1 Status signal (operation identify karne ke liye).

34 IO/M̅ Select karta hai operation memory ke liye hai ya I/O device ke liye.

35 READY Batata hai ki peripheral/memory ready hai ya nahi (CPU wait kar sakta hai).

36 RESET IN CPU ko reset karta hai, program counter = 0000h.

37 CLK (out) Clock output to synchronize external devices.

38 HLDA Hold Acknowledge (DMA ke liye).

39 HOLD External device memory access request (DMA ke liye).

40 Vcc +5V power supply.

🌸 SIM – Set Interrupt Mask 🌸

Full form: Set Interrupt Mask

Purpose:

1. Kuch interrupts (RST7.5, RST6.5, RST5.5) ko enable/disable (mask) karna.

2. Serial Output Data (SOD) line ko control karna.

Kaise kaam karta hai?

• Jab hum SIM instruction execute karte hain, tab Accumulator (A) ka ek control byte load hota hai.
• Accumulator ke har ek bit ka alag meaning hota hai (D0–D7).
 Accumulator Bit Format for SIM

Bit Name Function

D7 SOD Serial Output Data bit (SOD pin pe data bhejne ke liye).

D6 SOE Serial Output Enable (1 = enable SOD).

D5 X Not used.

D4 R7.5 Reset RST7.5 flip-flop (1 = reset pending RST7.5).

D3 MSE Mask Set Enable (1 = niche ke D2–D0 bits ko consider karega).

D2 M7.5 Mask RST7.5 (1 = disable/mask, 0 = enable).

D1 M6.5 Mask RST6.5 (1 = disable/mask, 0 = enable).

D0 M5.5 Mask RST5.5 (1 = disable/mask, 0 = enable).

D3 = MSE (Mask Set Enable) → ye ek “switch” hai, bina iske D0–D2 kaam hi nahi karenge

RIM – Read Interrupt Mask

Full form: Read Interrupt Mask

Purpose:

1. Ye interrupts ki status check karta hai – kaun enabled hai, kaun disabled.
2. Ye pending interrupts (jo request bhej rahe hain) ko bhi check karta hai.
3. Ye Serial Input Data (SID) line ka status bhi read karta hai.

Matlab, SIM se hum set karte hain, aur RIM se hum status read karte hain

RIM Execution ka Process

• Jab hum RIM execute karte hain,

o Accumulator (A) me ek byte load hota hai
o Har bit ka ek alag meaning hota hai (D0–D7).

Accumulator Bit Format for RIM

Bit Name Function

D7 SID Serial Input Data line ka status (1 = High, 0 = Low).

D6 Interrupt IE Interrupt Enable status (1 = Enabled, 0 = Disabled).

Bit Name Function

D5 R7.5 RST7.5 interrupt ka status (1 = Request pending).

D4 R6.5 RST6.5 interrupt ka status.

D3 R5.5 RST5.5 interrupt ka status.

D2 M7.5 Mask status of RST7.5 (1 = Masked/Disabled).

D1 M6.5 Mask status of RST6.5 (1 = Masked/Disabled).

D0 M5.5 Mask status of RST5.5 (1 = Masked/Disabled).

Easy Example for You

RIM

• Execution ke baad Accumulator me ek byte aayega

• Us byte ke bits read karke pata chalega:
o Kaunse interrupts request kar rahe hain
o Kaunse interrupts enabled ya disabled hain
o Serial Input Data line pe kya status hai

1. Timing Diagram kya hota hai?

• Timing diagram ek graph hota hai jo dikhata hai ki 8085 microprocessor ke control signals,
address/data lines aur clock pulses ka timing relation kya hai jab koi instruction execute hota hai.
• Matlab: kis time pe kaunsa signal HIGH hai, kaunsa LOW hai, aur kaunsa kaam ho raha hai.

2. Important Terms

(a) T-state (T1, T2, T3...)

• Ek clock period ko T-state kehte hain.

• Jaise T1 → first clock cycle, T2 → second clock cycle.

(b) Machine Cycle

• Ek basic operation (jaise memory read, memory write, opcode fetch) complete hone mein jitna time
lagta hai usko machine cycle kehte hain.
• Example:
o Opcode Fetch (OF)
o Memory Read (MR)
 o Memory Write (MW)
o I/O Read, I/O Write

(c) Control Signals

• ALE (Address Latch Enable) → Lower address ko lock karne ke liye (T1 mein HIGH hota hai).
• RD̅ → Low hone par data read hota hai.
• WR̅ → Low hone par data write hota hai.
• IO/M̅ → Batata hai ki operation Memory ka hai ya I/O ka.
o 0 = Memory operation
o 1 = I/O operation

(d) S1, S0

• Status lines jo batati hain kaunsa machine cycle chal raha hai.
o 1 1 → Opcode Fetch
o 1 0 → Memory Read
o 0 1 → Memory Write

3. 8085 Execution ke Phases

Phase 1: Fetch Cycle

• Instruction ka opcode memory se laaya jata hai.

• Steps:
1. T1 → Address bus pe address bhejna + ALE HIGH.
2. T2–T3 → RD̅ LOW → Opcode memory se read hota hai.
3. T4 → Internal decoding (agar zaroorat ho).

Phase 2: Execute Cycle

• Opcode ke according instruction execute hoti hai (Memory Read/Write ya I/O operation).

4. Timing Diagram Banane ke Steps

1. Horizontal axis → T1, T2, T3 … likho (Clock cycles).

2. Vertical signals → ALE, RD̅, WR̅, IO/M̅, S1, S0 aur Data/Address lines.
3. Clock → Sabse pehle Clock pulses draw karo.
4. ALE → T1 mein HIGH pulse banao (address latch ke liye).
5. Address/Data line → T1 mein Address, baaki cycles mein Data show karo.
6. RD̅/WR̅ → Jab read/write hoga tab LOW pulse draw karo.
7. S1, S0 → Table ke according values set karo.
1. Introduction – Intel 8255

Intel 8255 ek Programmable Peripheral Interface (PPI) hai jo microprocessor ke saath I/O devices ko
connect karne ke liye use hota hai.

• Ye basically ek bridge ka kaam karta hai CPU aur external devices ke beech.
• Ye microprocessor ki speed aur external devices ki speed ke beech ka gap fill karta hai.
• Mostly 8085 aur 8086 ke saath use hota hai.

2. Features of 8255

• 3 Independent I/O ports: Port A, Port B, Port C

• 24 I/O pins total → 8-8 pins har port ke liye
• Har port ko input ya output mode mein program kiya ja sakta hai
• Programmable control word se operation set hota hai
• Modes of operation:
o Mode 0: Simple I/O
o Mode 1: Strobed I/O (Handshaking)
o Mode 2: Bidirectional I/O

3. 8255 Architecture

8255 ke andar 3 main ports aur ek control register hota hai:

1. Port A (PA0–PA7):
o 8-bit input/output port
o Mode 0, 1, 2 mein kaam kar sakta hai
2. Port B (PB0–PB7):
o 8-bit input/output port
o Mode 0 aur 1 mein kaam kar sakta hai
3. Port C (PC0–PC7):
o 8-bit port, jisko 2 parts mein divide kiya gaya hai:
▪ PC0–PC3 → Lower
▪ PC4–PC7 → Upper
o Control aur handshaking signals ke liye bhi use hota hai
4. Control Register:
o Isme Control Word likha jata hai jo modes aur ports ko define karta hai

4. Control Word Format

Control word ek 8-bit instruction hai jo CPU 8255 ko deta hai taaki wo apna mode aur port direction set kare.

Example:

D7 D6 D5 D4 D3 D2 D1 D0
1 A1 A0 M2 M1 B C D

• D7 = 1 → Control word set mode ke liye hai

• Port direction: 1 → Input, 0 → Output
 • Modes define karne ke liye bits hoti hain

5. Modes of Operation

(a) Mode 0: Simple I/O

• Basic Input/Output operation

• No handshaking, no interrupt
• All ports → independent input/output

(b) Mode 1: Strobed I/O (Handshaking mode)

• Handshaking signals ke saath data transfer hota hai

• Synchronization ke liye Port C ke kuch bits use hote hain

(c) Mode 2: Bidirectional I/O

• Port A → bidirectional data transfer

• Ek hi port se data input/output dono hota hai
• Handshaking ke signals bhi use hote hain

6. Applications of 8255

• Keyboards aur display interfacing

• ADC (Analog to Digital Converter) aur DAC (Digital to Analog Converter)
• Stepper motor control
• Traffic light control
• Microprocessor based measurement systems

7. Example Control Word

Agar hume chahiye:

• Port A → Output mode

• Port B → Input mode
• Mode 0 mein

To control word hoga: 10000010 → Hex me: 82H

latch ka matlab simple shabdon mein ye hai ki data ko hold karke rakhna, jab tak koi naya data na aa jaye.
1. Latching ka concept

• Jab microprocessor ek data bhejta hai Port A/B/C par, to ye data turant external device ko nahi bheja
jata.
• Pehle ye data latch (ek temporary storage) me store hota hai.
• Ye latch data ko hold karke rakhta hai taaki output device us data ko use kar sake, bina data ke change
hone ki tension ke.
• Naya data aane par purana data replace ho jata hai.

2. Output me latch kyu chahiye?

• Output devices (like LEDs, display) ko stable data chahiye.

• Agar latch nahi hoga to jaise hi microprocessor next instruction execute karega, output data badal sakta
hai aur device confuse ho jayega.
• Latch data ko stable rakhta hai jab tak microprocessor naya data nahi deta.

3. Input me latch kyu nahi hota?

• Input devices (like switches) ka data microprocessor read karta hai.

• Data continuously change ho sakta hai (switch press/release).
• Isliye processor ko hamesha latest data read karna padta hai, isliye input me latch use nahi hota.

4. Example

• Suppose microprocessor ne Port A pe 10101010 bheja hai.

• Ye data pehle latch me store hoga → phir LED ya display tak jaayega.
• Jab tak naya data nahi aata, LEDs wahi pattern dikhayengi.

1. Interfacing of 8255 with 8085

• 8085 microprocessor ke saath 8255 PPI (Programmable Peripheral Interface) ko connect karne ka
purpose hota hai peripheral devices (like keyboard, display, sensors) ko microprocessor ke saath
interface karna.
• 8255 ke andar 3 I/O ports (Port A, Port B, Port C) hote hain aur ek Control Register hota hai.
• Microprocessor inko address aur control signals ke through select karta hai aur data bus ke through
data transfer hota hai.

2. Address/Data Demultiplexing

8085 microprocessor ke AD0–AD7 lines multiplexed hoti hain, matlab ye dono kaam karti hain:

• Lower 8-bit Address (A0–A7)

• Data (D0–D7)
Isko demultiplex karne ke liye ek Latch (jaise 74LS373) use kiya jata hai.

• ALE (Address Latch Enable) signal se address ko alag karke data ko alag kiya jata hai.
• Isse hume A0, A1 signals milte hain jo 8255 ke registers select karne me help karte hain.

3. Chip Select (CS) using Decoder

• 8085 ke A2–A7 lines ko ek Decoder (3-to-8 or 4-to-16) se connect kiya jata hai.
• Decoder ka output CS (Chip Select) hota hai jo 8255 ko enable karta hai.
• Jab CS = 0 hota hai, tabhi 8255 active hota hai.

4. Control Signals

8085 se 8255 ke liye ye control signals use hote hain:

• RD̅ (Read): 8085 se data read karne ke liye

• WR̅ (Write): 8085 se data write karne ke liye
• RESET: 8255 ko initial state me set karne ke liye
• CS̅ (Chip Select): 8255 ko select karne ke liye

5. Register Selection inside 8255

A0 aur A1 lines ka use hota hai register select karne ke liye:

A1 A0 Selected Register
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register

6. Data Bus Connection

• 8255 ka D0–D7 bus directly 8085 ke D0–D7 se connect hota hai.

• Data transfer dono taraf possible hai – input aur output ke liye.

7. Peripheral Connections

• Port A, Port B, Port C ke pins ko external devices se connect karte hain:

o Port A: Input/Output device
o Port B: Output device (like LEDs, display)
 o Port C: Control signals ya small devices

dfgdfg

Intel
8255 –
Overview

• Ye ek Programmable Peripheral Interface (PPI) hai.

• Matlab iska kaam hai microprocessor (8085/8086) aur peripheral devices (keyboard, display, ADC,
DAC, printer, etc.) ke beech bridge ka kaam karna.
• Ye ek 40-pin IC hoti hai.

Ports

Intel 8255 me total 24 I/O lines hoti hain, jo divide hoti hain 3 ports mein:

1. Port A → 8️ bits (PA7️ – PA0)

2. Port B → 8️ bits (PB7️ – PB0)
3. Port C → 8️ bits (PC7️ – PC0)
o Isko aur tod kar do 4–4 bit ke 2 parts me use kar sakte ho:
▪ Port C Upper → PC7️ – PC4
▪ Port C Lower → PC3️ – PC0

Is flexibility ke wajah se ek hi port C alag alag kaam ke liye use ho sakta hai.

Grouping

8255 ke ports ko do groups me divide kiya gaya hai:

• Group A → Port A + Port C (upper 4️ bits)

• Group B → Port B + Port C (lower 4️ bits)

Har group ko alag mode me program kiya ja sakta hai (Mode 0, Mode 1, Mode 2).
 Programming

Ye ports programmable hote hain, matlab tum decide karte ho ki:

• Port input hoga ya output

• Kaunsa mode of operation hoga (simple I/O, handshake, bidirectional transfer, etc.)

Block Diagram (Right side diagram)

1. Data Bus Buffer (D7–D0)

o Ye ek bidirectional bus hai jo 8255 aur microprocessor ke beech data exchange karti hai.
2. Read/Write Control Logic
o Ye control signals (RD, WR, CS, A0, A1, RESET) handle karta hai.
o Isse decide hota hai ki kaunsa port select hoga aur read ya write operation hoga.
3. Group A Control & Group B Control
o Ye alag-alag control karte hain ports ko unke respective group ke according.
4. Ports
o Port A, Port B, Port C → ye hi external peripherals se directly connected hote hain.

8255 Pin Diagram Explanation

8255 ke total 40 pins hote hain. Ye basically ek I/O device controller hai jo microprocessor aur peripherals
(jaise keyboard, display, printer) ke beech interface banata hai.

Data Bus (D0 – D7)

• Pin: 32 to 39 (8 pins)
• Bidirectional data lines → microprocessor aur peripheral ke beech data transfer ke liye.

Control Signals

• RD (Read) → Active low. Microprocessor se 8255 ko bolta hai ki data read karo.
• WR (Write) → Active low. Microprocessor se 8255 ko bolta hai ki data write karo.
• CS (Chip Select) → Active low. Isse select karte hain ki microprocessor abhi 8255 ko access karega.
• RESET → Reset karta hai 8255 ko aur sabko default mode mein laata hai.

Address Pins (A0, A1)

Ye select karte hain ki microprocessor 8255 ke andar kaunsa port ya control register access karega.

A1 A0 Select
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control Register

Ports
 • Port A (PA0–PA7) → 8-bit
• Port B (PB0–PB7) → 8-bit
• Port C (PC0–PC7) → 8-bit (yeh actually 2 parts mein divide hota hai – PC0–PC3 aur PC4–PC7)

Total: 24 I/O lines

Power Pins

• Vcc → +5V supply

• Vss → Ground

Modes of Operation

8255 mainly 3 modes mein kaam karta hai (Mode 0, 1, 2).

Mode 0 → Simple Input/Output

• Is mode mein har port simple input ya output ki tarah kaam karta hai.
• Data transfer ke liye koi handshaking (extra control signals) nahi hota.
• Bas likho ya padho → direct transfer.

Example:

• Suppose Port A = Output (LEDs connected)

• Port B = Input (Switches connected)
Switch press karoge → microprocessor ke through LED on/off hoga.

Mode 1️ → Input/Output with Handshaking

• Is mode mein ports ke sath kuch handshaking signals (status signals) use hote hain jo
synchronization ke liye hote hain.
• Isme Port C ke kuch pins use hote hain handshaking ke liye.

Input Mode:

• Jab external device data bhejta hai → microprocessor ko "Data Ready" signal milta hai.
• Microprocessor jab data read kar leta hai → "Acknowledge" bhejta hai.

Output Mode:

• Microprocessor data bhejta hai aur ek "Strobe" signal deta hai.

• Peripheral jab data le leta hai tab "Acknowledge" signal deta hai.

Example:

• Printer ko connect karna.

Printer jab ready hota hai toh ek signal deta hai aur jab data receive karta hai toh acknowledge kar deta
hai.
 Mode 2️ → Bidirectional Data Transfer (Only on Port A)

• Is mode mein sirf Port A bidirectional hota hai.

• Matlab same port se data input bhi aur output bhi ho sakta hai.
• Synchronization ke liye Port C ke signals use hote hain.

Example:

• Microprocessor aur ek external communication device ke beech data exchange.

• Kabhi microprocessor data bhejega aur kabhi receive karega – dono same port (Port A) se possible hai.

Simple Summary (for quick recall)

• Mode 0: Simple input/output (no handshaking).

• Mode 1: Input/output with handshaking (synchronization).
• Mode 2: Bidirectional data transfer (only Port A).

1. Control Word of 8255 (Mode Set Word - MSW)

Ye ek 8-bit word hota hai (D7–D0) jo decide karta hai ki ports kis mode mein kaam karenge (Input/Output,
Mode0/1/2).

Breakdown of Bits:

• D7 → 1 = IO Mode, 0 = BSR Mode

• D6 & D5 → Port A ke mode select (00=Mode0, 01=Mode1, 1x=Mode2)
• D4 → Port A direction (1 = Input, 0 = Output)
• D3 → Port C upper (PC7–PC4) direction (1 = Input, 0 = Output)
• D2 → Port B mode (0=Mode0, 1=Mode1)
• D1 → Port B direction (1 = Input, 0 = Output)
• D0 → Port C lower (PC3–PC0) direction (1 = Input, 0 = Output)

✨ Matlab har port ke liye tum decide kar sakte ho ki wo input hoga ya output aur kis mode mein chalega.

2. BSR (Bit Set/Reset) Mode

Is mode mein hum sirf Port C ke individual bits ko control karte hain (set ya reset karna).
Iske liye bhi ek 8-bit control word hota hai:

• D7 = 0 → Matlab ye BSR Mode hai.

• D3–D1 → Bit select (000 = PC0, 001 = PC1 … 111 = PC7)
• D0 → Action (1 = Set, 0 = Reset)
• D6–D4 → Not used (generally 0 rakhe jate hain).

Example:

• Agar tumhe PC3 ko set karna hai → Control word = 0000 0111 (07H)
• Agar tumhe PC5 ko reset karna hai → Control word = 0000 1010 (0AH)
Exam Point of View:

Types of Questions aayenge:

1. Define Control Word format (bits ka meaning likhna).

2. Given a situation, likho control word.
o Example: Port A input Mode1, Port B output Mode0, Port C lower output, Port C upper input.
o Tumhe bas bits set karne hote hain → usse 8-bit binary → usko Hex mein likho.
3. Bit Set/Reset question:
o Example: Reset PC2 → iska control word likho.

Example Question

Q: Program the 8255 in IO mode with the following conditions:

• Port A → Input, Mode 1

• Port B → Output, Mode 0
• Port C Upper → Input
• Port C Lower → Output

Step 1: Control Word Format (D7–D0)

• D7 = 1 (IO mode select)

• D6–D5 = 01 (Port A = Mode 1)
• D4 = 1 (Port A = Input)
• D3 = 1 (PC upper = Input)
• D2 = 0 (Port B = Mode 0)
• D1 = 0 (Port B = Output)
• D0 = 0 (PC lower = Output)

Step 2: Bits likho

Control word = 1 0 1 1 1 0 0 0

Step 3️: Binary → Hex conversion

10111000 (binary) = B8H

✅ Final Answer: Control Word = B8H

How to Write in Exam

“The control word for the given configuration is 10111000 (B8H).”

1) Address / Data demultiplexing (AD0–AD7, ALE, latch)

Problem to solve: 8085 ki lower bus lines AD0–AD7 dono ka kaam karti hain — pehle lower address phir
data. Humko address ko alag karna padta hai taaki decoder/8255 ko sahi address mil sake.

Solution (how it’s wired):

• AD0–AD7 → CPU ke pass pehle lower address byte hoti hai (T1).
• ALE (Address Latch Enable) signal T1 mein HIGH pulse deta hai.
• A standard latch (eg. 74LS373) ka enable ALE se hota hai — jab ALE HIGH, latch samples AD0–
AD7 and outputs stable A0–A7.
• After T1, ALE goes LOW → latch holds the lower-address bits while AD0–AD7 bus becomes data bus
(D0–D7).
• Upper address bits (A8–A15) are on separate lines (not multiplexed) and are available continuously.

Important notes:

• Latch output (A0–A7) + upper address bits used by decoder for chip selection.
• ALE pulse must be wide enough to meet latch setup/hold times.
• Without demultiplexing, decoder would see wrong signals once data appears on AD lines.

2) Chip Select (CS) using a decoder (e.g., 74LS138)

Why decoder? Multiple I/O devices share the I/O address space — a decoder maps higher address lines to a
single active CS for the addressed device.

Typical arrangement (conceptual):

• Use a 3-to-8 decoder (74LS138) or similar.

• Inputs to decoder: some higher address bits (e.g., A4, A5, A6) — choose bits that represent the block of
addresses you want for peripherals.
• Use IO/M (from 8085) as an enable so decoder only works during I/O cycles: IO/M = 1 → I/O
operation, decoder enabled; IO/M = 0 → memory operation, decoder disabled.
• Decoder outputs (IOCS0..IOCS7) are active low outputs; connect one output to CS̅ (chip select,
active low) of the 8255.

Example logic idea:

• Suppose you want to map 8255 to I/O addresses 0x10–0x13. You can setup decoder so that when
A7..A3 equals specific pattern and IO/M=1, the decoder output Yx goes LOW and that is tied to
8255 CS̅.

Key points:
 • Decoder enables: some have G1 (active high) and G2A/G2B (active low) — tie them to IO/M and
another address bit to restrict selection further.
• Ensure CS̅ is LOW only for the exact addresses mapped to 8255, otherwise peripheral may drive bus
unintentionally.

3) Control signals (RD̅ , WR̅ , RESET, IO/M)

• RD̅ (from 8️08️5️) → RD̅ (of 8255): Active low. CPU reads from 8255 when RD̅ is low and CS̅ is low
and correct A0,A1 select a register.
• WR̅ (from 8️08️5️) → WR̅ (of 8255): Active low. CPU writes into selected 8255 register when WR̅ low
+ CS̅ low + A0,A1 selects register.
• RESET (from 8️08️5️) → RESET (of 8️2️5️5️): Initializes 8255 (ports default to outputs or input as per
datasheet; control register cleared). Always tie resets to same reset source for predictable start-up.
• IO/M: used for distinguishing memory vs I/O cycles. Use as decoder enable so decoder outputs only
during IO cycles.

Timing relation summary:

• ALE pulse in T1 → latch lower address.

• Decoder uses latched address + A-lines to assert CS.
• In T2 (or T2–T3), RD̅ or WR̅ is asserted by CPU. 8255 must drive (read) or receive (write) data during
this window.

4) Register selection inside 8255 (A0, A1 mapping)

8085’s latched A0 and A1 are directly connected to 8255’s A0,A1 to choose which internal register is accessed:

A1 A0 Selected Register

0 0 Port A

0 1 Port B

1 0 Port C

1 1 Control Register

So: within the I/O base address of the 8255:

• base + 0 → Port A
• base + 1 → Port B
• base + 2 → Port C
• base + 3 → Control register (write control word or BSR word)

5) Data bus connection (D0–D7)

• D0–D7 (8255) connect directly to D0–D7 (8085) (bidirectional).

• On a read (RD̅ LOW), 8255 drives the data bus with requested port/control value.
• On a write (WR̅ LOW), CPU drives D0–D7 and 8255 latches the incoming data.
 • Must ensure only the selected device drives the bus (CS̅ + RD̅ ensure that). Otherwise bus contention
occurs (bad!).

Hardware note: often use bus transceivers or ensure devices are tri-state outside their drive window.

6) Peripheral connections

• Port A, Port B => connect to external devices (LED arrays, data lines to ADC/DAC, displays).
• Port C => used for individual control lines and handshaking:
o PC7–PC4 (upper nibble) grouped with Port A (Group A).
o PC3–PC0 (lower nibble) grouped with Port B (Group B).
• If in Mode 1/2, certain PC bits become handshaking signals (STB, IBF, OBF, INTR, ACK etc.).
These must be wired to peripheral control pins per mode spec.

7) Read / Write cycle (step-by-step) — exact timing (useful for timing-diagram)

CPU wants to read Port A (base + 0):

1. T1: CPU places address on AD0–AD7 (low byte) and A8–A15 on high bus. ALE = 1 briefly → latch
captures AD0–AD7 into latch → latch outputs stable A0–A7.
2. T2: CPU sets IO/M=1 (I/O), decoder enabled sees latched address + upper bits → decoder asserts
CS̅ for 8255. CPU asserts RD̅ = 0. 8255 senses CS̅=0 & RD̅=0 & A1A0 select Port A → 8255
drives data on D0–D7.
3. T2–T3: CPU samples data from bus.
4. End of cycle: RD̅ returns HIGH, CS̅ deasserted, data bus released.

CPU write to Port B (base + 1): same T1 latch step, then in T2 CPU puts data on D0–D7 and asserts WR̅ =
0 while CS̅=0. 8255 latches data on the rising edge (or per datasheet timing) of WR.

Important: RD/WR assertion timing relative to ALE and latch — ensure address is latched BEFORE RD/WR
is asserted (hence ALE in T1, RD/WR in T2/T3).

8) Example mapping — practice (concrete)

Say you want 8255 to occupy I/O addresses 0x10–0x13. Implementation idea:

• Use 3-to-8 decoder.

• Let decoder inputs be A4,A5,A6 (or appropriate bits) — choose so that when address = 0001 000x x
(hex 10–13), one decoder output is active.
• Also use IO/M as an enable so decoder output only active during I/O cycles.
• Connect that decoder output to 8255 CS̅.
• Then:
o 0x10 → A1A0 = 00 → Port A
o 0x11 → A1A0 = 01 → Port B
o 0x12 → A1A0 = 10 → Port C
o 0x13 → A1A0 = 11 → Control register

Exam answer style: Draw small block: AD0-AD7 → latch (ALE) → A0–A7; A8–A15 directly → decoder +
IO/M → CS; A0,A1 → 8255 select; D0–D7 ↔ data bus.
9) Extra practical tips / wiring checklist (so your lab/internals never fail)

• Connect RESET of 8255 to system reset so it starts in known state.

• Connect Vcc = +5V and Vss = GND properly; decoupling caps near IC.
• Make sure decoder outputs are active-low to match CS̅ (invert if necessary).
• Use ALE → 74LS373 latch (enable on ALE) — not forgetting pull-ups if needed.
• Use buffer/transceiver if long bus lines or multiple devices to avoid contention.
• For inputs, consider pull-ups/pull-downs as required (especially for TTL).
• When using Mode 1/2, wire PC pins exactly as per handshaking signals to peripheral.

10) How to solve typical exam questions (step-by-step)

1. Read question — base I/O address (given?), which ports inputs/outputs, which mode?
2. Find control word (if required): set D7 = 1 for IO mode; set mode bits D6–D5 for Port A; D4 = portA
dir etc → form 8-bit → hex. (We practiced before.)
3. Address mapping / CS logic: Identify which address lines decoder must match → show which
decoder output connects to 8255 CS. Mention IO/M = 1 as enable.
4. Timing diagram question: Draw T1 (ALE high, address latch), T2 (RD/WR asserted, data valid), T3
(data/finish). Label ALE, AD lines (address in T1, data in T2/T3), CS, RD/WR, D0–D7.
5. Bit-set/reset (BSR) question: If asked to set/reset a PC bit, set D7 = 0 and fill bit select and S/R as
shown earlier.

Quick reference table (put in notes for exam)

• ALE high → latch AD0–AD7 → generate A0–A7.

• IO/M = 1 → I/O cycle.
• CS̅ active (LOW) + RD̅ LOW → device must drive data bus.
• CS̅ active + WR̅ LOW → device will latch data from bus.
• A1 A0 = 00/01/10/11 → Port A / B / C / Control Reg.

Part 1: 4×4 Matrix Keypad with 8085 + 8255

Structure

• 4 rows × 4 columns → total 16 keys.

• Rows (R0–R3) and Columns (C0–C3).
• Each key is at intersection of one row and one column.

Connection with 8255:

• Suppose:
o Rows → Port A (output).
 o Columns → Port B (input, with pull-up resistors).

Working (Scanning principle)

1. Processor outputs 0001 on Port A → activates Row0.

o If a key in Row0 is pressed, one of the column lines (Port B) goes LOW.
o Example: key (Row0, Col2) pressed → Port B reads 1110 (bit2 low).
2. If no key pressed → all inputs HIGH (1111).
3. Then processor outputs 0010 → activates Row1, check Port B.
4. Repeat for all 4 rows.
5. So, you can detect exact row+col → key number identified.

Part 2: Three major tasks for Keyboard

1. Sense a key actuation → detect transition from HIGH to LOW on a column when scanning.
2. Debounce the key → mechanical key press is noisy (ON/OFF jitter 10–20 ms).
o Software introduces small delay or checks multiple times to confirm stable press.
3. Decode the key → row + column = unique key code.
o Example: Row2 + Col1 = “5” (depending on keypad layout).

Part 3: Flowchart of keyboard scanning subroutine

Typical steps:

1. Initialize 8255:
o Port A = output (rows), Port B = input (columns).
2. Send pattern 0001 → read Port B.
o If all HIGH → no key.
o If any LOW → key detected → go to debounce + decode.
3. If no key in Row0, shift 0010 → repeat for Row1, Row2, Row3.
4. Once key found, identify which row and which column bit = 0.
5. Use lookup table (mapping row+col → ASCII or hex digit).
6. Return key code to main program.

Part 4: Display interface using ports

Here 7-segment displays (common cathode/anode) are connected to 8255 output.

• Each digit has 7 LEDs: a, b, c, d, e, f, g.

• To display “2”: segments a, b, g, e, d ON.

Binary code for each number → stored in a lookup table in program.

Decimal digit 7-seg Binary code (abcdefg) Hex

0 0x3F 3Fh
1 0x06 06h
2 0x5B 5Bh
3 0x4F 4Fh
4 0x66 66h
Decimal digit 7-seg Binary code (abcdefg) Hex
5 0x6D 6Dh
6 0x7D 7Dh
7 0x07 07h
8 0x7F 7Fh
9 0x6F 6Fh

Ye codes directly 8255 ke output port par bhejte ho → segments light up → digit appear hota hai.

Part 5: DAC interface

DAC (Digital-to-Analog Converter) converts digital binary → analog voltage.

Formula:

Vout=(D2n−1)×VrefV_{out} = \left(\frac{D}{2^n - 1}\right) \times V_{ref}Vout=(2n−1D)×Vref

• D = digital input (binary number)

• n = number of bits (e.g. 8 bits)
• Vref = reference voltage

Example:
8-bit DAC, Vref = 5 V, Digital input = 1111 1111 (255)

Vout=255255×5=5VV_{out} = \frac{255}{255} \times 5 = 5VVout=255255×5=5V

If input = 1000 0000 (128):

Vout=128255×5≈2.51VV_{out} = \frac{128}{255} \times 5 ≈ 2.51 VVout=255128×5≈2.51V

Part 6: ADC interface (Analog-to-Digital)

ADC converts analog voltage → digital binary.

Process:

• CPU sends START signal.

• ADC converts and sets EOC (End of Conversion) flag.
• CPU reads binary output → processed as digital number.

Part 7: Typical Exam Question (Keyboard + Display)

“Write a program to read a key from keypad and display its decimal value on 7-segment.”

Steps:

1. Scan keypad → get row+col → decode to digit.

2. Lookup 7-segment code table.
3. Send code to 8255 port connected to display.
4. Show digit.

Summary for you:

• Keypad: row/col scanning, debounce, decode.

• Display: lookup table of 7-segment hex codes.
• DAC: digital input → analog voltage (formula).
• ADC: analog input → digital code (read by processor).