Microprocessors and

Microcontrollers (ECL 1302)

 Introduction to Microprocessors & Microcontrollers
brain without body brain with body
A Microprocessor is like a central processing unit (CPU) which is on a single integrated circuit (IC) chip.
-> It mainly contains ALU, Control Unit and Registers.
-> Read instructions -> Process it -> Give result
-> It don't have any built in memory or I/O device.
-> Ex- Intel 8085,

Raspberry Pi
8085 8051
Microcontroller is a small computer on a single chip having CPU, Memory(RAM + ROM), I/O ports, and timers everything embeded in a chip.
-> perform specific task (pre-programmed function)
-> Used in embeded systems
-> Ex- 8051, ARM Cortex M series
 Aspect Microprocessor Microcontroller

Main Function General-purpose computing Specific control tasks (embedded

systems)

Components Only CPU; external RAM, ROM, CPU + RAM + ROM + I/O all in
I/O needed one chip

Cost More expensive (needs extra Cost-effective (integrated system)

components)

Power High Low

Consumption

Speed Higher performance Optimized for control, not speed

Applications PCs, laptops, complex systems Washing machines, microwaves,

IoT, robotics
8085 microprocessor

+5 V

0v
Arithmetic and Logic Unit (ALU)

➢ Performs arithmetic operations (ADD, SUB, etc.) and logical

operations (AND, OR, XOR, etc.).

➢ Works with 8-bit data.

➢ Results affect flag bits in the flag register.

Flag structure

Sign Flag (S): Set when the result of an operation is negative. This means the most significant bit (MSB) of the result is 1.

Zero Flag (Z): Set when the result of an operation is zero. If all bits of the result are 0, this flag is activated.

Auxiliary Carry Flag (AC): Set if there’s a carry from bit 3 to bit 4 during addition or subtraction—especially useful in
Binary-Coded Decimal (BCD) operations.

Parity Flag (P): Set if the number of 1s in the result is even. It helps in error detection.

Carry Flag (CY): Set if there is a carry out of the most significant bit (bit 7) during addition, or a borrow during subtraction.
 Register Size Description

Accumulator 8-bit Main register used in arithmetic and

(A) logical operations.

General B, C, D, E, H, L Used individually or as register pairs

Purpose (8-bit each) (BC, DE, HL).
Registers

Program 16-bit Holds the memory address of the next

Counter (PC) instruction.

Stack Pointer 16-bit Points to the top of the stack (used in

(SP) subroutine calls, interrupts).

Instruction 8-bit Holds the opcode of the current

Register (IR) instruction.

Temporary 8-bit Used internally by the ALU.

Register

Flag Register 8-bit Holds status flags that reflect ALU

results: S, Z, AC, P, CY.
Control Unit
➔ Decodes instructions and generates control Timing and Control Unit
signals. ➔ Generates clock signals.
➔ Controls the timing and operation of other parts. ➔ Synchronizes all internal operations.
➔ Coordinates memory and I/O operations with the system
Key signals: bus.
➔ RD̅ (Read): Enables memory or I/O read.
➔ WR̅ (Write): Enables memory or I/O write. Clock Generator
➔ IO/M̅: Distinguishes between memory and I/O ➔ Internal clock generator using an external crystal
operations. (usually 6 MHz).
➔ ALE (Address Latch Enable): Used to latch the ➔ Provides timing for instruction execution.
lower byte of the address.
➔ S1 & S0: Status signals indicating current
operation.
System Buses
Bus Width Function

Address Bus 16-bit Carries address to memory/I/O. (A0–A15)

Data Bus 8-bit Carries data (D0–D7). Bidirectional.

Control Bus Several Carries control signals (RD̅, WR̅, etc.)

lines

Serial I/O Control

● Two lines: SID (Serial Input Data) and SOD (Serial Output Data) Used to transfer single bit data form sensor to processor

● For bit-by-bit data communication Used to transfer single bit data form processor to output
Interrupt Control in 8085
➔ An interrupt is a mechanism by which a microprocessor's normal execution flow is temporarily halted, and a special routine
(Interrupt Service Routine or ISR) is executed. After the ISR is executed, the processor resumes the previous task.

➔ This allows the CPU to respond to asynchronous events like I/O requests, timers, or hardware signals.

Hardware Interrupts

● These are external signals received through dedicated pins of the 8085
microprocessor.

Maskable Interrupts

● These can be enabled or disabled using software instructions (EI, DI, SIM).

● The processor can ignore (mask) these interrupts if needed.

SIM – Set Interrupt Mask

RIM – Read Interrupt Mask ● Examples in 8085:

RST7.5
EI – Enable Interrupts RST6.5
RST5.5
DI – Disable Interrupts
INTR
 Non-Maskable Interrupt

● These cannot be disabled or ignored by the program.

● Used for critical events like power failure or emergency halt.

● Example in 8085: TRAP

Software Interrupts

● These are instructions written in the program that explicitly invoke an

interrupt.

SIM – Set Interrupt Mask ● Used to call routines or services.

RIM – Read Interrupt Mask ● In 8085, they are called Restart Instructions.

EI – Enable Interrupts
🔹 Examples:
DI – Disable Interrupts
● RST 0 to RST 7 (i.e., RST 0, RST 1, ..., RST 7)

● These are like software-generated vector calls to specific memory addresses.

An Interrupt Service Routine (also called an Interrupt Handler) is a special block of code that is executed when the CPU receives an
interrupt request.

It contains the instructions to handle whatever event triggered the interrupt — for example, reading data from an I/O device, handling a
timer overflow, etc.
SIM — Set Interrupt Mask
Full form: Set Interrupt Mask
Purpose: Enables, disables (masks), or controls
certain interrupts (RST7.5, RST6.5, RST5.5) and
can also control the serial output data (SOD)
line.
Agar bit = 1 → interrupt band (masked/disabled)

Agar bit = 0 → interrupt chalu (enabled)

Accumulator (A) is loaded with a control

byte.

Each bit in A has a meaning.

Executing SIM sets or resets interrupt masks

and SOD accordingly.

MVI A, 00001110B ; MSE(D3)=1, M7.5(D2)=1, M6.5(D1)=1, M5.5(D0)=0

RST7.5 → ❌ disabled
D3 (MSE) = 1 → Matlab D2, D1, D0 bits valid hain.
SIM D2 (M7.5) = 1 → RST7.5 disable.
RST6.5 → ❌ disabled
D1 (M6.5) = 1 → RST6.5 disable.

D0 (M5.5) = 0 → RST5.5 enable.

RST5.5 → ✅ enabled
This keeps RST 5.5 active but blocks RST7.5 and RST6.5.
 Feature SIM RIM

Full form Set Interrupt Mask Read Interrupt Mask

Function Set/mask interrupts, serial out Read mask, status, serial in

Data flow Accumulator → Control Logic Control Logic → Accumulator

Used for Enabling/disabling interrupts, Checking interrupt enable/mask

sending SOD status, reading SID

Requires Yes (to set masks) No

MSE bit?

Opcode size 1 byte 1 byte

Instructions LMBDA

1. Data Transfer Instructions: These instructions move data between registers, memory, and I/O devices.

Examples:

● MOV: Copy data from one register to another

● LDA: Load data from memory into the accumulator
● STA: Store data from accumulator to memory
● IN / OUT: Input/Output data from/to a port

2. Arithmetic Instructions: Perform arithmetic operations like addition, subtraction, etc.

Examples:

● ADD: Add contents to the accumulator

● SUB: Subtract contents from the accumulator
● INR: Increment a register or memory location
● DCR: Decrement a register or memory location
Instructions

3. Logical Instructions: Perform bitwise operations and compare operations.

Examples:

● ANA: Logical AND with accumulator

● ORA: Logical OR with accumulator
● XRA: Logical XOR with accumulator
● CMA: Complement accumulator
● CMP: Compare register/memory with accumulator

4. Branching Instructions: Alter the normal sequence of execution (used for loops, conditionals).

Examples:

● JMP: Unconditional jump to a memory location

● JC, JNC: Jump if carry/no carry
● JZ, JNZ: Jump if zero/non-zero
● CALL, RET: Call subroutine / return from subroutine
Instructions

5. Machine Control Instructions: Control the operation of the processor.

Examples:

● NOP: No operation
● HLT: Halt the processor
● DI: Disable interrupts
● EI: Enable interrupts
Addressing Modes
DR III

1. Immediate Addressing Mode

● Definition: Data is specified directly in the instruction.

● Example:
MVI A, 32H → Load value 32H directly into accumulator A.

2. Register Addressing Mode

● Definition: Data is in a register.

● Example:
MOV B, C → Copy contents of register C into register B.

3. Direct Addressing Mode

● Definition: The memory address is given explicitly.

● Example:
LDA 2050H → Load accumulator with the value at memory address 2050H.
4. Indirect Addressing Mode

● Definition: Address of the data is stored in a register pair.

● Example:
MOV A, M → Move data from the memory location pointed by HL pair to accumulator.

5. Implicit (Implied) Addressing Mode

● Definition: Operand is implied by the instruction.

● Example:
CMA → Complement the contents of accumulator (no operand needed).
 Addressing Description Example Instruction Word
Mode (8085) Size

Immediate Operand is given directly in the MVI A, 32H 2 bytes

instruction

Register Operand is a CPU register MOV B, C 1 byte

Direct Address of operand is given in LDA 2050H 3 bytes

the instruction

Indirect Address is in a register pair (e.g., MOV A, M 1 byte

HL)

Implicit Operand is implied by the CMA 1 byte

(Implied)
instruction
 Timing diagram
❖ shows the relationship between control signals, address/data lines, and clock pulses during the
execution of instructions or machine cycles.
Key Terms in 8085 Timing Diagram

T-state (T1, T2, T3…):

The smallest unit of time in the 8085, one clock period.
Machine Cycle:
Time required to complete one basic operation such as:
Opcode Fetch (OF)
Memory Read (MR)
Memory Write (MW)
I/O Read (IOR)
I/O Write (IOW)
Interrupt Acknowledge (INTA)

Control Signals:
● ALE (Address Latch Enable): High during T1 to latch the lower address.
● RD̅: Low when reading from memory/I/O.
● WR̅: Low when writing to memory/I/O.
● IO/M̅:
○ 0 → Memory operation
○ 1 → I/O operation
● S1, S0: Status signals identifying the machine cycle.
The 8085 executes any instruction in two phases:

1. Fetch Cycle – Get the instruction from memory.

2. Execute Cycle – Perform the instruction, which may involve memory or I/O operations.

Each phase is made of machine cycles, and each machine cycle is made of T-states (T1, T2, T3, …).

Fetch Cycle
Purpose: Get the instruction's opcode from memory.

Steps:
Control Signals:
T1: Put the memory address (PC contents) on address bus. IO/M̅ = 0 (Memory)
RD̅ = Active (Low)
ALE = 1 to latch lower byte (AD0–AD7).
WR̅ = High
T2–T3: Read the opcode from memory (RD̅ = 0, IO/M̅ = 0). ALE = High in T1 only
T4+ (if needed): Internal decoding.
STA 2500H

A = 20 H
Address Data Address Data

1000H 32H 2500H 20H

1001H 00H 2501H

1002H 25H 2502H

Execute Cycle
Purpose: Carry out the fetched instruction.

Execution may require:

Memory Read Cycle

Memory Write Cycle
I/O Read Cycle
I/O Write Cycle
No external operation (for some instructions like NOP or register-to-register moves)

Memory Read Cycle

Purpose: Read data from a memory location (for operands or instructions).

Steps: Control Signals:

IO/M̅ = 0
T1: Put address on bus, ALE = 1. RD̅ = Low during read
WR̅ = High
T2: IO/M̅ = 0, RD̅ = 0 → Data from memory to CPU.
T3: RD̅ returns High.
 A = 20 H
Address Data

1000H 32H

1001H 00H

1002H 25H

Address Data

2500H 20H

2501H

2502H
Memory Write Cycle
Purpose: Write data to a memory location. Control Signals:
IO/M̅ = 0
Steps: WR̅ = Low during write
RD̅ = High
T1: Put address on bus, ALE = 1.
T2: IO/M̅ = 0, WR̅ = 0 → Data from CPU to memory.
T3: WR̅ returns High.
STA 2500H Address Data Address Data

1000H 32H 2500H 20H

A = 20 H
1001H 00H 2501H

1002H 25H 2502H

2500H

25H

A= 20H at 2500H
I/O Read Cycle
Purpose: Read data from an input device or I/O port.

Steps: Control Signals:

IO/M̅ = 1
T1: Put I/O port address on address bus (lower byte on AD0–AD7, upper byte ignored). ALE = 1. RD̅ = Low during read
WR̅ = High
T2: IO/M̅ = 1, RD̅ = 0 → Data from port to data bus.
ALE = High in T1
T3: RD̅ returns High, CPU stores the data.

IN 08H

I/O Write Cycle

Purpose: Write data to an output device or I/O port.
Control Signals:
IO/M̅ = 1
Steps: WR̅ = Low during write
RD̅ = High
T1: Put I/O port address on address bus, ALE = 1. ALE = High in T1
T2: IO/M̅ = 1, WR̅ = 0 → Data placed on data bus.
T3: WR̅ returns High.