8086 Microprocessor
• First 16- bit processor released by INTEL in the year 1978
• It can support up to 64K I/O ports
• 20-bit address to access memory => can address up to 220 = 1
megabytes of memory space.
• Operates in two modes: minimum mode and maximum mode,
decided by the signal at MN and 𝐌𝐗 pins.
• Word size is 16 bits and double word size is 4 bytes.
• It has multiplexed address and data bus AD0- AD15 and A16 – A19.
• It requires single phase clock with 33% duty cycle to provide internal
timing.
Common Signal
AD0-AD15 (Bidirectional)
Address/Data bus
➢ Low order address bus; these are
multiplexed with data.
➢ When AD lines are used to transmit
memory address the symbol A is used
instead of AD, for example A0 -A15.
➢ When data are transmitted over AD lines
the symbol D is used in place of AD, for
example D0 -D7 , D8 -D15 or D0 -D15.
A16/S3 , A17/S4 , A18/S5 , A19/S6
➢ High order address bus. These are
multiplexed with status signals
Common Signal BHE (Active Low)/S7 (Output)
Bus High Enable/Status
➢ It is used to enable data onto the most
significant half of data bus, D8 -D15.
➢ 8-bit device connected to upper half of
the data bus use BHE (Active Low) signal.
➢ It is multiplexed with status signal S7 .
MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
RD (Read) (Active Low)
The signal is used for read operation. It is an
output signal. It is active when low.
TEST READY
𝐓𝐄𝐒𝐓 input is tested by the ‘WAIT’ This is the acknowledgement from the slow
instruction. 8086 will enter a wait state after device or memory that they have completed
execution of the WAIT instruction and will the data transfer. The signal made available
resume execution only when the 𝐓𝐄𝐒𝐓 is by the devices is synchronized by the 8284A
made low by an active hardware. This is clock generator to provide ready input to
used to synchronize an external activity to the 8086. The signal is active high.
the processor internal operation.
RESET (Input) INTR Interrupt Request
Causes the processor to immediately This is a triggered input. This is sampled
terminate its present activity. The signal during the last clock cycles of each
must be active HIGH for at least four clock instruction to determine the availability of
cycles. the request. If any interrupt request is
CLK pending, the processor enters the interrupt
acknowledge cycle. This signal is active high
The clock input provides the basic timing and internally synchronized.
for processor operation and bus control
activity. Its an asymmetric square wave with
33% duty cycle
Min/Max Pins The 8086 microprocessor can work in two
modes of operations :
➢ Minimum mode and Maximum mode. In
the minimum mode of operation the
microprocessor do not associate with
any co-processors and can not be used
for multiprocessor systems.
➢ In the maximum mode the 8086 can
work in multi-processor or co-processor
configuration.
➢ Minimum or maximum mode operations
are decided by the pin MN/ MX(Active
low).
➢ When this pin is high 8086 operates in
minimum mode otherwise it operates in
Maximum mode.
Minimum mode signals
Minimum mode signals
Maximum mode signals
Maximum mode signals