Computer Organization & Architecture Guide
Computer Organization & Architecture Guide
S.
No. Computer Architecture Computer Organization
Computer Architecture deals with the Computer Organization deals with a structural
2. functional behavior of computer systems. relationship.
In the above figure, it’s clear that it deals In the above figure, it’s also clear that it deals with
3. with high-level design issues. low-level design issues.
S.
No. Computer Architecture Computer Organization
Architecture coordinates the hardware and Computer Organization handles the segments of
11. software of the system. the network in a system.
12. The software developer is aware of it. It escapes the software programmer’s detection.
Examples- Intel and AMD created the x86 Organizational qualities include hardware
processor. Sun Microsystems and others elements that are invisible to the programmer,
created the SPARC processor. Apple, IBM, such as interfacing of computer and peripherals,
13. and Motorola created the PowerPC. memory technologies, and control signals.
A computer organization describes the functions and design of the various units
of a digital system.
o A general-purpose computer system is the best-known example of a digital system.
Input unit
• Input units are used by the computer to read the data. The most commonly used
input devices are keyboards, mouse, joysticks, trackballs, microphones, etc.
• However, the most well-known input device is a keyboard. Whenever a key is pressed,
The corresponding letter or digit is automatically translated into its corresponding binary
code and transmitted over a cable to either the memory or the processor.
Memory unit
o The Memory unit can be referred to as the storage area in which programs are kept
which are running, and that contains data needed by the running programs.
o The Memory unit can be categorized in two ways namely, primary memory
and secondary memory.
o It enables a processor to access running execution applications and services that
are temporarily stored in a specific memory location.
o Primary storage is the fastest memory that operates at electronic speeds. Primary
memory contains a large number of semiconductor storage cells, capable of storing a bit
of information. The word length of a computer is between 16-64 bits.
o It is also known as the volatile form of memory, means when the computer is shut
down, anything contained in RAM is lost.
o Cache memory is also a kind of memory which is used to fetch the data very soon.
They are highly coupled with the processor.
o The most common examples of primary memory are RAM and ROM.
o Secondary memory is used when a large amount of data and programs have to be stored
for a long-term basis.
o It is also known as the Non-volatile memory form of memory, means the data is
stored permanently irrespective of shut down.
o The most common examples of secondary memory are magnetic disks, magnetic
tapes, and optical disks.
Control unit
Output Unit
o The primary function of the output unit is to send the processed results to the user.
Output devices display information in a way that the user can understand.
o Output devices are pieces of equipment that are used to generate information or any
other response processed by the computer. These devices display information that has
been
held or generated within a computer.
o The most common example of an output device is a monitor.
o The special function registers include program counters (PC), instruction registers (IR),
memory address registers (MAR) and memory and memory data registers (MDR).
o The Program counter is one of the most critical registers in CPU.
o The Program counter monitors the execution of instructions. It keeps track on
which instruction is being executed and what the next instruction will be.
o The instruction register IR is used to hold the instruction that is currently being
executed. o The contents of IR are available to the control unit, which generate the timing
signals that control, the various processing elements involved in executing the instruction.
o The two registers MAR and MDR are used to handle the data transfer between the main
memory and the processor.
o The MAR holds the address of the main memory to or from which data is to
be transferred.
o The MDR contains the data to be written into or read from the addressed word of
the main memory.
o Whenever the processor is asked to communicate with devices, we say that the
processor is servicing the devices. The processor can service these devices in one of the
two ways.
o One way is to use the polling routine, and the other way is to use an interrupt.
o Polling enables the processor software to check each of the input and output
devices frequently. During this check, the processor tests to see if any devices need
Computer Instructions
Computer instructions are a set of machine language instructions that a particular processor
understands and executes. A computer performs tasks on the basis of the instruction
provided. An instruction comprises of groups called fields. These fields include:
o The Operation code (Opcode) field which specifies the operation to be performed.
o The Address field which contains the location of the operand, i.e., register or
memory location.
o The Mode field which specifies how the operand will be located.
In Memory-reference instruction, 12 bits of memory is used to specify an address and one bit
to specify the addressing mode 'I'.
Register - reference instruction
The Register-reference instructions are represented by the Opcode 111 with a 0 in the
leftmost bit (bit 15) of the instruction.
The Operation code (Opcode) of an instruction refers to a group of bits that define arithmetic
and logic operations such as add, subtract, multiply, shift, and compliment.
Just like the Register-reference instruction, an Input-Output instruction does not need a
reference to memory and is recognized by the operation code 111 with a 1 in the leftmost bit
of the instruction. The remaining 12 bits are used to specify the type of the input-output
operation or test performed.
Note
o The three operation code bits in positions 12 through 14 should be equal to 111. Otherwise,
the instruction is a memory-reference type, and the bit in position 15 is taken as the addressing
mode I.
o When the three operation code bits are equal to 111, control unit inspects the
bit in position 15. If the bit is 0, the instruction is a register-reference type.
Otherwise, the instruction is an input-output type having bit 1 at position 15.
A computer can process data, pictures, sound and graphics. They can solve highly
complicated problems quickly and accurately. A computer as shown in below figure
performs basically five major computer operations or functions irrespective of their size
and make. These are
1) it accepts data or instructions by way of
input,
2) it stores
data,
3) it can process data as required by the
user,
4) it gives results in the form of output,
and
5) it controls all operations inside a
computer.
1. Input: This is the process of entering data and programs in to the computer system. You
should know that computer is an electronic machine like any other machine which takes
as inputs raw
data and performs some processing giving out processed data. Therefore, the input unit
takes data from us to the computer in an organized manner for processing.
2. Memory: The process of saving data and instructions permanently is known as storage.
Data has to be fed into the system before the actual processing starts. It is because the
processing speed of Central Processing Unit (CPU) is so fast that the data has to be provided
to CPU with the same speed. Therefore the data is first stored in the storage unit for faster
access and processing. This storage unit or the primary storage of the computer system is
designed to do the above functionality. It provides space for storing data and instructions.
• All data and instructions are stored here before and after processing.
3. Arithmetic Logic Unit: The task of performing operations like arithmetic and logical
operations is called processing. The Central Processing Unit (CPU) takes data and
instructions from the storage unit and makes all sorts of calculations based on the
instructions given and the type of data provided. It is then sent back to the storage unit.
4. Output: This is the process of producing results from the data for getting useful information.
Similarly, the output produced by the computer after processing must also be kept
somewhere inside the computer before being given to you in human readable form. Again,
the output is also stored inside the computer for further processing.
5. Control Unit: The manner how instructions are executed and the above operations
are performed. Controlling of all operations like input, processing and output are
performed by control unit. It takes care of step-by-step processing of all operations
inside the computer.
Functional Units
In order to carry out the operations mentioned in the previous section the computer allocates
the task between its various functional units. The computer system is divided into three
separate units for its operation. They are
Arithmetic Logical Unit (ALU)
Logical Unit: After you enter data through the input device it is stored in the primary storage
unit. The actual processing of the data and instruction are performed by Arithmetic Logical
Unit. The major operations performed by the ALU are addition, subtraction, multiplication,
division, logic and
comparison. Data is transferred to ALU from storage unit when required. After processing the
output is returned back to storage unit for further processing or getting stored.
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The next component of computer is the Control Unit, which acts like the supervisor seeing that
things are done in proper fashion. Control Unit is responsible for coordinating various
operations using time signal. The control unit determines the sequence in which computer
programs and instructions are executed. Things like processing of programs stored in the main
memory, interpretation of the instructions and issuing of signals for other units of the
computer to execute them. It also acts as a switch board operator when several users access
the computer simultaneously. Thereby it coordinates the activities of computer’s peripheral
equipment as they perform the input and output.
The ALU and the CU of a computer system are jointly known as the central processing unit. You
may call CPU as the brain of any computer system. It is just like brain that takes all major
decisions, makes all sorts of calculations and directs different parts of the computer functions
by activating and controlling the operations.
Von-Neumann Computer
The modern computers are based on a stored-program concept introduced by John Von
Neumann. In this stored-program concept, programs and data are stored in a separate storage
unit called memories and are treated the same. This novel idea meant that a computer built
with this architecture would be much easier to reprogram.
Control Unit –
The arithmetic logic unit is that part of the CPU that handles all the calculations the CPU may need,
e.g., Addition, Subtraction, Comparisons. It performs Logical Operations, Bit Shifting Operations,
and Arithmetic Operation.
Arithmetic Logic Unit (ALU) is the main part the Central Processing Unit (CPU) in processing
the instructions. The other parts of the CPU are the Control Unit (CU) and register unit.
ALU simply executes the instructions
in the order as dictated by the CU. The ALU performs the instruction execution on the
operand data stored in registers. A CPU with many registers reduces the number of
references to the main memory, and thus simplifying the programming task and shortening
the execution time. An operation performed on the data stored in registers is called micro-
operation. The result of the micro-operation may replace the previous binary information
of a register or may be transferred to another register. Examples of micro-operations are
add, subtract, shift, load and clear, etc. The internal hardware structure of a computer is
characterized by the following attributes:
1. The types of micro-operations performed on the binary information stored in registers.
2. The control signals that initiate the sequence of micro-operations.
3. The set of registers it contains and their functions.
The frequently used micro-operations in digital computers are classified into four categories:
1. Register Transfer Micro-operations: Transfer of binary information from one register to another.
2. Arithmetic Micro-operations: Arithmetic operations performed on the data stored in registers.
3. Logical Micro-operations: Bit manipulation operations on non-numeric data stored in registers.
4. Shift Micro-operations: Shift operations on data stored in registers.
Computers contain some registers within CPU for faster execution. The number of
registers differs from processor to processor. A register is nothing but a collection
of flip flops (see Appendix, for details) each capable of storing one bit of
information. Registers are available in the following forms:
Accumulator (AC) The accumulator is a register which holds one of the operands before
the execution of an instruction, and receives the result of most of the arithmetic and logical
microoperations. Thus, an accumulator is the most frequently used register. Some CPUs
have a single accumulator and some have several accumulators.
Block diagram of a
register
Special-purpose Registers A CPU contains a number of special purpose registers for various purposes.
Commonly used special-purpose registers and their functions are
summarized below: Register Function
PC (Program Counter) Holds the address of the next instruction to be executed.
IR (Instruction register) Holds the instruction code (operation code) currently being executed.
SP (Stack Pointer) Holds the address of the top element of the memory stack.
BR (Base Register) Holds the starting address of the memory stack.
MAR (Memory Address Register) Holds the address of the data item to be retrieved
from the main memory.
MBR or DR (Memory Buffer Holds the data item retrieved from the main memory.
SR or PSW (Status Register Holds the condition code flags and other information that describe the or
Program Status Word) status of the currently executing program.
Many registers are provided in the CPU of a computer for fast execution. Therefore
several paths must be provided to transfer information from one register to
another. If a separate communication line is used between each register pair in the
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system, the number of lines will be excessive and thus cost of communication will
be huge. Thus it is economical to have a common bus system for transferring
information between registers in a multiple-register configuration. A bus system
consists of a group of common communication lines, where each line is used to
transfer one bit of a register at a time. Thus, a shared communication path
consisting of one or more connection lines is known as a bus and the transfer of
data through this bus is known as bus transfer. Sometimes, it is said that n-bit bus
or n-line bus, the meaning of which is that the bus consists of n parallel lines to
transfer n-bit of data all at a time. The n is called width of the bus. The width of the
bus has an impact on a computer’s performance. The wider the bus, the greater the
number of bits transferred at a time.
We will present two ways to construct common bus system. One way is using
multiplexers (simply known as MUXs, see appendix for MUX) and another way is
using tri-state buffers
The below figure shows that an n-line common busbsystem using multiplexers for register
transfer, where four registers are used each of n-bit. This common bus is used to transfer
a register’s content to other register or memory at a single time. A multiplexer selects
one source register whose all n-bit information is then placed on the bus. Two
multiplexers are shown in the figure one for the low-order significant bit and another for
the high order significant bit. The bus consists of n 4 ¥ 1 multiplexers each having four
data inputs, 0 through 3 and two common selection lines for all multiplexers.
Each MUX has four input lines each is connected to all four registers’ bits marked. The two
selection lines S0 and S1 are connected to the selection inputs of all n MUXs. The selection
lines choose all n bits of one register and transfer them into the n-line common bus. For
example, when S1 S0 = 00, the 0th data inputs of all n
MUXs are selected and placed to the outputs that
form the bus. The function table for above figure
will be
Another way to construct a common bus system is using tri-sate buffers. A tri-state gate is
a digital circuit that exhibits three states out of which two states are normal signals
equivalent to logic 1 and logic 0 similar to a conventional gate. The third state is a high-
impedance state. The high-impedance state behaves like an open circuit, which means that
no output is produced though there is an input signal and does not have logic significance.
The gate is controlled by one separate control input C. If C is high the gate behaves like a
normal logic gate having output 1 or 0. When C is low the gate does not product any output
irrespective of the input values. The graphic symbol of a tri-state buffer gate is:-
The outputs of four buffers are connected together to form a single line of the bus. The
control inputs to the buffers, which are generated by a common decoder, determine which
of the four normal inputs will communicate with the common line of the bus. Note that
only one buffer may be in the active state at any given time. Because the selection lines S0,
S1 of the decoder activate one of its output lines at a time and the output lines of the
decoder act as the control lines to the buffers. For example, if select combination
S1S0 is equal to 00, then 0th output of the decoder will be activated, which then
activates the top-most tri-state buffer and thus the bus line content will be currently
A0, 0th bit of A resistor.
Table of Contents
Memory organization, Memory interleaving, concept of hierarchical
memory organization, cache memory, cache size vs. block size,
mapping functions, replacement algorithms, write policies.
Multiple-choice questions (MCQs)
Short Question
Long Question
Memory organization:
Memories are made up of registers. Each register in the memory is one storage location. Storage location
is also called as memory location. Memory locations are identified using Address. The total number of bit
a memory can store is its capacity.
A storage element is called a Cell. Each register is made up of storage element in which one bit of
data is stored. The data in a memory are stored and retrieved by the process called writing and
reading respectively.
A word is a group of bits where a memory unit stores binary information. A word with group of 8
bits is called a byte.
A memory unit consists of data lines, address selection lines, and control lines that specify the
direction of transfer.
Memory Hierarchy Design and its Characteristics
In the Computer System Design, Memory Hierarchy is an enhancement to organize the memory
such that it can minimize the access time. The Memory Hierarchy was developed based on a
program behavior known as locality of references. The figure below clearly demonstrates the
different levels of memory hierarchy:
Levels of memory
Level 1 or Register: It is a type of memory in which data is stored and accepted that are immediately
stored in CPU. Most commonly used register is accumulator, Program counter, address register etc.
Level 2 or Cache memory: It is the fastest memory which has faster access time where data is
temporarily stored for faster access.
Level 3 or Main Memory: It is memory on which computer works currently. It is small in size and
once power is off data no longer stays in this memory.
Level 4 or Secondary Memory: It is external memory which is not as fast as main memory but data
stays permanently in this memory.
Cache Performance
When the processor needs to read or write a location in main memory, it first checks for a
corresponding entry in the cache.
If the processor finds that the memory location is in the cache, a cache hit has occurred and data
is read from cache
If the processor does not find the memory location in the cache, a cache miss has occurred. For a
cache miss, the cache allocates a new entry and copies in data from main memory, then the request
is fulfilled from the contents of the cache.
For purposes of cache access, each main memory address can be viewed as consisting of three fields. The
least significant w bits identify a unique word or byte within a block of main memory. In most
contemporary machines, the address is at the byte level. The remaining s bits specify one of the 2s blocks
of main memory. The cache logic interprets these s bits as a tag of s-r bits (the most significant portion)
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and a line field of r bits. This latter field identifies one of the m=2r lines of the cache. Line offset is index
bits in the direct mapping.
2. Associative Mapping
In this type of mapping, associative memory is used to store the content and addresses of the memory
word. Any block can go into any line of the cache. This means that the word id bits are used to identify
which word in the block is needed, but the tag becomes all of the remaining bits. This enables the
placement of any word at any place in the cache memory. It is considered to be the fastest and most
flexible mapping form. In associative mapping, the index bits are zero.
3. Set-Associative Mapping
This form of mapping is an enhanced form of direct mapping where the drawbacks of direct mapping are
removed. Set associative addresses the problem of possible thrashing in the direct mapping method. It
does this by saying that instead of having exactly one line that a block can map to in the cache, we will
group a few lines together creating a set. Then a block in memory can map to any one of the lines of a
specific set. Set-associative mapping allows each word that is present in the cache can have two or more
words in the main memory for the same index address. Set associative cache mapping combines the best
of direct and associative cache mapping techniques. In set associative mapping the index bits are given by
the set offset bits. In this case, the cache consists of a number of sets, each of which consists of a number
of lines.
Set-Associative Mapping
Relationships in the Set-Associative Mapping can be defined as:
m=v*k
i= j mod v
where
i = cache set number
j = main memory block number
v = number of sets
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m = number of lines in the cache number of sets
k = number of lines in each set
For more, you can refer to the Difference between Types of Cache Mapping.
Application of Cache Memory
Here are some of the applications of Cache Memory.
Primary Cache: A primary cache is always located on the processor chip. This cache is small and its access
time is comparable to that of processor registers.
Secondary Cache: Secondary cache is placed between the primary cache and the rest of the memory. It is
referred to as the level 2 (L2) cache. Often, the Level 2 cache is also housed on the processor chip.
Spatial Locality of Reference: Spatial Locality of Reference says that there is a chance that the element
will be present in close proximity to the reference point and next time if again searched then more close
proximity to the point of reference.
Temporal Locality of Reference: Temporal Locality of Reference uses the Least recently used algorithm
will be used. Whenever there is page fault occurs within a word will not only load the word in the main
memory but the complete page fault will be loaded because the spatial locality of reference rule says that
if you are referring to any word next word will be referred to in its register that’s why we load complete
page table so the complete block will be loaded.
Advantages of Cache Memory
Cache Memory is faster in comparison to main memory and secondary memory.
Programs stored by Cache Memory can be executed in less time.
The data access time of Cache Memory is less than that of the main memory.
Cache Memory stored data and instructions that are regularly used by the CPU, therefore it increases the
performance of the CPU.
Disadvantages of Cache Memory
1. First In First Out (FIFO): This is the simplest page replacement algorithm. In this algorithm, the
operating system keeps track of all pages in the memory in a queue, the oldest page is in the front of
the queue. When a page needs to be replaced page in the front of the queue is selected for removal.
Example 1: Consider page reference string 1, 3, 0, 3, 5, 6, 3 with 3 page [Link] the number of page
faults.
Initially, all slots are empty, so when 1, 3, 0 came they are allocated to the empty slots —> 3 Page
Faults.
when 3 comes, it is already in memory so —> 0 Page Faults. Then 5 comes, it is not available in memory
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so it replaces the oldest page slot i.e 1. —>1 Page Fault. 6 comes, it is also not available in memory so
it replaces the oldest page slot i.e 3 —>1 Page Fault. Finally, when 3 come it is not available so it replaces
0 1 page fault.
Belady’s anomaly proves that it is possible to have more page faults when increasing the number of
page frames while using the First in First Out (FIFO) page replacement algorithm. For example, if we
consider reference strings 3, 2, 1, 0, 3, 2, 4, 3, 2, 1, 0, 4, and 3 slots, we get 9 total page faults, but if we
increase slots to 4, we get 10-page faults.
2. Optimal Page replacement: In this algorithm, pages are replaced which would not be used for the
longest duration of time in the future.
Example-2: Consider the page references 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 3 with 4 page frame. Find
number of page fault.
Initially, all slots are empty, so when 7 0 1 2 are allocated to the empty slots —> 4 Page faults
0 is already there so —> 0 Page fault. when 3 came it will take the place of 7 because it is not used for
the longest duration of time in the future.—>1 Page fault. 0 is already there so —> 0 Page fault. 4 will
takes place of 1 —> 1 Page Fault.
Now for the further page reference string —> 0 Page fault because they are already available in the
memory.
Optimal page replacement is perfect, but not possible in practice as the operating system cannot know
future requests. The use of Optimal Page replacement is to set up a benchmark so that other
replacement algorithms can be analyzed against it.
3. Least Recently Used: In this algorithm, page will be replaced which is least recently used.
Example-3: Consider the page reference string 7, 0, 1, 2, 0, 3, 0, 4, 2, 3, 0, 3, 2, 3 with 4 page frames.
Find number of page faults.
Initially, all slots are empty, so when 7 0 1 2 are allocated to the empty slots —> 4 Page faults
0 is already their so —> 0 Page fault.
when 3 came it will take the place of 7 because it is least recently used —>1 Page fault
0 is already in memory so —> 0 Page fault.
4 will takes place of 1 —> 1 Page Fault
Now for the further page reference string —> 0 Page fault because they are already available in the
memory.
4. Most Recently Used (MRU): In this algorithm, page will be replaced which has been used recently.
Belady’s anomaly can occur in this algorithm.
Cache is a technique of storing a copy of data temporarily in rapidly accessible storage memory. Cache
stores most recently used words in small memory to increase the speed at which data is accessed. It
acts as a buffer between RAM and CPU and thus increases the speed at which data is available to the
processor.
Whenever a Processor wants to write a word, it checks to see if the address it wants to write the data
to, is present in the cache or not. If the address is present in the cache i.e., Write Hit.
We can update the value in the cache and avoid expensive main memory access. But this results
in Inconsistent Data Problem. As both cache and main memory have different data, it will cause
problems in two or more devices sharing the main memory (as in a multiprocessor system).
This is where Write Through and Write Back comes into the picture.
Write Through:
In write-through, data is simultaneously updated to cache and memory. This process is simpler and
more reliable. This is used when there are no frequent writes to the cache(The number of write
operations is less).
It helps in data recovery (In case of a power outage or system failure). A data write will experience
latency (delay) as we have to write to two locations (both Memory and Cache). It Solves the
inconsistency problem. But it questions the advantage of having a cache in write operation (As the
whole point of using a cache was to avoid multiple access to the main memory).
Write Back:
The data is updated only in the cache and updated into the memory at a later time. Data is updated in
the memory only when the cache line is ready to be replaced (cache line replacement is done using
Belady’s Anomaly, Least Recently Used Algorithm, FIFO, LIFO, and others depending on the application).
Write Back is also known as Write Deferred.
Dirty Bit: Each Block in the cache needs a bit to indicate if the data present in the cache was modified
(Dirty) or not modified(Clean). If it is clean there is no need to write it into the memory. It is designed
to reduce write operation to a memory. If Cache fails or if the System fails or power outages the
modified data will be lost. Because it’s nearly impossible to restore data from cache if lost.
If write occurs to a location that is not present in the Cache(Write Miss), we use two options, Write
Allocation and Write Around.
Memory Interleaving is less or More an Abstraction technique. Though it’s a bit different from
Abstraction. It is a Technique that divides memory into a number of modules such that Successive words
in the address space are placed in the Different modules.