Program [Link].
ROBOTICS AND ARTIFICIAL INTELLIGENCE
Course Code Course Name L T P C
244RA1A35TB DIGITAL ELECTRONICS
3 0 0 3
Year and Semester II Year ( III Semester ) Contact hours per week
3 Hrs.
Prerequisite course Nil
Course category Humanities and Social Management courses Professional Core Professional Elective
Sciences
√
Basic Science Engineering Science Open Elective Mandatory
Course Objective 1 Acquire basic knowledge of Digital fundamentals.
2 Explore the way of various combinational circuit.
3 Examine the concept of synchronous sequential circuits.
4 Assess the concept of a synchronous sequential circuits.
Appraise and analyze the concept and applications memory devices and digital integrated
5
circuits.
Course Outcome CO1 Explain and understand the basic concept of Digital fundamentals.
CO2 Illustrate the basic concepts of combinational circuit.
CO3 Examine the concept of synchronous sequential circuits.
CO4 Appraise and analyze the concept of a synchronous sequential circuits.
Analyze and explain the concept and applications and applications memory devices and digital
CO5
integrated circuits.
Study, create a simple application or solve the problems using the concept of Digital
CO6
Electronics.
CO-PO ATTAINMENT
POs /
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2 PSO3
COs
CO1 3 2 3 2 2 - - - - - - - 3 1 1
CO2 3 2 3 2 1 - - - 1 1 - 2 3 2 1
CO3 3 3 3 3 - - - - - - - - 3 3 1
CO4 3 3 3 3 - - - - 1 1 - 2 3 2 2
CO5 3 2 3 2 2 - - - 1 1 - 2 3 2 2
CO6 3 2 3 2 2 - - - 1 1 - 2 3 2 2
Average 3 2.3 3 2.3 1.7 - - - 1 1 - 2 3 2 1.5
CORRELATION LEVELS 1. SLIGHT (LOW) 2. MODERATE (MEDIUM) 3. SUBSTANTIAL (HIGH)
UNIT 1 DIGITAL FUNDAMENTALS 9 Hrs
Number Systems – Decimal, Binary, Octal, Hexadecimal, 1‘s and 2‘s complements, Codes – Binary, BCD, Excess 3, Gray,
Alphanumeric codes, Boolean theorems, Logic gates, Universal gates, Sum of products and product of sums, Minterms and
Maxterms, Karnaugh map Minimization and Quine-McCluskey method of minimization.
UNIT 2 COMBINATIONAL CIRCUIT DESIGN 9 Hrs
Design of Half and Full Adders, Half and Full Subtractors, Binary Parallel Adder – Carry look ahead Adder, BCD Adder,
Multiplexer, Demultiplexer, Magnitude Comparator, Decoder, Encoder, Priority Encoder
UNIT 3 SYNCHRONOUS SEQUENTIAL CIRCUITS 9 Hrs
Flip flops – SR, JK, T, D, Master/Slave FF – operation and excitation tables, Triggering of FF, Analysis and design of
clocked sequential circuits – Design - Moore/Mealy models, state minimization, state assignment, circuit implementation –
Design of Counters- Ripple Counters, Ring Counters, Shift registers, Universal Shift Register.
UNIT 4 ASYNCHRONOUS SEQUENTIAL CIRCUITS 9 Hrs
Stable and Unstable states, output specifications, cycles and races, state reduction, race free assignments, Hazards, Essential
Hazards, Pulse mode sequential circuits, Design of Hazard free circuits.
UNIT 5 MEMORY DEVICES AND DIGITAL INTEGRATED CIRCUITS 9 Hrs
Basic memory structure – ROM -PROM – EPROM – EEPROM –EAPROM, RAM – Static and dynamic RAM -
Programmable Logic Devices – Programmable Logic Array (PLA) - Programmable Array Logic (PAL) – Field
Programmable Gate Arrays (FPGA) - Implementation of combinational logic circuits using PLA, PAL. Digital integrated
circuits: Logic levels, propagation delay, power dissipation, fan-out and fan-in, noise margin, logic families and their
characteristics-RTL, TTL, ECL, CMOS
Total : 45 Hrs
Text Book:
1. M. Morris Mano and Michael D. Ciletti, “Digital Design”, 5th Edition, Pearson, 2014.
Reference Books:
1. Charles [Link]. “Fundamentals of Logic Design”, 6th Edition, Thomson Learning, 2013.
2. Thomas L. Floyd, “Digital Fundamentals”, 10th Edition, Pearson Education Inc, 2011
3. [Link] and [Link]“Digital Electronics”, Ist Edition, Vikas Publishing House pvt Ltd, 2012.
4. Anil [Link] “Digital Electronics”, Wiley, 2014.
Reference web site:
1. [Link]
2. [Link]
3. [Link]
Document Prepared in “ Board of Studies” held on Document Approved in “ Academic Council” held on
Date: _____08/05/2024_______________________ Date: ____19/08/2024________________________
Controlled Copy F199/ Rev 01/ 09.11.2021