Lecture2
Introduction(PartII)
VLSI Physical Design Fundamentals Course
PhilHoang
Tresemi
Specs
ASICDevelopmentFlow
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
2
Fr ont
-
EndDesi gn
Back
-
EndDesi gn
Chip S pe c ific a tion
Mic ro
-
a rc hitec ture Des ign
RTL Des ign
Arc hitec tura l Des ign
Logic S ynthe s is
P hys ic a l De s ign
Ma rk e tRes e a rch
Ma rket ingRequ ire m entDocu m en t(MRD)
Arc hitec tura l Le ve l
Regi s ter
-
Tra ns fer
Le ve l (RTL)
Ga teLe ve l
Transis torLevel
P rod u ctRequ ire m en tDocu m e nt(PRD)
(How achi pi sbui l t
-
si mpl i fi ed)
Does thechiphaveal l ther equi r ed
functi onalities?
I sthedesi gnadequatefor meeti ng
per for mancegoal s?
Doesthechi pmeetall ther equi r ed
per for mancespeci fi cations?
Levels of Abs tra ct ion
Circ uit Des ign
P hys ic a l Le ve l
Whatdoesthechi pdo?
How fastdoesi tneedtooper ate?
How muchpow erw i lli tconsume?
How bi gw il li tbe?
How muchw i lli tcost?
Back
-
EndDesi gn
Fr ont
-
EndDesi gn
IC DesignConceptualFlow
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
3
RTL Des ign
V e rific a tion
S ynthe s is
P hys ic a l Des ign
S ignoff
Fa bric a tion / P a c k aging
Devic e s
S pe c ific a tions
Te s ting
IC DevelopmentFlow(Simplified)
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
4
M anufactur ing& Testi ng
Si mul ati ons&Si gnoff
Fr ont
-
EndDesi gn
Back
-
End
Design
Chip S pe c ific a tion
Mic ro
-
a rc hitec ture Des ign
RTL Des ign
Arc hitec tura l Des ign
Logic S ynthe s is
Logic E quiva le nc e Che c k
P hys ic a l Des ign
Functional S imul a tions
S ys tem V e rific a tion
Ma rk e tRes e a rch
Ma rke tin gRe qu ire m entDo cu m en t(MRD)
Be ha vioralMod els
Fu n ctio n alMo d e ls
RT L Net lists
Ga te
-
Le vel
Net ist
P h ysicalL a yo u t
P rod u ctRequ ire m en tDocu m e nt(PRD)
E MIR Ana lys is
P ow e rAna lys is
Dyna mic Timi ng Ana lys is
S tatic Tim ing Ana lys is
P hys ic a l V e rific a tion
TapeOut
Con stra int s
T e stB e n ch es
FPG A P rototyping
Sim ula tionDum pFiles
ATPG
T e stP a tt e rns
Mas k Mak ing
Fabrica tion
Pa ck aging
S il ic on
V a li da tion
Del ive ry
DigitalDesignSystemExample
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
5
Inf rast ru ctu re
C om puteInf r as tr uc ture
D es ign Envir onm ent
Proj ec tD ir ec tory Struc ture
R evis ion C ontr ol
I mage s ourc e: S k y w ork s
Design
Automat ion
DES IG N
IMP LE ME NTATIO N
S IG N
-
OFF
E DA
Flow s
E DA
Tools
I nfr astr uctur e
Desi gn
Re
-
use
(I P)
DigitalImplementationFlowExamples
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
6
Sign
-
Off
Pl aceand Route
Post
-
SynthesisAnal ysis
Logi cSynthesis,DFT
Mem oryB uil t
-
In
-
Sel f
-
T est
Init ializ e
Project /W orkspace
Pr epare
ReferenceData
Int ernal
Design
Automat ion
I mage s ourc e: S k y w ork s
Place andRoute(P&R)Flow
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
7
In p u tsa reva lid
Con stra int sa reco m p let e
I mpor t
Fl oor pl anning
Pl acement
Routi ng
Expor t
Flo o rpla n DB
P lace m en tDB
Cl ockTr eeSynthesi s
CT S DB
Rou te DB
Steps
Rea d a n d ch e ck
qu a lity o f inp u ts
Def ine B ou ndarie s
S e tu p p lace me nt
a rea sf o rd if f erent
typ e s o f co m p o nen ts
Cre a te th e P o we r
Distrib u tio n S tru ctu res
Im po rtDB
P lace a llco m p o ne nts
Design is rou ta b le
IR d rop is b e lowlim its
T im ingclosu reis f e a sible
Designis rou ta ble
Notim ingviolation s
P o we rco n su m p tionis m inim ize d
B u ild th e clocktre e s
Clo cktre e sa reo p tim ize d
f o rtim inga n d p o we r
Rou te a llsign a ls
Design is f ree o f d e sign
rule e rro rs
Notim ingviola tio n s
IR d rop is b e lowlim its
P o we ris with in b u d ge t
Design is relia b le
Design is m a n u f acturable
Design is rea d y f o r
ve rif icat ion a n d th e n
o n to Ma n u f actu ring
W riteo u tp u ts
I nputs
Ga te Le vel
Net list
CellA b stra cts
T imin g
Con stra int s
Ph ysical
Con stra int s
Outputs
Ga te L e ve lNet list
L a yo u t
QO R Rep o rts
FAB
Primary Goals
ofPhysicalDesign
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
8
µ
PPA
Opti mi z at io n:
fin di ng the ri ght
bal anc e a mong the se 3 f ac tors to
ac hi eve an opt imal de si gn for a
sp ec ifi capp li ca tio n o r us e c as e:
#¸
P
er for m an ce
Enha nce overall processing
capabil i ti es.
Meeti ng ti mingconstrai nts.
#¸
P
ower
Mini mizepower consumpti on for
extended battery l i fe,reduced energy
costs, and effecti ve thermal
management.
#¸
A
r ea
Mini mizechi parea to enhance cost
effi ci ency i nmassproducti on.
µ
R
elia bili ty and
Robus tnes s:
#¸
Ensure pr oper functio nality
unde r all oper ating
conditio ns and
environm ental factors.
µ
M
an uf ac tu rab il it y:
#¸
Optim ize the d esign for
ma nufa ctur ability to im pr ove
the yield of th e
ma nufa ctur ing pr ocess.
µ
P
roductivity:
#¸
Achieve ra pid closur e of all
design goals, contr ibuting to
the successfu l deliver y of
high
-
quality ICs.
Th eprimary go alsof ph ysical d esig n encompass op timizi ng in tegratedcircuits
fo r sup erio r
performance, mini mizin gpow erconsumpti on ,and efficient chip area uti li
zation .
PPA
RMP
Longe r Batte ry Life
More P ow e rful
Better Ther mal
Le s s E x pe ns ive
Performance
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
9
PPA
RMP
P erform ance
P ow er
Area
Rel i abi l i ty
Robustness
M anufactura
bi l i ty
P roducti vi ty
Doesthedesi gnmeetal l the
ti mingconstrai nts?
Understandi ngDelays
Under standi ngTi mi ng
Constrai nts
UnderstandingDelays
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
10
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Delays
GateDelay
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
11
a. k . a.
Cel l Del ay
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Moreont his
lat er
Net
Delay
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
12
a. k . a.
Wir eDela y
I nterconnectDelay
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Moreont his
lat er
SynchronousDesign
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
13
Timing
Constraint s
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
StaticTimingAnalysis(STA)
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
14
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
TimingConstraints
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
15
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
ClockTerminologies
Period,DutyCycle,Edges
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
16
Del ays
Ti m i ng
Constrai nts
Duty
Cycl e
Per i od
Clocks
Edges
Creatinga Clockor GeneratedClock
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
17
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
ClockSkews
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
18
Del ays
Ti m i ng
Constrai nts
Skew s
ClockUncertainty
ClockLatency
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
19
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Uncertaint y
Latency
Setup&HoldTime
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
20
Del ays
Ti m i ng
Constrai nts
Setup
Time
Hold
Time
Max Delay/ MinDelay
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
21
Del ays
Ti m i ng
Constrai nts
Setup(Max)Constraint
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
22
Del ays
Ti m i ng
Constrai nts
Hold(Min)Constraint
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
23
Del ays
Ti m i ng
Constrai nts
Setup/Hold
Summary
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
24
Del ays
Ti m i ng
Constrai nts
I/OConstraints
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
25
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
I/O
I/OConstraintsSummary
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
26
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
CaseAnalysis/ DesignRules
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
27
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Case
Multi
-
CyclePaths
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
28
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Timing
Excepti ons
FalsePaths
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
29
Perf o rman ce
Del ays
Ti m i ng
Constrai nts
Timing
Excepti ons
Multi
-
ModeMulti
-
Corner(MMMC)
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
30
Del ays
Ti m i ng
Constrai nts
TCL
Design
Contraints
SDC
Modes &
Corners
Moreont his
lat er
MMMCExamples
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
31
creat e_c onst raint _mo de
-
name
cm_ func
-
sdc _fi les
func. sdc
creat e_c onst raint _mo de
-
name
cm_ test
-
sdc _fi les
test. sdc
create_
library_set
-
name
ls_slow
#w
timing [listlibs/lib/sc_slow.lib libs/mem_slow.lib]
creat e_
l ibra ry_se t
-
name
ls_
f ast
#w
ti ming [li stl ibs/l ib/ sc_f ast.l ib libs /mem_ fas [Link] b]
create_rc_corner
-
name
rc_max
#w
cap_table
libs/
captbl
/worst/
c apTab le
creat e_r c_co rner
-
na me
r c_
min
#w
c ap_t able
lib s/
ca ptbl
/ bes t/
capTable
create_
delay
_corner
-
name
d
c_max
#w
library_set
ls_slow
#w
rc_corner
rc_max
creat e_
d elay
_corn er
-
nam e
d
c_
min
#w
li brary _se t
ls _
fast
#w
r c_co rner
rc_ min
creat e_a naly sis_v iew
-
name
av _fu nc_m ax
#w
d ela y_co rner
dc_ max
#w
cons tra int_ mode
fun c
create_analysis_view
-
name
av_
test
_min
#w
delay_corner
dc_min
#w
constraint_mode
test
set_analysis_view
-
setup [list
av_func_max
]
-
hold[list
av_test_min
]
P &R
Inp uts
Desi gn
Netl i st
Cel l
Abstracts
Ti m i ng
Constrai nts
P hysi cal
Constrai nts
TimingDerates
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
32
Examples:
Add 3% toall max delays:
#¸
set_timing_derate
#w
delay_corner
dc_max
#w
ce ll_d elay
#w
late 1.03
Subtract 3% toallmindelays:
#¸
set_timing_derate
#w
delay_corner
dc_min
#w
ce ll_d elay
#w
early 0.97
P &R
Inp uts
Desi gn
Netl i st
Cel l
Abstracts
Ti m i ng
Constrai nts
P hysi cal
Constrai nts
More later
Time to
TimingClosure
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
33
µ
PPA
Opti mi z at io n:
fin di ng the ri ght
bal anc e among thes e 3 fa cto rs to
ach ieve an opti mal d esi gn fo r a
sp ec ifi capp li ca tio n o r us e c as e:
#¸
P
er for m an ce
Enha nce overall processing
capabi l i ti es.
Meeti ng ti mingconstrai nts.
#¸
P
ower
Mini mizepower consumpti on for
extended battery l i fe,reduced energy
costs, and effecti ve thermal
management.
#¸
A
r ea
Mini mizechi parea to enhance cost
effi ci ency i nmassproducti on.
µ
R
elia bili ty and
Robus tnes s:
#¸
Ensure pr oper functio nality
unde r all oper ating
conditio ns and
environm ental factors.
µ
M
an uf ac tu rab il it y:
#¸
Optim ize the d esign for
ma nufa ctur ability to im pr ove
the yield of th e
ma nufa ctur ing pr ocess.
µ
P
roductivity:
#¸
Achieve ra pid closur e of all
design goals, contr ibuting to
the successfu l deliver y of
high
-
quality ICs.
Th eprimary go alsof ph ysical d esig n encompass op timizi ng in tegratedcircuits
fo r sup erio r
performance, mini mizin gpow erconsumpti on ,and efficient chip area uti li
zation .
PPA
RMP
Longer Batter y Life
More P ow e rful
Bette rTher ma l
Le s s E x pe ns ive
TimetoTimingClosure!
References
© T rese m i20 24
VL SI Ph ysicalDesignEn gine eringFun da ment als
p.
34
CMOSVL SIDesign
Weste
-
H arris
D igital IntegratedC ircuits
Jan
Rabaey
2011
L
ecture
N
otes
-
D avidMoneyH arris
D igital V LSID esign
Adam
Tem an
Principles of V LSID esign
Jim
Plusquellic
Digital IntegratedCircuits
YuZhuo
Fu
V LSI Back
-
End Adventure, A SICBlog
V LSI Phy sicalD esignForFresher
SoCPhy sicalDesign
V LSI Expert
A SIC
-
Sy stemon C hip
-
V LSID esign
Fr omLogic to Lay out
Rob
Rutenbar
asic
back
-
end
-
[Link]
Sy stem
-
on
-
ChipD esign
AnandRaghunathan
Phy sicalD esignFlow
Mohamm ad
Kakoee
TeamV LSI Blog
C adenceOnline Support
Site and YouT ubeV ideos
Reliability of segmentededgeseal ringf orRF devices
-
J. G am bino, etal.
A R eliable I/O R ingFor AR eliableSoC
Abdelliah
Bakhali
A pply Wirebonding P BGAorFlip C hip PB GA ?
-
FionaZhang
FloorplanStrategiesf orMacroDominatingBlocks
Team VLSI
FloorplanGuidelines f orSub
-
MicronTechnology
N odef orN etw orkingC hips
-
D havalS. Shukla