ST.

XAVIER’S COLLEGE

MICROPROCESSOR
CSC - 153

Er. Anil Sah

8/6/2013

The course objective is to introduce the operation ,

programming and application of microprocessor.
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UNIT 1
INTRODUCTION TO MICROPROCESSOR

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MICROPROCESSOR

• A Microprocessor is a multipurpose, Programmable clock-

driven, register based electronic device that read binary
instruction from a storage device called memory, accepts
binary data as input and processes data according to those
instructions and provides results as outputs.
• A Microprocessor is a clock driven semiconductor device
consisting of electronic circuits manufactured by using either
a LSI or VLSI technique.
• A typical programmable machine can be represented with
three components : MPU,Memory and I/O as shown in Figure

Figure: A Programmable Machine

• These three components work together or interact with

each other to perform a given task; thus they comprise a
system
• The machine (system) represented in above figure can be
programmed to turn traffic lights on and off, compute
mathematical functions, or keep trace of
guidance system.
• This system may be simple or sophisticated, depending on
its applications.
• The MPU applications are classified primarily in two
categories : reprogrammable systems and embedded
systems
• In reprogrammable systems, such as Microcomputers, the
MPU is used for computing and data processing.
• In embedded systems, the microprocessor is a part of a
final product and is not available for reprogramming to end
user.

MICROCOMPUTER
• As the name implies, Microcomputers are small computers
• They range from small controllers that work directly with 4-
bit words to larger units that work directly with 32-bit words
• Some of the more powerful Microcomputers have all or
most of the features of earlier minicomputers.

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• Examples of Microcomputers are Intel 8051 controller-a
single board computer, IBM PC and Apple Macintosh
computer.

MICRO CONTROLLER
• Single-chip Microcomputers are also known as
Microcontrollers.
• They are used primarily to perform dedicated functions.
• They are used primarily to perform dedicated functions or
as slaves in distributed processing.
• Generally they include all the essential elements of a
computer on a single chip: MPU,R/W memory, ROM and I/O
lines.
• Typical examples of the single-chip microcomputers are the
Intel 8051, AT89C51, AT89C52 and Zilog Z8.
• Most of the micro controllers have an 8-bit word size, at
least 64 bytes of R/W memory, and 1K byte of ROM
• I/O lines varies from 16 to 40

Typical Example: AT89C51 Microcontroller

• It is low power, high performance CMOS 8 bit
microcomputer with 4K bytes of Flash programmable and
erasable Read Only Memory.
• 128 bytes of Internal RAM
• 32 I/O pins arranged as 4 ports (PO-P3)
• A full duplex serial port
• 6 Hardware Interrupts
• 16 bit PC and Data Pointers.
• 8 bit Program Status Word
• Two 16 bits timers/counter TO and T1

MEMORY CALCULATIONS
• 210 =1K(Kilo)
• 220=1M(Mega)
• 230=1G(Giga)
• 240=1T (Tera)
• Specify Data and Address Bus size and calculate the size of
Memory.

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APPLICATIONS OF MICROPROCESSOR
• Microcomputers
• Industrial Control
• Robotics
• Traffic Lights
• Washing Machines
• Microwave Oven
• Security Systems
• On Board Systems

EXAMPLE: A SYSTEM DESIGN WITH MPU

• SMART Fan
• Access Control System
• Automated Water Tank

EVOLUTION OF MICROPROCESSOR: INTEL SERIES

4004
• The first commercially available Microprocessor was the
Intel 4004 produced in 1971.
• It contained 2300 PMOS transistors.
• The 4004 was a 4 bit device intended to be used with some
other devices in making a calculator.
• In 1972 Intel came out with the 8008,which was capable of
working with 8 bit words.

8008
• The 8008, however required 20 or more additional devices
to form a functional
CPU.

8080
• In 1974 Intel announced the 8080, which had a much
larger instruction set than the 8008 and required only two
additional devices to form a functional CPU.
• The 8080 used NMOS transistor, so it operated much faster
than the 8008
• The 8080 is referred as a Second generation
Microprocessor.
• It requires +5V,-5V and +12V supply.

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8085
• In 1977, Intel Produced 8085, an upgrade of 8080 that
required only a +5V supply
• It was a 8 bit Microprocessor.

8088
• Intel Produced 8088, which was the first Microprocessor
used in Personal computer by IBM.
• It has 16 bit registers and an 8 bit data bus and can
address up to 1 million bytes of internal memory.

8086
• In 1978 Intel came out with the 8086 which is a full 16 bit
Microprocessor.
• It has a 16 bit data bus and runs faster.
• It can address 220 or 1048576 memory locations.

80286
• Runs faster than the preceding processors, has additional
capabilities and can address up to 16 million bytes.
• This processor can operate in real mode or in protected
mode, which enables an operating system like windows to
perform multitasking and to protect them from each other.

80386
• Has 32 bit registers and 32bit data bus.
• It can address up to 4 billion bytes of memory.
• The processor supports virtual mode, whereby it can swap
portions of memory onto disk.

80486
• Has 32 bit registers and 32 bit data bus.
• High speed cache memory connected to the processor bus
enables the processor to store copies of the most recently
used instructions and data.
• The processor can operate faster when using the cache
directly without having to access the slower memory.

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PENTIUM
• It has 32 bit registers, a 64 bit data bus and separate
caches for data and for memory.
• The Pentium has a 5 Stage pipelined structure and the
Pentium II has a 12 stage super pipelined structure.
• This feature enables them to run many operations in
parallel.

Stored Program concept: The task of entering and altering

the programs for the ENIAC (electronic numerical integrator
and computer) was extremely tedious. The programming
concept could be faciliated if the program could represented
in a form suitable for storing in memory along side the data.
Than a computer could get it's instruction by reading them
form the memory and a program could be set or altered by
setting the values of a portion of memory . This approach is
known stored program concept.

Main memory is used to store both data and instruction ALU

is capable for performing Arithmetic and logical operation
binary data. The program control unit(cpu) interprets the
instruction in memory and causes them to be a execute. The
input/output unit and helps inputting data and getting
results. The memory of Von-Neumann machine consists of
thousand storage location called words of 40 binary
digits(bits). Both data and instruction are stored in it. The
storage locations of control unit and ALU are called registers.
The various registers of this model are MBR, MAR, IR, IBR,
PC, AC.

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Memory Buffer Register: It consist of a word to be stored
in memory or is used to receives a memory or is used to
receive a word from memory.

Memory address Register: It contain the address in

memory of the world to be written from or read into the
MBR.

IR(Instruction register): Contain the 8 bit upcode

(operation code) instruction being executed.

IBR(instruction buffer register): It is used to temporarily

hold the instruction from a word in memory.

PC (program counter): It contain address of next

instruction to be fetched from memory.

Ac (Accumulator) and MQ(multiplier quotient): They

are employed to temporarily hold operands and results of
ALU operations.

Harvard Architecture:

Address
Program mermory Address bus
bus

Data mermory Address bus

Control program Data

bus central counter memroy Data
control Arithmatic related address program Memory
unit unit Hardware arithmatic Memory
unit

Data
bus Program mermory Data bus

Data mermory Data bus

Fig. Block diagram of the Harvard architecture based µP

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Harvard Architecture based computer consist so separate
memory spaces for the programs (or instruction) and
[Link] memory space has it's own address and data bus.
Thus both instruction and data can fetch from memory
concurrently. From the figure it is seen that there are two
data and two and address buses for the program and data
memory spaces respectively. The program memory data bus
and data memory data are multiplexed to form single data
bus where as program memory Address and data memory
address are multiplexed to form single address bus. Hence
there are two blocks of ram chip. One for program memory
and another for data memory space. Data memory address
arithmetic unit generates data memory address. The data
memory address bus carries the memory address of data
where as program memory address bus carries the memory
address of the instruction. Central arithmetic logic unit
consists of the ALU, multiplier, Accumulator, etc. The
program counter is used to address program memory. Pc
always contains the address of next instruction to be
fetched. Control unit control the sequence of operations to
be executed. The data and control bus are bidirectional
where as address bus is unidirectional.

GENERAL ARCHITECTURE OF MICROCOMPUTER

SYSTEM

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• Figure shows a block diagram for a simple Microcomputer.
• The major parts are the CPU, Memory and I/O.
• Connecting these parts are three sets of parallel lines called
buses.
• The three buses are address bus, data bus and the control
bus.

MEMORY
• It consists of RAM and ROM.
• The First Purpose of memory is to store binary codes for
the sequences of instructions you want the computer to
carry out.
• The second purpose of the memory is to store the binary-
coded data with which the computer is going to be working.

INPUT/OUTPUT
• The input/output or I/O Section allows the computer to
take in data from the outside world or send data to the
outside world.
• Peripherals such as keyboards, video display terminals,
printers are connected to I/O Port.

CPU
• The CPU controls the operation of the computer.
• In a microcomputer CPU is a microprocessor.
• The fetches binary coded instructions from memory,
decodes the instructions into a series of simple actions and
carries out these actions in a sequence of steps.
• The CPU also contains an address counter or instruction
pointer register, which holds the address of the next
instruction or data item to be fetched from memory.
INPUT
DEVICE
O/P
DEVICE
I/O PORT CPU MEMORY

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ADDRESS BUS
• The address bus consists of 16, 20, 24 or 32 parallel signal
lines.
• On these lines the CPU sends out the address of the
memory location that is to be written to or read from.
• The no of memory location that the CPU can address is
determined by the number of address lines.
• If the CPU has N address lines, then it can directly address
2N memory locations i.e. CPU with 16 address lines can
address 216 or 65536 memory locations.

DATA BUS
• The data bus consists of 8, 16 or 32 parallel signal lines.
• The data bus lines are bi-directional.
• This means that the CPU can read data in from memory or
it can send data out to memory.

CONTROL BUS
• The control bus consists of 4 to 10 parallel signal lines.
• The CPU sends out signals on the control bus to enable the
output of addressed memory devices or port devices.
• Typical control bus signals are Memory Read, Memory
Write, I/O Read and I/O Write.

COMPONENTS OF CPU

Figure: Microprocessor Based System with Bus

Architecture.

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• The Microprocessor is divided into three segments: ALU,
Register array and Control Unit.

ARITHMETIC LOGIC UNIT

•This is the area of Microprocessor where various computing
functions are performed on data.
•The ALU performs operations such as addition, subtraction
and logic operations such as AND, OR and exclusive OR.

REGISTER ARRAY
• These are storage devices to store data temporarily.
• There are different types of registers depending upon the
Microprocessors.
•These registers are primarily used to store data temporarily
during the execution of a program and are accessible to the
user through the instructions.
• General purpose Registers of 8086 includes AL, AH, BL, BH,
CL, CH, DL, DH.

CONTROL UNIT
• The Control Unit Provides the necessary timing and control
signals to all the operations in the Microcomputer
• It controls the flow of data between the Microprocessor and
Memory and Peripherals.
• The Control unit performs 2 basic tasks
o Sequencing
o Execution

1. SEQUENCING
• The control unit causes the processor to step through a
series of micro-operations in the proper sequence, based on
the program being executed.

2. EXECUTION
• The control unit causes each micro operation to be
performed.

CONTROL SIGNALS

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• For the control unit to perform its function it must have
inputs that allow it to determine the state of the system and
outputs that allow it to control the behavior of the system.
• Inputs : Clock , Instruction Register, Flags
• Outputs :
o Control signals to Memory
o Control signals to I/O
o Control Signals within the Processor.

LEVEL OF INTEGRATION

SSI: Small Scale Integration

• No of gates Less than 10.

MSI: Medium Scale Integration

• No of gates between 10-100.

LSI: Large Scale Integration

• No of gates between 100-1000.

VLSI: Very Large Scale Integration

• More than 1000 gates in a single chip.

ULSI: Ultra Large Scale Integration

• Millions of gates in a single chip.

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Unit 2
Basic Computer Architecture

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INTRODUCTION
SAP Architectures, Instructions, Microprogram; 8 8-bit "W"
bus, 4-bit
bit program counter, 4-bitbit Memory Address Register
(MAR), 16x8-bitbit memory, 8-bit
8 bit instruction register (IR), 6
6-
cycle controller with 12-bit
12 micro-instruction
instruction word, 8-bit
8
accumulator, 8-bitbit B register, 8-bit
8 adder-subtractor,
subtractor, 8
8-bit
output register, SAP-1
SAP 1 Instructions, Fetch & Ex Execution,
microprogram, fetch cycle, execution cycle, microprogram,
controller implementation, SAP 2 Architecture, architectural
differences with SAP
SAP-1, bi-directional
directional registers, instruction
set, flags.

SAP 1(SIMPLE AS POSSIBLE 1)

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W -Bus

• A single 8 bit bus for address and data transfer.

• All register outputs to the W- bus are three state. This
allows orderly transfer of data.
Program Counter
• Sends address of next instruction to be fetched and
executed to the memory.
• Counts from 0000 to 1111.
• Points where something important is being stored.
Input and MAR
• MAR- Memory Address Register.
• Includes the address and data switch register.
• Switch register allows you to send 4 address bits and 8
data bits to RAM.
• Address from program counter latches into MAR.
RAM
• 16 X 8 Static TTL RAM.
• Allows you to store data before a program runs.
• Programmed by means of address and data switch.
• Receives 4 bit addresses from MAR and read operation
is performed.
• Instructions and data word are placed in W-bus.
Instruction Register
• Computer does a memory read operation.
• Places the contents of addressed memory location on W
bus.
• Contents spilt into two nibbles
o Upper nibble (2 State) Controller Sequence
o Lower nibble (3 State) W Bus

Controller Sequence

• Sends CLR signal to program counter.

• Sends CLR signal instruction register.
• Sends CLK signal to all buffer register.

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 • Sends CLK signal to program counter.
• Forms a control word.
• Determines how register will react to next clock edge.

Accumulator

• Stores intermediate answers.

• Low CE + Low LA = Accumulator
• Two state output goes to the adder – subtracter.
• Three state output goes to the W – bus.

The adder- subtracter

• Uses 2’s compliment adder subtracter.

• SU high S= A+B
• SU low S= A+B’
• Is asynchronous (unclocked)

B Register

• Buffer register used in arithmetic operation.

• Low LB + Positive Clock Edge= B register.
• Supplies the number to be added and subtracted to the
adder-subtracter.

Output Register

• Used to transfer the answer to outside world.

• High EA + low LO =Output Register.
• Also known as Output Port.
• Peripheral devices are connected to Output port.

Binary Display

• Row of eight light emitting diode.

• Connected to the output port.

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MNEMONIC OPERATION OPCODES

LDA Load RAM data into 0000

accumulator
ADD Add RAM data to 0001
accumulator
SUB Subtract RAM data from 0010
accumulator
OUT Load accumulator data into 1100
output register
HLT Halt or Stop processing. 1111

SAP 1 Instruction Set

• The instruction format of SAP-1 Computer is
(XXXX) (XXXX)
• Opcode address
LDA
• A complete LDA instruction includes the hexadecimal
address of data to be loaded
• For eg: LDA 8H means “ load the accumulator with
the contents of memory location 8H”
ADD
• A complete ADD instruction includes the address of
the data to be added.
• For eg: ADD 9H means “ add the contents of memory
location 9H to the the content of the accumulator”
• The sum replaces the original content of
accumulator.
SUB
• A complete SUB instruction includes the address of
the data to be subtracted.

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 • For e.g.: ADD CH means “ subtract the contents of
memory location CH from the content of the
accumulator”
• The difference replaces the original content of
accumulator.

OUT
• OUT instruction tells SAP-1 computer to transfer
contents to the output port.
• For e.g.: ADD CH means “ subtract the contents of
memory location CH from the content of the
accumulator”
• It is complete by itself.

HLT
• HLT instruction tells the computer to stop processing of
data and end the program.
• It is complete by itself

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 FETCH CYCLE

Address State
• Address in the program counter(PC) is transferred to
the memory address register(MAR)
• The controller sequencer is sending CON=
CPEPLMCE LI EI LAEA SUEULBLO
o =0 1 0 1 1 11 0 0 0 1 1
during this state
Increment state
• The program counter is incremented
• The controller-sequencer produces a control word of
CON= CPEPLMCE LI EI LAEA SUEULBLO

=1 0 1 1 1 11 0 0 0 1 1

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 Memory State
• The addressed RAM instruction is transferred from the
memory to the instruction register
• The active parts during this state is MAR, RAM, IR and
CON
• The controller-sequencer produces a control word of
CON= CPEPLMCE LI EI LAEA SUEULBLO
= 0 0 10 011 0 0 01 1

The Execution Cycle

• The control unit generates the control words that fetch

and execute each instruction,
• While each instruction is fetched and executed, the
computer passes through different timing states (T
states), periods during which register contents change.
• There are six T states:
o T1
o T2
o T3
o T4
o T5

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 o T6

Execution Cycle
• The next three states (T4, T5 and T6) are the execution
cycles of SAP-1
• The register transfers during the execution cycle
depend on the particular instruction being executed.
• For example, LDA 14H requires different register
transfers than ADD BH.
LDA Routine
• Let us assume that the instruction register has been
loaded with LDA 9H:
• IR = 0000 1001
• During T4 state, the instruction field 0000 goes to the
controller- sequencer, where it is decoded; the address
field 1001 is loaded into MAR.
• In T4 state, E1 and LM are active; all other control bits
are inactive.
• During the T5 state, CE and LA go low.
• This means that the addressed data word in the RAM
will be loaded into the accumulator on the next positive
clock edge.
• T6 state is a NO- OPERATION state.
• During this third execution state, all registers are
inactive.
• This means that the controller sequencer is sending out
a word whose bits are all inactive.
• During the T1 state, EP and LM are active; the positive
clock edge midway through this state will transfer the
address in the program counter to the MAR.
• During the T2 state, CP is active and the program
counter is incremented to positive clock edge
• During the T3 state, CE and LI are active; when the
positive clock edge occurs, the addressed RAM word is
transferred to the instruction register.

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 • The LDA execution starts with the T4 state, where LM
and EI are active; on the positive clock edge the
address field in the instruction register is transferred to
MAR.
• During the T5 state, CE and LA are active, this means
that the addressed RAM data word is transferred to the
accumulator on the positive clock edge.
• T6 state in the LDA routine is nop, i.e. no operation.

ADD Routine
• Suppose at the end of the fetch cycle, the instruction
register contains ADD BH
IR = 0001 101
• During the T4 state, the instruction goes to the
controller sequencer and the address field to MAR.
• During this state, EI and LM are active.
• Control bits CE and LB are active during T5 state.
• This allows the addressed RAM word to set up the B
register.
• Loading takes place midway through the state when the
positive clock edge his the CLK input of the B register.
• During the T6 state, EU and LA are active.
• Therefore, the adder- subtracter sets up the
accumulator.
• Halfway through this state, the positive clock edge
loads the sum into the accumulator.
• The setup time and propagation time delay time
prevent racing of the accumulator during this final
execution state.
• When the positive clock edge hits, the accumulator
contents change, forcing the adder- subtracter contents
to change.
• The new contents return to the accumulator input, but
the new contents don’t get there until two propagation
delays after the positive clock edge.
• By then its too late to set up the accumulator. This
prevents accumulator racing i.e. loading more than
once on the same clock edge

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 • The fetch routine is the same as before: the T1 state
loads the PC address into MAR; the T2 state increments
the program counter; the T3 state sends the addressed
instruction to the instruction register.
• During the T4 state, EI and LM are active; on the next
positive clock edge, the address field in the instruction
register goes to the MAR.
• During the T5 state, CE and LB are active; therefore the
addressed RAN word is loaded into the B register
midway through the state.
• During the T6 state, EU and LA are active; when the
positive clock hits, the sum out of the adder/ subtracter
is stored in the accumulator.

MICROPROGRAM:

A set of microinstructions in a CPU, used to implement

machine instructions to manually write a microprogram.
Each microinstruction indicates the machine micro-
operations or micro-orders, the address of the next
microinstruction, the duration of the microinstruction
itself, and special actions relating to test operations. By
changing the sequence and composition of the
microinstructions—that is, by altering the structure of a
microprogram—the system of instructions for a digital
computer can be changed, thus adapting it to a certain
class of problems or providing program compatibility
with another digital computer. Microprograms are
usually stored in a specialized memory, which responds
more rapidly than a direct-access memory.

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 Microinstructions of SAP-1 instructions:

The instructions that have been used for programming

with (LDA,ADD,SUB,…)are sometimes called
macroinstructions. Each SAP1 macroinstruction is made
up of three microinstructions. For example, the LDA
macroinstruction consists of the microinstructions in the
table below.

A list of macroinstruction and microinstructions needed

to carry out are shown below. This table summarizes
the execute routines for SAP-1 instructions.

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SAP 2 (SIMPLE AS POSSIBLE 2)
• Bidirectional registers
• Includes jump instructions
• All register outputs to W bus are three-state; those not
connected to the bus are two-state

Fig: Block diagram of SAP 2 architecture

Input Ports
• 2 input ports numbered 1 and 2
• Hexadecimal keyboard encoder connected to port 1,
sends READY signal to bit 0 of port 2
• This signal indicates when the data in port 1 is valid,
the SERIAL IN, signal going to pin 7 or port 2.

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 Program Counter
• Program counter has 16 bits; therefore it can count
from PC= 0000 0000 0000 000 to PC=1111 1111 1111
1111
• Its job is to send to the memory the address of the next
instructions to be fetched and executed
• A low resets the PC before each computer run; so
the data processing starts with the instruction stored in
memory location 0000H

MAR and Memory

• During the fetch cycle, the MAR receives 16 bit
addresses from PC. The two state MAR output then
addresses memory location.
• The memory has 2K ROM with address 0000H too
07FFH. The ROM contains a program called monitor that
initializes the computer on power-up, interprets the
keyboard inputs and so on.
• The rest of memory is 64 K RAM with addresses from
0800H to FFFFH.

MDR(Memory Data Register)

• 8 bit buffer register
• Its output sets up the RAM
• Receives data from the bus before a write operation
and it sends data to the bus after a read operation

IR(Instruction Register)
• Part of control unit

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 • Memory read operation performed by computer to
fetch an instruction from memory; this places the
contents of the addressed memory location on W bus
• Contents split into 2 nibbles
• SAP 2 use 8 bits for op code which can accommodate
256 instructions

Controller Sequencer
• Produces the control words or microinstructions that
coordinate and direct the rest of the computer
• Has more hardware since SAP 2 has bigger instruction
set
• Microinstruction determines how the registers react to
the next positive clock edge

Accumulator
• A buffer register that stores intermediate answers
during the computer run
• Has two outputs two-state and three-state
• Two-state output goes to ALU and three-state to W bus
• Hence the 8 bit word in the accumulator continuously
drives the ALU, but this same word appears on the bus
only when EA is active

ALU and Flags

• Includes arithmetic and logic operations
• Has 4 or more control bits that determine the arithmetic
or logic operation performed on words A and B
• Flag is a flip-flop that keeps track of a changing
condition during a computer run
• SAP-2 has two flags; sign and zero flag

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 TMP, B and C Registers
• TMP(temporary) register is used instead of register B to
hold data being added or subtracted; which allows us
more freedom in using the B register
• Besides B and TMP SAP 2 has a register C which gives
us more flexibility in moving data during the computer
run

Output Ports

Two output ports numbered 3 and 4

Contents of the accumulator can be loaded into port 3,
which drives a hexadecimal display

The contents can also be seen through port 4

Architectural difference between SAP 1 and SAP 2

architecture

Major differences:

• Bidirectional registers
• Flags
• Large instruction set having jump, call & loop.
• Standard Input Output devices in SAP 2.
• Large no. of processor registers in SAP 2.
• High memory capacity(64K) in SAP 2.
• Address bus 16 bit in SAP 2.
• Separate MAR & MDR in SAP 2.

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 • Complex programming possible in SAP 2
• Introduction of ALU in SAP 2
• Serial as well as parallel I/O in SAP 2.

Flag
• Represent the status of the arithmetic and logical
operation.
• flip-flop concepts are used in flag to represent the
status of arithmetic and logical operation.
• Two types of flag are there sign flag and zero flag.
1)Sign flag: gets set when the accumulator
content is negative.
2)Zero flag : gets set when the accumulator
content is negative.

Instruction Set

Forewords:

The basic set of commands, or instructions, that a
microprocessor understands.

Also called the “Command Set”.

Deals with programming, including the native data
types, instructions, memory architecture and external
I/O Devices.

Step-by-step processes that are loaded into the
memory before the start of a computer run.

It is essential to understand the Instruction Set before
programming a computer.

Includes a specification of the set of opcodes (machine
language), and the native commands implemented by a
particular processor.

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 The SAP-2 Instruction Set:
MEMORY REFERENCE INSTRUCTIONS
1. LDA and STA :
LDA(Load to Accumulator):
• Loads the accumulator with the content of memory
location.
• More memory location can be accessed in SAP-2
than SAP-1 because the addresses are
from 0000H to FFFFH.
• E.g. LDA 2000H: loads the accumulator with
content of memory location 2000H

STA(Store the Accumulator):

• Stores the accumulator contents at different
memory locations.
• E.g. STA 7FFFH: To store the accumulator
contents at memory location 7FFFH.
i.e. If A=8AH, STA 7FFFH stores 8AH at address
7FFFH.

2. MVI (Move Immediate):

• Loads a designated register with the byte that
immediately follows the op code.
• E.g. MVI A,37H loads accumulator with 37H and
binary content of A becomes A=0011 0111

REGISTER INSTRUCTIONS
1. MOV (Move):
Moves data from one register to another register.
E.g. MOV A,B: Copies data from B to A
2. ADD and SUB:

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 Adds the content of assigned register to accumulator.
E.g. If A=04H and B=02H, ADD B gives result in
A=06H
Subtract the content of the assigned register from the
accumulator.
3. INR and DCR (Increment and Decrement):
Increases and decreases the register.
E.g. If B=56H and C=8AH then
INR B gives B=57H
DCR C gives C=89H

JUMP and CALL INSTRUCTIONS

1. JMP (Jump):
• Tells the computer to get the next instruction from
the designated memory location.
• E.g. JMP 3000H gives next instruction from
memory location 3000H.
• [Link] (Jump if Minus):
• Jump to designated address if and only if the sign
flag is set.
• E.g. Let JM 3000H is stored at 2005H. After this
instruction is fetched, PC=3000H is
executed if S=1 else (S=0) instruction is
fetched from 2006H.
3. JZ (Jump if Zero):
• Tells the computer to jump to designated address
only if the zero flag is set.
• E.g. JZ=3000H is stored at 2005H. Next
instruction is fetched from 3000H only if
Z=1 else from 2006.
4. JNZ (Jump if Not Zero):

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 We get a jump when the zero flag is clear and no jump
when it is set.
(Vice-versa of JZ)
5. CALL and RET:
CALL the Subroutine :
E.g. CALL 5000H will jump to the square root
subroutine and CALL 6000H produces a jump to the
logarithm subroutine.
RETURN:
Used at the end of every subroutine to tell the
computer to go back to the original program.

LOGIC INSTRUCTIONS:
1. CMA (Complement the Accumulator):
Inverts each bit in the accumulator, producing a 1’s
complement.
2. ANA (AND the Accumulator):
ANDs the content of accumulator with the content of
specified register.
E.g. A = 1100 1100, B = 1111 0001
ANA B results A = 1100 0000
3. ORA (OR the Accumulator):
ORs the content of accumulator with the content of
specified register.
E.g. A = 1111 1101, B = 1111 0001
ORA B results A = 1111 1101

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 4. ANI (AND Immediate):
ANDs the accumulator content with the byte that
immediately follows the op code.
E.g. A = 0101 1110 and ANI C7H gives A = 0100 0110
since C7= 1100 0111.
5. ORI (OR immediate):
The accumulator contents are ORed with the byte that
follows the op code.
6. XRI (XOR immediate):
A = 0001 1100
XRI D4H will XOR 0001 1100 and 1101 0100 to
produce A = 1100 1000 (High only if different
inputs else low if same inputs)

OTHER INSTRUCTIONS
1. NOP (No Operation):
Do nothing. (Used to waste time)
By repeating NOP a number of times, we can delay
the data processing, which is useful in timing
operations.
2. HLT (Halt):
Ends the data processing.
3. RAL (Rotate the accumulator Left):
Shift all bits to the left and move the MSB to the LSB
position.
E.g. A = 1011 0100
Then, RAL will produce A = 0110 1001
4. RAR (Rotate the accumulator Right):
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 The bits shift to the right, the LSB going to the MSB
position.
E.g. A = 1011 0100
Then, RAR results A = 0101 1010
5. IN (Input):
Tells a computer to transfer data from the
designated port to the accumulator.
E.g. IN 02H means to transfer the data in port 2 to
the accumulator.
6. OUT (Output):
When this instruction is executed, the accumulator
word is loaded into the designated output port.
E.g. OUT 03H will transfer the contents of the
accumulator to port 3.

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UNIT 3
INSTRUCTION CYCLE

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INTRODUCTION
Instruction cycle: The necessary steps that the cpu carries
out to fetch an instruction and necessary data from the
memory and to execute it constitute and instruction cycle it
is defined as the time required to complete the execution of
an instruction.
An instruction cycle consists of fetch cycle and execute
cycle. In fetch cycle CPU fetches upcode from the memory .
The necessary steps which are carried out to fetch an upcode
from memory constitute a fetch cycle. The necessary steps
which are carried out to get data if
any from the memory and to perform the specific operation
specified in an instruction constitute and execute cycle . The
total time required to execute an instruction given by IC =
Fc+ Ec
The 8085 consists of 1-6 machine cycles or operations.

Fetch cycle: The first byte of an instruction is it's upcode .

The program counter keeps the memory address of the next
instruction to be executed in the beginning of fetch cycle the
content of the program counter ,which is the address of the
memory location where upcode is
available , is send to the memory. The memory places the
upcode on the data bus so as to transfer it to CPU. The
entire process takes 3 clock cycle.

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Execute cycle/Operation: The upcode fetched from the
memory goes to IR from the IR it goes to the decoder which
decodes instruction. After the instruction is decoded
execution begins.
• If the operand is in general purpose register, execution
is performed immediately. I,e in one clock cycle.
• If an instruction is contains data or operand address,
then CPU has to perform some read operations to get
the desired data.
• In some instruction write operation is performed. In
write cycle data are sent from the CPU to the memory
of an o/p device.
• In some cases execute cycle may involve one or more
read or write cycle or both.

Figure1: Instruction Cycle

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Figure2: Fetch Cycle

Fetch execution overlap:

t1 t2 t3

I1 F E1

F2
E2
I2

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Machine cycle: It is defined as the time required to
complete one operation of accessing memory , i/p, o/p or
acknowledging and external request. This cycle may consists
of 3 to 6 T states.

T-states: It is defined as one sub division of the operation

performed in one clock period. These sub division are
internal states synchronized with system clock and each T
states precisely equal to one clock period.

Timing diagram: The necessary steps which are carried in

a machine cycle can represented graphically. Such graphical
representation is called timing diagram.

Opcode Fetch
A microprocessor either reads or writes to the memory or
I/O devices. The time taken to read or write for any
instruction must be known in terms of the µP clock. The 1st
step in communicating between the microprocessor and
memory is reading from the memory. This reading process is
called opcode fetch. The process of opcode fetch operation
requires minimum 4- clock cycles T1, T2, T3, and T4 and is
the 1st machine cycle (M1) of every instruction.
In order to differentiate between the data byte
pertaining to an opcode or an address, the machine cycle
takes help of the status signal IO/M, S1, and S0. The IO/M =

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0 indicates memory operation and S1 = S0 = 1 indicates
Opcode fetch operation. The opcode fetch machine cycle M1
consists of 4-states (T1, T2, T3, and T4). The 1st 3-states
are used for fetching (transferring) the byte from the
memory and the 4th-state is used to decode it. Thus,
thorough understanding about the communication between
memory and microprocessor can be achieved only after
knowing the processes involved in reading or writing into the
memory by the microprocessor and time taken w.r.t. its
clock period. This can be explained by examples. The
process of implementation of each instruction follows the
fetch and execute cycles. In other words, first the instruction
is fetched from memory and then executed. Figure 3 and 4
depict these 2-steps for implementation of the instruction
ADI 05H. Let us assume that the accumulator contains the
result of previous operation i.e., 03H and instruction is held
at memory locations 2030H and 2031H.

Figure3: Instruction fetch : reads 1st byte (Opcode)

in instruction register (IR)

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The fetch part of the instruction is the same for every
instruction. The control unit puts the contents of the
program counter (PC) 2030H on the address bus. The 1st
byte (opcode C6H in this example) is passed to the
instruction register. In the execute cycle of the instruction,
the control unit examines the opcode and as per
interpretation further memory read or write operations are
performed depending upon whether additional information/
data are required or not. In this case, the data 05H from the
memory is transferred through the data bus to the ALU. At
the same time the control unit sends the contents of the
accumulator (03H) to the ALU and performs the addition
operation. The result of the addition operation 08H is passed
to the accumulator overriding the previous contents 03H. On
the completion of one instruction, the program counter is
automatically incremented to point to the next memory
location to execute the subsequent instruction.

Figure4: Instruction execute : reads 2nd byte from memory

and adds to accumulator

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Note : The slope of the edges of the clock pulses has been
shown to be much exaggerated
to indicate the existence of rise and fall time.

TIMING DIAGRAM OF OPCODE FETCH

The process of opcode fetch operation requires minimum 4-

clock cycles T1, T2, T3, and T4
and is the 1st machine cycle (M1) of every instruction.
Example
Fetch a byte 41H stored at memory location 2105H.
For fetching a byte, the microprocessor must find out the
memory location where it is stored.
Then provide condition (control) for data flow from memory
to the microprocessor. The process of data flow and timing
diagram of fetch operation are shown in figures. The
µP fetches opcode of the instruction from the memory as per
the sequence below
• A low IO/M means microprocessor wants to communicate
with memory.
• The µP sends a high on status signal S1 and S0 indicating
fetch operation.
• The µP sends 16-bit address. AD bus has address in 1st
clock of the 1st machine cycle,
T1.
• AD7 to AD0 address is latched in the external latch when
ALE = 1.

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• AD bus now can carry data.
• In T2, the RD control signal becomes low to enable the
memory for read operation.
• The memory places opcode on the AD bus
• The data is placed in the data register (DR) and then it is
transferred to IR.

Figure5: Opcode fetch

• During T3 the RD signal becomes high and memory is

disabled.
• During T4 the opcode is sent for decoding and decoded in
T4.
• The execution is also completed in T4 if the instruction is
single byte.
• More machine cycles are essential for 2- or 3-byte
instructions. The 1st machine cycle M1 is meant for fetching
the opcode. The machine cycles M2 and M3 are required
either to read/ write data or address from the memory or
I/O devices.

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Example

Opcode fetch MOV B,C.

T1 : The 1st clock of 1st machine cycle (M1) makes ALE
high indicating address latch
enabled which loads low-order address 00H on AD7 _
AD0 and high-order address 10H simultaneously on A15
_ A8. The address 00H is latched in T1.

T2 : During T2 clock, the microprocessor issues RD
control signal to enable the memory and memory
places 41H from 1000H location on the data bus.

Figure6: Data flow from memory to microprocessor

• T3 : During T3, the 41H is placed in the instruction

register and RD = 1 (high) disables [Link] means the
memory is disabled in T3 clock cycle. The opcode cycle
is completed by end of T3 clock cycle.

T4 : The opcode is decoded in T4 clock and the action
as per 41H is taken accordingly. In other word, the
content of C-register is copied in B-register. Execution
time for opcode 41H is

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Clock frequency of 8085 = 3.125 MHz
Time (T) for one clock = 1/3.125 MHz = 325.5 ns = 0.32 µS

Figure7: Timing diagram for MVI B,05H

Figure8: Opcode fetch (MOV B,C)

The MVI B,05H instruction requires 2-machine cycles (M1

and M2). M1 requires 4-states and M2 requires 3-states,
total of 7-states as shown in Fig. 5.3 (d). Status signals
IO/M, S1 and S0 specifies the 1st machine cycle as the op-
code fetch.
In T1-state, the high order address {10H} is placed on
the bus A15 A8 and low-order address {00H} on the bus

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AD7 AD0 and ALE = 1. In T2 -state, the RD line goes
low, and the data 06H from memory location 1000H are
placed on the data bus. The fetch cycle becomes complete in
T3-state. The instruction is decoded in the T4-state. During
T4-state, the contents of the bus are unknown. With the
change in the status signal, IO/M = 0, S1 = 1 and S0 = 0,
the 2nd machine cycle is identified as the memory read. The
address is 1001H and the data byte[05H] is fetched via the
data bus. Both M1 and M2 perform memory read operation,
but the M1 is called op-code fetch i.e., the 1st machine cycle
of each instruction is identified as the opcode fetch cycle.
Execution time for MBI B,05H i.e., memory read machine
ycle and instruction cycle is
Mnemonics Machine Memory
MVI B,05H code Location
06H 1000H
05H 1001H

Read Cycle
The high order address (A15 ⇔ A8) and low order
address (AD7 ⇔ AD0) are asserted on
1st low going transition of the clock pulse. The timing
diagram for IO/M read are shown in Figures 9 & 10The A15 ⇔
A8 remains valid in T1, T2, and T3 i.e. duration of the bus
cycle, but AD7 ⇔ AD0 remains valid only in T1. Since it has to
remain valid for the whole bus cycle, it must be saved for its
use in the T2 and T3.

Figure9: Memory read timing diagram

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 ALE is asserted at the beginning of T1 of each bus cycle
and is negated towards the end of T1. ALE is active during T1
only and is used as the clock pulse to latch the address (AD7
⇔ AD0) during T1. The RD is asserted near the beginning of
T2. It ends at the end of T3. As soon as the RD becomes
active, it forces the memory or I/O port to assert data. RD
becomes inactive towards the end of T3, causing the port or
memory to terminate the data.

Figure10: I/O Read timing diagram

Write Cycle
Immediately after the termination of the low order
address, at the beginning of the T2, data
is asserted on the address/data bus by the processor. WR
control is activated near the start of T2 and becomes inactive
at the end of T3. The processor maintains valid data until
after WR is terminated. This ensures that the memory or
port has valid data while WR is active.
It is clear from Figure11 & 12that for READ bus cycle,
the data appears on the bus as a result of activating RD and
for the WR bus cycle, the time the valid data is on the bus
overlaps the time that the WR is active.

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Figure11: Memory write timing diagram.

Figure12: I/O write timing diagram

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STA
The STA instruction stands for storing the contents of the
accumulator to a memory location whose address is
immediately available after the instruction (STA). The 8085
have 16-address lines, it can address 216 = 64 K. Since the
STA instruction is meant to store the contents of the
accumulator to the memory location, it is a 3-byte
instruction. 1st byte is the opcode, the 2nd and 3rd bytes
are the address of the memory locations. The storing of the
STA instruction in the memory locations is as
Opcode 1st byte
Low address 2nd byte
High address 3rd byte
Three machine cycles are required to fetch this instruction
: opcode Fetch transfers the opcode from the memory to the
instruction register. The 2-byte address is then transferred,
1-byte at a time, from the memory to the temporary
register. This requires two Memory read machine cycles.
When the entire instruction is in the microprocessor, it is
executed. The execution process transfers data from the
microprocessor to the memory. The contents of the
accumulator are transferred to memory, whose address was
previously transferred to the microprocessor by the
preceding 2-Memory Read machine cycles. The address of
the memory location to be written is generated as
Mnem Instruction Machine T-
onic Byte Cycle states
Opcode
Opcode Fetch 4
LOW Memory
Address Read 3
HIGH Memory
STA Address Read 3
Memory
Write 3
13
The high order address byte in the temporary register is
transferred to the address latch and the low order address
byte is transferred to the address/data latch. This data
transfer is affected by

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 Figure13: STA timing diagram

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Memory Write machine cycle. Thus 3-byte STA instruction
has four machine cycles in its instruction cycle.
The timing and control section of the microprocessor
automatically generates the proper machine cycles required
for an instruction cycle from the information provided by the
opcode. The timing diagram of the instruction STA is shown
in Fig. 5.3 (i). The status of IO / M , S1 and S0 for 4-
machine cycles are obtained from Table 5.1. The condition of
IO / M , S1 and S0 would be 0, 1 and 1 respectively in MC1.
The status of ALE is high at the beginning of 1st state of
each machine cycle so that AD7 ⇔ AD0 work as the address
bus. RD remains high during 1st state of each machine
cycle, since during 1st state of each machine cycle AD7 ⇔
AD0 work as address bus. It remains high during 4th state of
the 1st machine cycle also as the 4th state is used to decode
the op code for generating the required control signals.

The opcode fetch of STA instruction has 4-states (clock

cycles). Three states have been used to read the opcode
from the main memory and the 4th to decode it and set up
the subsequent machine cycle.
The action of memory read or write cycles containing 3-
states i.e., T1, T2, and T3 are explained as:
T1 : During this period the address and control signals
for the memory access are set up.
T2 : The µP checks up the READY and HOLD control lines.
If READY = 0, indicating a slow memory device, the µP
enters in the wait state until READY = 1, indicating DMA
request, then only the µP floats the data transfer lines and
enters into wait until HOLD = 0.
T3 : In memory read cycles the µP transfers a byte from
the data bus to an internal register and in memory write
cycle the µP transfers a byte from an internal register to the

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data bus.
Thus STA instruction requires 4-machine cycles
containing 13-states (clock cycles). With a typical clock of 3
MHz (= 330 ns), the STA instruction requires 13*330 ns =
4.29 ms for its execution.

General Control signal:

Signals
IO/M S1 S0 RD WR

0 1 0 0 1 MEMR
0 0 1 1 0 MEMW
1 1 0 0 1 IOR
1 0 1 1 0 IOW
0 1 1 0 1 OPCEDE FETCH

MOV A, B = 1MC – opcode fetch – 4 T state

MVI A, 32H = 2MC – opcode fetch, 1 memory read – 7 T
states
STA 2050H- 4 MC- opcode fetch, 2 memory read , 1
memory write.
MOV A, M- 2 MC- 1 opcode fetch, 1 memroy write.
IN 84H – 3 MC – opcode fetch, 1 memory read, i/o read.
OUT 02H – 3 MC – opcode fetch, 1 memory read, 1 i/o
write.

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JMP 2050 – 3 MC – opcode fetch, 2 memory read. (when
condition satisfied)
-2 MC- opcode fetch, 1 memory read. (When condition
unsatisfied)
ADI 12H- 2MC- opcode feth, 1 memory read.

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Figure14: Timing Diagram of OUT 01H

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Figure15: Timing Diagram of IN 84H

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UNIT 4
INTEL 8085/8086/8088 ARCHITECTURE

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8085 MicroprocessorArchitecture
• 8-bit general purpose µp
• Capable of addressing 64 k of memory
• Has 40 pins
• Requires +5 v power supply
• Can operate with 3 MHz clock
• 8085 upward compatible

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 Figure: Architecture of Intel 8085 Microprocessor

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Intel 8085 Microprocessor consists of:

Control unit: control microprocessor operations.

ALU: performs data processing function.
Registers: provide storage internal to CPU.
Interrupts

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Internal data bus
The ALU
• In addition to the arithmetic & logic circuits, the
ALU includes the accumulator, which is part of every
arithmetic & logic operation.
• Also, the ALU includes a temporary register used
for holding data temporarily during the execution of
the operation. This temporary register is not
accessible by the programmer.

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• Auxillary Carry Flag
–Is set if there is a carry out of bit 3
• Parity Flag
–Is set if parity is even
–Is cleared if parity is odd

The Internal Architecture

• We have already discussed the general purpose
registers, the Accumulator, and the flags.
• The Program Counter (PC)

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 – This is a register that is used to control the sequencing
of the execution of instructions.
– This register always holds the address of the next
instruction.
– Since it holds an address, it must be 16 bits wide.
• The Stack pointer
–The stack pointer is also a 16-bit register that is used to
point into memory.
–The memory this register points to is a special area called
the stack.
–The stack is an area of memory used to hold data that will
be retreived soon.
–The stack is usually accessed in a Last In First Out (LIFO)
fashion.
Non Programmable Registers
• Instruction Register & Decoder
– Instruction is stored in IR after fetched by processor
– Decoder decodes instruction in IR
Internal Clock generator
– 3.125 MHz internally
– 6.25 MHz externally

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• The high order address is placed on the address bus and
hold for 3 clk periods,
• The low order address is lost after the first clk period, this
address needs to be hold however we need to use latch
• The address AD7 –AD0 is connected as inputs to the latch
74LS373.
• The ALE signal is connected to the enable (G) pin of the
latch and the OC –Output control –of the latch is grounded

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Serial I/O Controller
Controls in serial I/O communication
Two I/O Pins SID(Serial Input Data) and SOD(Serial
output Data)

Interrupt controller
 Managing the interrupt.

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 Can vector an interrupt request
 Solve levels of interrupt priorities.
 Have 6 interrupt pins
INTR (Input)
o INTERRUPT REQUEST; is used as a general purpose
interrupt.
o It is sampled only during the next to the last clock cycle of
the instruction. If it is active, the Program Counter (PC) will
be inhibited from incrementing and an INTA will be issued.
o During this cycle a RESTART or CALL instruction can be
inserted to jump to the interrupt service routine.
o The INTR is enabled and disabled by software.
o It is disabled by Reset and immediately after an interrupt
is accepted.
INTA (Output)
o INTERRUPT ACKNOWLEDGE; is used instead of (and has
the same timing as) RD during the Instruction cycle after an
INTR is accepted.
o It can be used to activate the 8259 Interrupt chip or some
other interrupt port.

RST 5.5
RST 6.5 - (Inputs)

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RST 7.5
RESTART INTERRUPTS; These three inputs have the same
timing as I NTR except they cause an internal RESTART to
be automatically inserted.
RST 7.5 Highest Priority
RST 6.5
RST 5.5 Lowest Priority
The priority of these interrupts is ordered as shown above.
These interrupts have a higher priority than the INTR.
TRAP (Input)
Trap interrupt is a non maskable restart interrupt. It is
recognized at the same time as
INTR. It is unaffected by any mask or Interrupt Enable. It
has the highest priority of
any interrupt.

CONTROL UNIT
• The Control Unit Provides the necessary timing and control
signals to all the operations in the Microcomputer
• It controls the flow of data between the Microprocessor
and Memory and Peripherals.
• The Control unit performs 2 basic tasks
o Sequencing

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o Execution
1. SEQUENCING
• The control unit causes the processor to step through a
series of micro-operations in the proper sequence, based on
the program being executed.
2. EXECUTION
• The control unit causes each micro operation to be
performed.

CONTROL SIGNALS

• For the control unit to perform its function it must have

inputs that allow it to determine the state of the system and
outputs that allow it to control the behavior of the system.
• Inputs : Clock , Instruction Register, Flags
• Outputs :
o Control signals to Memory
o Control signals to I/O
o Control Signals within the Processor.

Control and status Signal in 8085

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 This group of signal indicates two control signals RD and
WR.
 Three status signals (IO/M, S1 and S0) to identify the
nature of operation.
 One special signal (ALE) to indicate the beginning of the
operation.
 ALE (Address Latch Enable)
 This is a positive going pulse generated every time the
8085 begins an operation ( Machine cycle); it indicates that
the bits on AD7- AD0 are address bits. This signal is used
primarily to latch the low-order address from the
multiplexed bus and generate a separate set of eight
address lines A7-a0.
 RD-Read

RESET IN (Input)
Reset sets the Program Counter to zero and resets the
Interrupt Enable and HLDA flipflops. None of the other flags
or registers (except the instruction register) are
affected The CPU is held in the reset condition as long as
Reset is applied.
RESET OUT (Output)

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Indicates CPlJ is being reset. Can be used as a system
RESET. The signal is synchronized to the processor clock.

X1, X2 (Input)
Crystal or R/C network connections to set the internal clock
generator X1 can also be an external clock input instead of a
crystal. The input frequency is divided by 2 to
give the internal operating frequency.

CLK (Output)
Clock Output for use as a system clock when a crystal or R/
C network is used as an input to the CPU. The period of CLK
is twice the X1, X2 input period.

IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O
Tristated during Hold and Halt modes.

ADDRESSING MODES

• The different ways in which a processor can access data

are referred to as its addressing modes.
• In assembly language statements, the addressing mode
is indicated in the instruction itself.

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 • The various addressing modes are
1. Register Addressing Mode
2. Immediate Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Implied Addressing Mode

1. REGISTER ADDRESSING MODE

• It is the most common form of data addressing.
• Transfers a copy of a byte/word from source register to
destination register.
INSTRUCTION SOURCE DESTINATION
MOV A,B REGISTER B REGISTER A

• It is carried out with 8 bit registers A,B,C,D,E,H & L

• It is important to use registers of same size.
• Never mix an 8 bit register with a 16 bit register
i.e. MOV A,SP
EXAMPLES
MOV A,B : Copys B into A
MOV SP,H : Copys H pair into SP

2. IMMEDIATE ADDRESSING MODE

•The term immediate implies that the data immediately
follow the hexadecimal opcode in the memory.

Note that immediate data are constant data.

• It transfers the source immediate byte/word of data in
destination register or memory location.

INSTRUCTION SOURCE DESTINATION

MVI C,3AH DATA 3AH REGISTER C

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 EXAMPLES
MOV A,90 : Copys 90 into A
LXI H,1234H : Copys 1234H into H

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 It transfers byte/word between a register and a memory
location addressed.

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8086 CPU ARCHITECURE AND INSTRUCTION SET THE

8086 MICROPROCESSOR OVERVIEW

• The Intel 8086 is a 16 bit Microprocessor that is intended to be

used as the CPU in a Microcomputer.

• The term 16 bit means that it's ALU, its internal registers,
and most of its instructions are designed to work with 16 bit
binary words.

• The 8086 has a 16 bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.

• The 8086 has a 20 bit address bus, so it can address 220 or

1,048576 memory locations.

• Sixteen bit words will be stored in two consecutive memory

locations.

• If the first byte of a word is at an even address, the 8086 can

read the entire word in one operation.

• If the first byte of the word is at an odd address, the 8086 will
read the first byte with one bus operation and the second byte
with another bus operation

• The main point here is that if the first byte of a 16 bit word is at
an even address, the 8086 can read the entire word in one
operation

8086 AND 8088

• The Intel 8088 has the same arithmetic logic unit, the same
registers and the same instruction set as the 8086.

• The 8088 also has a 20 bit address bus, so it can address any
one of 1,048,576 bytes in memory.

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 • The 8088 has an 8 bit data bus, so it can only read data from
or write data to memory and ports 8 bits at a time.

• The 8086 can read or write either 8 or 16 bits at a time.

• To read a 16 bit word from two successive memory

locations, the 8088 will always have to do two read operations.

• The Intel 80186 is an improved version of 8086,and 80188

is an improved version of 8088

• In addition to 16 bit CPU, the 80186 and 80188 each

have programmer peripheral devices integrated in the same
package.

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 8086 INTERNAL ARCHITECTURE

INTERNAL ARCHITECTURE OF

8086

Figure: Internal Architecture of 8086

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 • The 8086 CPU is divided into two independent functional
parts : BIU (Bus Interface Unit) and EU (Execution Unit)

• Dividing the work between these units speeds up the processing.

• The BIU send out address, fetches instructions from memory,

reads data from ports and memory, and writes data to ports
and memory.

• In other words BIU handles all transfers of data and addresses

on the buses for the execution unit.

• The EU of the 8086 tells the BIU where to fetch the

instructions and data from, decodes instructions and executes
instructions.

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 A. THE EXECUTION UNIT
• The EU contains control circuitry which directs internal operations.

• A decoder in EU translates instructions fetched from memory into

a series of actions which the EU carries out.

• The EU has a 16 bit ALU which can add subtract, ND, OR, increment,
decrement, complement or shift binary numbers.

1. GENERAL PURPOSE REGISTERS

• The EU has eight general purpose registers, labeled AH, AL, BH, BL,
CH, CL, DH and DL.

• These registers can be used individually for temporary storage of 8 bit

data.

• The AL register is also called accumulator

• It has some features that the other general purpose registers do not
have.

• Certain pairs of these general purpose registers can be used together

to store 16 bit words.

• The acceptable register pairs are AH and AL,BH and BL,CH and CL,DH
and DL

• The AH-AL pair is referred to as the AX register, the BH-BL pair is

referred to as the BX register, the CH-CL pair is referred to as the CX
register, and the DH-DL pair is referred to as the DX register.

AX = Accumulator Register

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 BX = Base Register

CX = Count Register

DX = Data Register

2. FLAG REGISTER
• A Flag is a flip-flop which indicates some condition produced by the
execution of an instruction or controls certain operations of the EU.

• A 16 bit flag register in the EU contains 9 active flags.

• Figure below show shows the location of the nine flags in the flag
register.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF

Figure: 8086 Flag Register Format

U = UNDEFINED

CONDITIONAL FLAGS

CF = CARRY FLAG [Set by Carry out of MSB]

PF = PARITY FLAG [Set if Result has even
parity] AF= AUXILIARY CARRY FLAG FOR BCD
ZF = ZERO FLAG [Set if Result is 0]
SF = SIGN FLAG [MSB of Result]

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 CONTROL FLAG

TF = SINGLE STEP TRAP

FLAG IF = INTERRUPT
ENABLE FLAG DF = STRING
DIRECTION FLAG
OF = OVERFLOW FLAG

• The six conditional flags in this group are the CF,PF,AF,ZF,SF and OF

• The three remaining flags in the Flag Register are used to

control certain operations of the processor.

• The six conditional flags are set or reset by the EU on the basis of
the result of some arithmetic or logic operation.

• The Control Flags are deliberately set or reset with specific instructions
you put in your program.

• The three control flags are the TF,IF and DF.

• Trap Flag is used for single stepping through a program.

• The Interrupt Flag is used to allow or prohibit the interruption of a

program.

• The Direction Flag is used with string instructions.

3. POINTER REGISTERS
• The 16 bit Pointer Registers are IP,SP and BP respectively

• SP and BP are located in EU whereas IP is located in BIU

3.1 STACK POINTER (SP)

• The 16 bit SP Register provides an offset value, which when
associated with the SS register (SS:SP)

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 3.2 BASE POINTER (BP)
• The 16 bit BP facilitates referencing parameters, which are data and
addresses that a program passes via the stack.

• The processor combines the addresses in SS with the offset in BP.

• BP can also be combined with DI and SI as a base register for special

addressing.

4. INDEX REGISTERS
• The 16 bit Index Registers are SI and DI

4.1 SOURCE INDEX (SI) REGISTER

• The 16 bit Source Index Register is required for some string handling
operations

• SI is associated with the DS Register.

4.2 DESTINATION INDEX (DI) REGISTER

• The 16 bit Destination Index Register is also required for some string
operations.
• In this context, DI is associated with the ES register.

B. THE BUS INTERFACE UNIT

1. SEGMENT REGISTERS

1.1 CS REGISTER
• It contains the starting address of a program's code segment.

• This segment address plus an offset value in the IP register indicates

the address of an instruction to be fetched for execution

• For normal programming purpose, you need not directly reference this
register.

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 1.2 DS REGISTER
• It contains the starting address of a program's data segment

• Instruction uses this address to locate data.

• This address plus an offset value in an instruction causes a reference

to a specific byte location in the data segment.

1.3 SS REGISTER
• Permits the implementation of a stack in memory
• It stores the starting address of a program's stack segment the SS
register.
• This segment address plus an offset value in the Stack Pointer
(SP) register indicates the current word in the stack being
addressed.

1.4 ES REGISTER
• It is used by some string operations to handle memory addressing.

• ES Register is associated with the DI Register.

2. INSTRUCTION POINTER (IP)

• The 16 bit IP Register contains the offset address of the next
instruction that is to execute.
• IP is associated with CS register as (CS:IP)

• For each instruction that executes, the processor changes the offset
value in IP so that IP in effect directs each step of execution.

3. THE QUEUE

• While the EU is decoding an instruction or executing an instruction

which does not require use of the buses, the BIU fetches up to six
instructions bytes for the following instructions.

• The BIU Stores prefetched bytes in First in First out register set called a
queue.

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 • When the EU is ready for its next instruction, it simply reads the
instruction bytes for the instruction from the queue in the BIU.

• This is much faster than sending out an address to the system

memory and waiting for memory to send back the next instruction
bytes or bytes.

• Fetching the next instruction while the current instruction

executes is called pipeling

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8086 MEMORY ORGANIZATION

1. INTRODUCTION
• The Intel 8086 is a 16 bit Microprocessor that is intended to be used
as the CPU in a Microcomputer.

• The 8086 has a 20 bit address bus so it can address any one of 220 or
1,048,576 memory locations.

• Each of the 1,048,576 memory address of the 8086 represents a

byte-wide location.

• 16 bit word will be stored in two consecutive memory locations.

• If the first byte of a word is at an even address, the 8086 can read
the entire word in one operation.

• If the first byte of a word is at an odd address, the 8086 will read the
first byte with one bus cycle and the second byte with another bus
cycle.

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 2. ACCESSING DATA IN MEMORY
• An important point here is that an 8086 always stores the low byte
of word in lower address and stores high byte of word in higher
address.

• Low Byte – Low Address : High Byte – High Address

• MOV AX,[437AH]

Assume DS=2000H

• To Compute the physical address Add 20000 H and

437AH 20000 H + 437A H = 2437AH

• 2437A H is the physical address.

AX

AH AL
2437BH

52
2437AH
02

20000 H [Start of Data Segment i.e. DS=2000H]

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 3. SEGMENTED MEMORY

• The 8086 BIU sends out 20 bit address so it can address any of 220 or
1,048,576 bytes in memory.

• However at any given time the 8086 works with only four 65536 bytes
(64 Kbyte) segment within this 1,048,576 byte (1 Mbyte) Range

• Four segments are : Code Segment, Stack Segment, Data Segment

and Extra Segment

• Four segment registers in BIU are used to hold the upper 16 bits of
the starting address of 4 memory segments that the 8086 is working
with at a particular time.

• The 4 segment registers are code segment register (CS), stack

segment register (SS), data segment register (DS) and the extra
segment register (ES).

• For small programs which do not need all 64 Kbytes in each segment can
overlap.

• For example, the code segment holds the upper 16 bits of the starting
address for the segment from which the BIU is currently fetching
instruction code bytes.

• The BIU always inserts zero for the lowest 4 bits of the 20 bit starting
address.

• If the code segment register contains 348A H then the code segment

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 will start at address 348A0 H

• A 64 Kbytes segment can be located anywhere within the 1 Mbyte

address space, but the segment will always start at an address with
zeros in the lowest 4 bits

ADVANTAGES OF SEGMENTATION [SEGMENT: OFFSET SCHEME]

Intel designed the 8086 family devices to access memory using the
segment: offset approach rather than accessing memory directly with 20
bit. The advantages are listed below.
• The segment: offset scheme requires only a 16 bit number to
represent the base address for a segment and only a 16 bit offset
to access any location in a segment. This means that 8086 has to
manipulate and store only 16 bit quantities instead of 20 bit
quantities.

• This makes easier interface with 8 and 16 bit wide memory boards
and with 16 bit registers in the 8086.

• It allows programs to be relocated in memory system. A relocatable

program is one that can be placed in any area of memory and
executed without change.

• It allows programs written to function in the real mode to operate

in protected mode.

• Segmentation also makes easy to keep user's program and data

separate from one another and segmentation makes it easy to switch
from one user's program to another user's program.

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 DISADVANTAGE OF SEGMENT: OFFSET APPROACH

• The segment: offset scheme introduces complexity in hardware

and software design.

DIFFERENT SEGMENT OFFSET COMBINATION

SEGMENT OFFSET SPECIAL PURPOSE

S [CODE
IP [INSTRUCTION INSTRUCTION
POINTER]
SEGMENT] SS
SP [STACK ADDRESS STACK
POINTER] BP
[BASE POINTER]
[STACK SEGMENT]
BX [BASE REGISTER] ADDRESS
DI [DESTINATION
INDEX] SI [SOURCE
DS [DATA INDEX]
8 BIT NUMBER DATA ADDRESS
16 BIT NUMBER

SEGMENT]
DI [DESTINATION INDEX]

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 ADDRESSING MODES

• The different ways in which a processor can access data are

referred to as its addressing modes.

• In assembly language statements, the addressing mode is

indicated in the instruction itself.

• The various addressing modes are

1. Register Addressing Mode

2. Immediate Addressing Mode
3. Direct Addressing Mode
4. Register Indirect Addressing Mode
5. Base plus Index Addressing Mode
6. Register Relative Addressing Mode
7. Base Relative Plus Index Addressing Mode

1. REGISTER ADDRESSING MODE

• It is the most common form of data addressing.

• Transfers a copy of a byte/word from source register to destination

register.

INSTRUCTION SOURCE DESTINATION

MOV AX,BX REGISTER BX REGISTER AX

• It is carried out with 8 bit registers AH,AL,BH,BL,CH,CL,DH & DL or

with 16 bit registers AX,BX,CX,DX,SP,BP,SI and DI.

• It is important to use registers of same size.

• Never mix an 8 bit register with a 16 bit register i.e. MOV AX,BL

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 EXAMPLES
MOV AL,BL : Copys BL into AL
MOV ES,DS : Copys DS into ES
MOV AX,CX : Copys CX into AX

2. IMMEDIATE ADDRESSING MODE

• The term immediate implies that the data immediately follow the
hexadecimal opcode in the memory.

• Note that immediate data are constant data.

• It transfers the source immediate byte/word of data in destination

register or memory location.

INSTRUCTION SOURCE DESTINATION

MOV CH,3AH DATA 3AH REGISTER AX

EXAMPLES
MOV AL,90 : Copys 90 into AL
MOV AX,1234H : Copys 1234H into
AX
MOV CL,10000001B : Copys 100000001 binary value into CL

3. DIRECT ADDRESSING MODE

• In this scheme, the address of the data is defined in the instruction

itself.

• When a memory location is to be referenced, its offset address must be

specified

INSTRUCTION SOURCE DESTINATION

MOV AL,[1234H] ASSUME REGISTER AL
DS=1000H
10000 H + 1234
H
11234H
MEMORY LOCATION

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 EXAMPLES
MOV AL,[1234H] : Copys the byte content of data segment memory
location 11234H into AL.

MOV AL, NUMBER : Copys the byte content of data segment memory
location NUMBER into AL.

4. REGISTER INDIRECT ADDRESSING MODE

• Register Indirect Addressing allows data to be addressed at any

memory location through an offset address held in any of the
following registers: BP, BX, DI and SI.

• The Index and Base registers are used to specify the address of data.

• It transfers byte/word between a register and a memory location

addressed by an index or base registers.

• The symbol [ ] denote indirect addressing.

• The data segment is used by default with register indirect addressing

or any other addressing mode that uses BX,DI or SI to address
memory. If BP register addresses memory, the stack segment is used
by default.

INSTRUCTION SOURCE DESTINATION

MOV CL,[BX] ASSUME REGISTER CL
DS=1000H
ASSUME
BX=0300H
10000 H + 0300 H
10300H
MEMORY LOCATION
EXAMPLES
MOV CX,[BX] : Copys the word contents of the data segment
memory location addressed by BX into CX.

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 MOV [DI],BH : Copys BH into the data segment memory location
addressed by DI.

MOV [DI],[BX] : Memory to Memory moves are not allowed

except with string instructions.

5. BASE PLUS INDEX ADDRESSING MODE

• Base plus index addressing is similar to indirect addressing because

it indirectly addresses memory data

• This type of addressing uses one base register (BP or BX) and one
Index Register (DI or SI) to indirectly address memory.

INSTRUCTION SOURCE DESTINATION

MOV [BX+SI],CL REGISTER CL ASSUME DS=1000H
ASSUME BX=0300H
ASSUME SI =0200H
10000H + 0300H +
0200H
10500H
MEMORY LOCATION
10500H
EXAMPLES
MOV CX,[BX+DI] : Copys the word contents of the data segment
memory location addressed by BX plus DI into
CX.

MOV CH,[BP+SI] : Copys the byte contents of the stack segment

memory location addressed by BP plus SI into
CH.

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 6. REGISTER RELATIVE ADDRESSING MODE

• In this case, the data in a segment of memory are addressed by

adding the displacement to the content of base or an index register
(BP,BX ,DI or SI).

• Transfers a byte/word between a register and the memory location

addressed by an index or base register plus a displacement.

INSTRUCTION SOURCE DESTINATION

MOV [BX+4],CL REGISTER CL ASSUME
DS=1000H
ASSUME
BX=0300H
10000H + 0300H + 4H
10304H
MEMORY LOCATION

EXAMPLES
MOV ARRAY[SI],BL : Copys BL into the data segment memory location
addressed by ARRAY plus SI.

MOV LIST[SI+2],CL : Copys CL into the data segment memory location

addressed by sum of LIST, SI and 2.

7. BASE RELATIVE PLUS INDEX ADDRESSING MODE

• The base relative plus index addressing mode is similar to the base
plus index addressing mode but it adds a displacement to form a
memory address.

• Transfers a byte or word between a register and the memory location

addressed by a base and an index register plus a displacement.

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 INSTRUCTION SOURCE DESTINATION
MOV [BX+SI+05],CL REGISTER CL ASSUME
DS=1000H
ASSUME
BX=0300H
ASSUME SI =0200H
10000H + 0300H + 0200H
+05H
10505H

EXAMPLES
MOV LIST[BP+DI],CL : Copys CL into the stack segment memory
location
addressed by the sum of LIST, BP and DI

MOV DH,[BX+DI+20H] : Copys the byte contents of the data segment

memory location addressed by the sum of
BX,DI and 20H into DH

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 INSTRUCTION SETS

1. DATA TRANSFER INSTRUCTIONS

1.1 GENERAL PURPOSE BYTE OR WORD TRANSFER INSTRUCTIONS

INSTRUCTIONS COMMENTS
MOV Copy byte or word from specified
source to specified destination.
MOV
Destination,Source
MOV CX,04H
PUSH Copy specified word to top of stack.
PUSH
Source
PUSH BX
POP Copy word from top to stack to
specified location.
POP
Destination
POP AX
XCHG Exchange word or byte.
XCHG
Destination,Source
XCHG AX,BX
XLAT Translate a byte in AL using a
table in memory.
It first adds AL + BX to form memory
address. It then copys the content into
AL

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 1.2 SIMPLE INPUT AND OUTPUT PORT TRANSFER INSTRUCTIONS

INSTRUCTIONS COMMENTS
IN Copy a byte or word from specified
port to accumulator.
IN
AX,Port_Addr
IN AX,34H
OUT Copy a byte or word from
accumulator to specified port.
OUT
Port_Addr,AX
OUT 2CH,AX

1.3 SPECIAL ADDRESS TRANSFER INSTRUCTIONS

INSTRUCTIONS COMMENTS
LEA Load effective address of operand
into specified register.
LEA Register,Source
LEA BX,PRICE

LDS Load DS register and other specified

register from memory.
LDS Register,Source
LDS BX,[4326H]

LES Load ES register and other specified

register from memory.

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 1.4 FLAG TRANSFER INSTRUCTIONS

INSTRUCTIONS COMMENTS
LAHF Copy to AH with the low byte of
the flag register.
SAHF Stores AH register to low byte of flag
register.
PUSHF Copy flag register to top of stack.
POPF Copy word at top of stack to flag
register.

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 2. ARITHMETIC INSTRUCTIONS

2.1 ADDITION INSTRUCTIONS

INSTRUCTIONS COMMENTS
ADD Add specified byte to byte or word to
word.
ADD
Destination,Source
ADD AL,74H
ADC Add byte + byte + carry
flag Add word+word +
ADC carry flag
Destination,Source
ADC CL,BL

INC Increment specified byte or word by 1.

INC Register
INC CX
AAA ASCII adjust after addition.
DAA Decimal adjust after addition.

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 2.2 SUBTRACTION INSTRUCTIONS

INSTRUCTIONS COMMENTS
SUB Subtract byte from byte or word from
word.
SUB
Destination,Source
SUB CX,BX
SBB Subtract byte and carry flag from byte.
Subtract word and carry flag from
SBB word.
Destination,Source
SBB CH,AL
DEC Decrement specified byte or word by 1.
DEC Register
DEC CX
NEG Form 2's complement.
NEG
Register
NEG AL
CMP Compare two specified bytes or words.
CMP
Destination,Source
CMP CX,BX
CF ZF SF
CX = BX 0 1 0
CX > BX 0 0 0
CX < BX 1 0 1

AAS ASCII adjust after subtraction.

DAS Decimal adjust after subtraction.

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 2.3 MULTIPLICATION INSTRUCTIONS

INSTRUCTIONS COMMENTS
MUL Multiply unsigned byte by byte or
unsigned word by word.
When a byte is multiplied by the
content of AL, the result is kept into AX.
When a word is multiplied by the
content of AX, MS Byte in DX and LS
Byte in AX.
MUL
Source
MUL CX
IMUL Multiply signed byte by byte or signed
word by word.
IMUL Source
IMUL CX
AAM ASCII adjust after multiplication.
It converts packed BCD to unpacked
BCD.

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 2.4 DIVISION INSTRUCTIONS

INSTRUCTIONS COMMENTS
DIV Divide unsigned word by
byte
Divide unsigned word double word
by byte.
When a word is divided by byte,
the word must be in AX register and
the divisor can be in a register or a
memory location.

After division AL
(quotient)
AH (remainder)
When a double word is divided by
DIV word, the double word must be in
Source DX:AX pair and the divisor can be in a
DIV BL register or a memory location.
DIV CX
After division AX
(quotient)
DX (remainder)

AAD ASCII adjust before division

BCD to binary convert before division.
CBW Fill upper byte of word with copies of
sign bit of lower byte.
CWD Fill upper word of double word with
sign bit of lower word.

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 3. BIT MANIPULATION INSTRUCTIONS

3.1 LOGICAL INSTRUCTIONS

INSTRUCTIONS COMMENTS
NOT Invert each bit of a byte or word.
NOT
Destination
NOT BX
AND AND each bit in a byte/word
with the corresponding bit in another
AND byte or word.
Destination,Source
AND BH,CL
OR OR each bit in a byte or word
with the corresponding bit in another
OR byte or word.
Destination,Source
OR AH,CL
XOR XOR each bit in a byte or word
with the corresponding bit in another
XOR byte or word.
Destination,Source
XOR CL,BH
TEST AND operands to update flags, but
don't change the operands.
TEST
Destination,Source
TEST AL,BH

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 3.2 SHIFT INSTRUCTIONS

INSTRUCTIONS COMMENTS
SHL/SAL Shift Bits of Word or Byte Left, Put
Zero(s) in LSB.
SAL Destination,Count
SHL Destination,Count
CF←MSB←LSB←0

SHR Shift Bits of Word or Byte Right, Put

Zero(s) in MSB.
SHR Destination,Count
0 → MSB→ LSB → CF

SAR Shift Bits of Word or Byte Right,

Copy Old MSB into New MSB.
SAR Destination,Count
MSB→ MSB → LSB→ CF

3.3 ROTATE INSTRUCTIONS

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 INSTRUCTIONS COMMENTS
ROL Rotate Bits of Byte or Word Left,MSB to
LS and to CF.
ROR Rotate Bits of Byte or Word Right,LSB
to MSB and to CF.
RCL Rotate Bits of Byte or Word Left,MSB to
CF and CF to LSB.
RCR Rotate Bits of Byte or Word Right,LSB
TO CF and CF TO MSB.

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 4. PROGRAM EXECUTION TRANSFER INSTRUCTIONS

4.1 UNCONDITIONAL TRANSFER INSTRUCTION

INSTRUCTIONS COMMENTS
CALL Call a Subprogram/Procedure.
RET Return From Procedure to Calling
Program.
JMP Goto Specified Address to Get Next
Instruction (Unconditional Jump to
Specified Destination).

4.2 CONDITIONAL TRANSFER INSTRUCTION

INSTRUCTIONS COMMENTS
JA/JNBE Jump if Above/Jump if Not Below or
Equal.
JAE/JNB Jump if Above or Equal/Jump if Not
Below.
JB/JNAE Jump if Below/Jump if Not Above or
Equal.
JBE/JNA Jump if Below or Equal/Jump if Not
Above.
JC Jump if Carry Flag CF=1.
JE/JZ Jump if Equal/Jump if Zero Flag (ZF=1).
JG/JNLE Jump if Greater/Jump if Not Less than or
Equal.
JGE/JNL Jump if Greater than or Equal/Jump if
Not Less than.
JL/JNGE Jump if Less than/Jump if Not Greater
than or Equal.
JLE/JNG Jump if Less than or Equal/Jump if Not
Greater than.
JNC Jump if No Carry i.e. CF=0

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 JNE/JNZ Jump if Not Equal/Jump if Not Zero(ZF=0)
JNO Jump if No Overflow.
JNP/JPO Jump if Not Parity/Jump if Parity Odd.
JNS Jump if Not Sign(SF=0)
JP/JPE Jump if Parity/Jump if Parity Even (PF=1)
JS Jump if Sign (SF=1)

4.3 ITERATION CONTROL INSTRUCTIONS

INSTRUCTIONS COMMENTS
LOOP Loop Through a Sequence of
Instructions Until CX=0.
LOOPE/LOOPZ Loop Through a Sequence of
Instructions While ZF=1 and CX!=0.
LOOPNE/LOOPNZ Loop Through a Sequence of
Instruction While ZF=0 & CX!=0.
JCXZ Jump to Specified Address if CX=0.

4.4 INTERRUPT INSTRUCTIONS

INSTRUCTIONS COMMENTS
INT
INT0 Interrupt Program Execution if OF=1
IRET Return From Interrupt Service Procedure
to Main Program.

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 5. PROCESSOR CONTROL INSTRUCTIONS

5.1 FLAG SET/CLEAR INSTRUCTION

INSTRUCTIONS COMMENTS
STC Set Carry Flag CF to 1.
CLC Clear Carry Flag to 0.
CMC Complement the State of CF.
STD Set Direction Flag to 1.
CLD Clear Direction Flag to 0.
STI Set Interrupt Flag
to 1. (Enable INTR
Input).
CLI Clear Interrupt Enable to 0

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 5.2 NO OPERATION INSTRUCTION

INSTRUCTIONS COMMENTS
NOP No Action Except Fetch and Decode.

5.3 EXTERNAL HARDWARE SYNCHRONIZATION INST.

INSTRUCTIONS COMMENTS
HLT Halt (Do Nothing) Until Interrupt or Reset.
WAIT Wait Until Signal On the TEST Pin is Low.
ESC Escape to External Coprocessor Such as
8087 or 8089.
LOCK Prevents Another Processor From Taking
the Bus While the Adjacent Instruction
Executes.

6. STRING INSTRUCTIONS

INSTRUCTIONS COMMENTS
REP Repeat Instruction Until CX=0.
REPE/REPZ Repeat if Equal/Repeat if Zero
REPNE/REPNZ Repeat if Not Equal/Repeat if Not Zero.
MOVS/MOVSB/MOVSW Move Byte or Word From One String to
Another.
COMPS/COMPSB/COMPSW Compare Two String Bytes or Two String
Words.
SCAS/SCASB/SCASW Compares a Byte in AL or Word in AX
With a Byte or Word Pointed By DI in
ES.

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UNIT 5
ASSEMBLY LANGUAGE PROGRAMMING

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 ASSEMBLY LANGUAGE PROGRAMMING

INTRODUCTION

• Assembly Language uses two, three or 4 letter mnemonics to represent

each instruction type.

• Low level Assembly Language is designed for a specific family of

Processors : the symbolic instruction directly relate to Machine Language
instructions one for one and are assembled into machine language

• To make programming easier, many programmers write programs in

assembly language

• They then translate Assembly Language program to machine language so

that it can be loaded into memory and run.

ADVANTAGES OF ASSEMBLY LANGUAGE

• A Program written in Assembly Language requires considerably less

Memory and execution time than that of High Level Language.

• Assembly Language gives a programmer the ability to perform highly

technical tasks.

• Resident Programs (that resides in memory while other programs

execute) and Interrupt Service Routine (that handles I/P and O/P) are
almost always developed in Assembly Language.
• Provides more control over handling particular H/W requirements.

• Generates smaller and compact executable modules.

• Results in faster execution.

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 TYPICAL FORMAT OF AN ASSEMBLY LANGUAGE INSTRUCTION

LABEL OPCODE FIELD OPERAND COMMENTS

NEXT: ADD FIELD
AL,07H ; Add correction factor

• Assembly language statements are usually written in a standard form

that has 4 fields.

• A label is a symbol used to represent an address. They are followed by

colon

• Labels are only inserted when they are needed so it is an optional field.

• The opcode field of the instruction contains the mnemonics for the
instruction to be performed

• The instruction mnemonics are sometimes called as operation codes.

• The operand field of the statement contains the data, the memory
address, the port address or the name of the register on which the
instruction is to be performed.

• The final field in an assembly language statement is the comment field

which starts with semicolon. It forms a well documented program.

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8085 PROGRAMMING EXAMPLES
[Link] a program to perform the following :
a). Load the no: 1BH in D
b) Load the no. B5H in B
C). Increment the content of B by 1.
d). Decrement the content of D by 1.
e). Subtract the content of D from the content of B.
f). Display the result at OUT port 1.
MVI D,1BH
MVI B,B5H
INR B
DCR D
MOV A, B
SUB D
OUT PORT 1
HLT
2 Wap to load the data byte in the register C. Mask the high- order bits (D7-D4)
and display the low order bits (D3-D0) at outport. Exclusive-OR the result with
57H and display at OUT PORT2.
Solution: MVI C, A8H
MOV A, C
ANI OFH
OUT PORT1
XRI 57H
OUT PORT 2
HLT

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3. Wap to load the byte 8EH in register D and F7H in register E. Mask the higher
order bits (D7 – D4) from both the data bytes , EX-OR the low order bit (D3-D0)
and display the answer.
Solution:
MVI D, 8EH
MOI A, D
ANI
MVI D, 8EH
MVI E, F7H
MOV A, D
ANI OFH
MOV D, A
MOV A, E
ANI OFH
XRA D
OUT PORT 1
HLT

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4. Write a program to load two unsigned nos in register B and C respectively .
Subtract c from B. If the result in 2's complement convert the result in absolute
magnitude and display it port 1. Otherwise display the result.

Solution:
MVI B, byte 1
MVI C, byte 2
MOV A, B
SUB C
JNC label 1
CMA
ADI 01H
Label 1 OUT PORT 1
HLT

5. Write an ALP to do the following:

a) Load A with byte 1.
b) Load B with byte 2.
c) Compare the equality of the contents of A and B
d) If two nos . are equal , display 01 otherwise display 00H at port 1.

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Solution:
MVI A, byte 1
MVI B, byte 2
SUB B
JNZ loop
MVI A, 01H
OUT PORT 1
HLT
Loop MVI A, 00H
OUT PORT
HLT

[Link] following block of data is stored in memory location from CO55 to C05A H.
Transfer the entire block of data to the locations C080 to C085 H in reverse order.
Data: 22, A5, B2, 99, 7F, 37
Solution:
LXI H, C055 H
LXI D, C085 H
MOV B, 06H

Next MVI A, M
STAX D
INX H
DCX D
DCR B
JNZ next
HLT.

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7. Write a program to find larger of two nos. 1st no in C001 and 2nd no in C002
and result in C003 H.
Solution:
LXI H, C001 H
MOV A, M
INX H
CMP M
JNC loop
MOV A, M
Loop STA C003 H
HLT

8. Write an ALP to find the smallest no in a data array. Data from location C000H
to C005 H.
Solution:
LXI H, C000H
MVI C, 06H
MOV A, M
DCR C
Loop INX H
CMP M
JC loop1
MOV A, M
Loop1 DCR C
JNZ loop
STA C0C0 H
HLT.

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9. Write an ALP to multiply two nos: eg 05 H × 08 H
Solution:
MVI A, 00H
MVI B, 08H
MVI C, 05H
Loop ADD B
DCR C
JNZ loop
STA C000H
HLT

[Link] an ALP for the following addition 12+22+32+42+52+62+72+82+92

Solution:
MVI A, 00H
MVI B, 09H
Loop 1 MOV C, B
Loop 2 ADD B
DCR C
JNZ loop2
DCR B
JNZ loop 1
OUT PORT 1
HLT

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[Link] an ALP to count the no of 1 in the given string
'10100110' and display the result at COCOH
Solution:
MVI A, A6 H
MVI B, 00H
MVI C, 08H
Loop1 RAL
JNC loop2
INR B
Loop2 DCR C
JNZ loop 1
MOV A, B
STA COCOH
HLT

[Link] following datas are stored in memory location starting from C0B0 to C0B9
H . Take a test no. 48. Find out how many times the no 48 is repeated. Display the
result at C0C0H .
DADA: 12, 23, 34, 45, 48, 56, 48, 67, 48, 89.
Solution:
LXI H, C0B0 H
MVI B, 00H
MVI C, 0A H
Loop 1 MOV A, M
CPI 48 H

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JNZ loop2
INR B
Loop 2 INX H
DCR C
JNZ loop1
MOV A,B
STA COCO H
HLT

13.8 bit multiplication , product is 16 bit . The multiplicand is loaded in the two
consecutive memory locations 2501 and 2502 H . The multiplier is stored in 2053
H. Store the
product in 2504 and 2505 H.
Solution:
LHLD 2501 H
XCHG
LDA 2503 H
LXI H, 0000
MVI C, 08
Loop1 DAD H
RAL
JNC loop2
DAD D
Loop 2 DCR C
JNZ loop1

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SHLD 2504 H
HLT

[Link] an ALP to divide two nos. The dividend is in C001 and divisor is in
C002. Store the quotient in C0C0 H and remainder in C0C1.
Solution:
LXI H, C001 H
MOV A,M
INX H
MOV B,M
MVI C, 00H
Loop1 CMP B
JC Loop2
INR C
SUB B
JNZ Loop 1
Loop2 STA COC1 H
MOV A, C
STA COCO H
HLT

[Link] arrange 54 , EB, 85, A8 & 99 in descending order. These numbers are stored
in the memory location 2501 to 2505 H. The count = 05 is restored in 2500 H.
Results are to be stored in 2601 to 2605 H.
Solution:

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LXI D, 2601 H
LXI H, 2500 H
MOV B, M
Start CALL Subroutine 1
STAX D
CALL Subroutine 2
INX D
DCR B
JNZ start
HLT
Subroutine 1:
LXI H, 2500 H
SUB A

Loop1: INX H
CMP M
JNC loop 2
MOV A, M
Loop2: DCR C
JNZ Loop 1
RET
Subroutin2: LXI H, 2500H
MOV C, M
Loop1 INX H
CMP M

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JZ Loop2
DCR C
JNZ Loop1
Loop2 MVI A, 00H
MOV M, A
RET
Note: Subroutine 1 gives the largest number of array.
Subroutine 2 find the largest number and replace it by 00.

Counter and delay:

Timing delay using one register:
MVI C, FFH ---------- 7 T state
Loop DCR C -------------- 4 T state
JNZ Loop --------10 or 7 T state
Consider a micro computer with 2 MHZ frequency
Clock period , T = 1/f = ½ = 0.5 µ sec
Delay for inst. Outside the loop To = No of Ts state × T
= 7 × 0.5
= 3.5 µ sec

Delay for inst inside the loop, TL = No of T state × T * (N10)

= ( 14× 0.5 × 10-6 ×255)
= 1785 µ sec

Now TLA = TL-3× 0.5

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 = 1785 – 1.5
= 1.7835 ms

TD = T0 + TL
= 3.5 + 1785
= 1788.5
= 1.7885 ms

Time delay for register pair:

LXI B, 2384 H ………………. 10 T state
Loop DCX B …………………. 6 Tstate
MOV A, C …………………….. 4 T state
ORA B ………………………… 4 T state
JNZ loop ………………………. 10/7

Delay calculation:
T0 = T state * T
= 10 × 0.5 × 10-3
= 109 ms
TL = No of T state * T * (N10)
= 24 * 0.5 * 90.92
Total Delay = T0 + TL
=

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Time delay using a loop within a loop:
MVI B, 38 H …….. 7 T
Loop2 MVI C, FFH ………7 T
Loop 1 DCR C……..4 T
JNZ loop1 ------10/7 T
DCR B ------ 4 T
JNZ loop2 ------ 10/7 T

Delay calculation:
To = 7 * 0.5 = 3.5 µ sec
TL1 = 14 * 0.5 * 255 – 3*0.5
TL2 = ( TL1 + 21*0.5) N10 – 3
Total dealy = To + TL2

Q. Write a program to count continuously in hexadecimal from FFH to 00H in a

system with a 0.5 µ s clock period. Use register C to set up a 1 ms delay between
each count and display the number at one of the o/p ports.
MVI B, 00H
Next DCR B
MVI C, count
Delay DCR C
JNZ delay
MOV A, B
OUT port 1

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JMP Next

Delay calculation:
TL = T state * T* (T10)
= 14 × 0.5 × count
= 7 × count µ s

To = 35 × T
= 35 × 0.5
= 17.5 µ s

TD = TL + To
1 ms = 7 * count * 10-6 + 17.5 * 10-6

Count = 140.35
= 8C H

Q. Write a program to generate a continuous square wave with the period 500 µ
sec. Assume the system clock period is 325 µ sec and use bit Do to output the
square wave.
Solution:
MVI D, AA
ROTATE
MOV A, D

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RLC
MOV D, A
ANI 01 H
OUT PORT 1
MVI B, count
Delay DCR B
JNZ delay
JMP ROTATE

Delay calculation:
TL = 14 * 325 * 10-9 * count or 14 * 325 * (count - 1) + 11 T-state * 325
T0 = 46 * 325 * 10-9
TD = TL + T0
250 = (52.4)10 = 34 H

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 ASSEMBLY LANGUAGE PROGRAM DEVELOPMENT TOOLS

1. EDITOR

• An Editor is a Program which allows you to create a file containing the

Assembly Language statements for your Program.

2. ASSEMBLER

• An Assembler Program is used to translate the assembly language

mnemonics for instruction to the corresponding binary codes.

3. LINKER

• A Linker is a Program used to join several files into one large .obj file. It
produces
.exe file so that the program becomes
executable.

4. LOCATOR

• A Locator is a program used to assign the specific address of where the

segment of object code are to be loaded into memory.

• It usually converts .exe file to .bin file.

• A Locator program EXE2BIN converts .exe file to .bin file.

5. DEBUGGER

• A Debugger is a program which allows you to load your .obj code

program into system memory, execute program and troubleshoot.

• It allows you to look at the content of registers and memory locations

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 after your program runs.

• It allows to set the breakpoint.

6. EMULATOR

• An Emulator is a mixture of hardware and software.

• It is used to test and debug the hardware and software of an external

system such as the prototype of a Microprocessor based system.

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ASSEMBLY LANGUAGE PROGRAM FEATURES

#PROGRAM COMMENTS
• The use of Comments throughout a program can improve its clarity,
especially in Assembly Language.
• A Comment begins with
Semicolon. EXAMPLE
MOV AX, BX ; Adds the Content of BX with AX

#RESERVED WORDS
• Instructions : MOV, ADD
• Directives : END,SEGMENT
• Operators : FAR,OFFSET
• Predefined Symbols : @DATA

#IDENTIFIERS

• An Identifier (or symbol) is a name that you apply to an item in your

program that you expect to reference. The two types of identifiers are
NAME and LABEL.

• NAME : Refers to the Address of a data

item COUNTER DB 0

• LABEL: Refer to the Address of an instruction, procedure, or segment.

MAIN PROC
A20: MOV
AL,BL

#STATEMENTS

• An Assembly Program consists of a set of statements. The two types of

statements are:

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1. INSTRUCTION
• Instructions such as MOV & ADD which the Assembler translates to
Object Code.

2. DIRECTIVES
• Directives tell the Assembler to perform a specific action, such as
define a data item etc.

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ASSEMBLY LANGUAGE PROGRAMMING USING MASM

GENERAL PATTERN FOR WRITING ALP IN MASM

[PAGE DIRECTIVE]
[TITLE DIRECTIVE]
[MEMORY MODEL DEFINITION]

[SEGMENT DIRECTIVES]
[PROC DIRECTIVES]
……………………………………………

……………………………………………

……………………………………………

……………………………………………
[END DIRECTIVES]

BASIC FORMAT OF ALP BASED UPON THE GENERAL PATTERN

PAGE 60,80
TITLE "ALP TO PRINT FACTORIAL NO"

.MODEL [MODEL NAME]

.STACK
.DATA

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 ……………………… ; INITIALIZE DATA VARIALBLES
.CODE

MAIN PROC

……………………………
…………………………..
…………………………..
…………………………… ; INSTRUCTION SETS
…………………………..
……………………………
…………………………..
……………………………

MAIN ENDP
END MAIN

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DIRECTIVES

• Assembly Language supports a number of statements that enable to

control the way in which a source program assembles and lists. These
Statements are called Directives.

• They act only during the assembly of a program and generate no machine
executable code.

• The most common Directives are PAGE, TITLE, PROC, and END.

# PAGE DIRECTIVE

• The PAGE Directive helps to control the format of a listing of an assembled

program.

• It is optional Directive.

• At the start of program, the PAGE Directive designates the maximum

number of lines to list on a page and the maximum number of characters
on a line.

• Its format is
PAGE [LENGTH],[WIDTH]

• Omission of a PAGE Directive causes the assembler to set the default

value to PAGE 50,80

# TITLE DIRECTIVE
• The TITLE Directive is used to define the title of a program to print on
line 2 of each page of the program listing.

• It is also optional Directive.

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• Its format is
TITLE [TEXT]

TITLE "PROGRAM TO PRINT FACTORIAL NO"

# SEGMENT DIRECTIVE

• The SEGMENT Directive defines the start of a segment.

• A Stack Segment defines stack storage, a data segment defines data

items and a code segment provides executable code.

• MASM provides simplified Segment Directive.

• The format (including the leading dot) for the directives that defines the
stack, data and code segment are

.STACK [SIZE]
.DATA
………………. Initialize Data Variables
.CODE

• The Default Stack size is 1024 bytes.

• To use them as above, Memory Model initialization should be carried out.

# MEMORY MODEL DEFINTION

• The different models tell the assembler how to use segments to

provide space and ensure optimum execution speed.

• The format of Memory Model Definition is

.MODEL [MODEL NAME]

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• The Memory Model may be TINY, SMALL, MEDIUM, COMPACT, LARGE AND
HUGE.

MODEL TYPE DESCRIPTION

TINY All DATA, CODE & STACK Segment must fit in one
Segment of Size <=64K.
SMALL One Code Segment of Size
<=64K. One Data Segment of
Size <=64 K.
MEDIUM One Data Segment of Size
<=64K. Any Number of Code
Segments.
COMPACT One Code Segment of Size <
=64K. Any Number of Data
Segments.
LARGE Any Number of Code and Data Segments.
HUGE Any Number of Code and Data Segments.

#THE PROC DIRECTIVE

• The Code Segment contains the executable code for a program, which
consists of one or more procedures, defined initially with the PROC
Directive and ended with the ENDP Directive.
• Its Format is given as:
PROCEDURE NAME
PROC
………………..
……………….
……………….
PROCEDURE NAME
ENDP

#END DIRECTIVE
• As already mentioned, the ENDP Directive indicates the end of a procedure.

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• An END Directive ends the entire Program and appears as the last
statement.

• Its Format is

END [PROCEDURE NAME]

#PROCESSOR DIRECTIVE

• Most Assemblers assume that the source program is to run on a basic 8086
level.

• As a result, when you use instructions or features introduced by later

processors, you have to notify the assemblers be means of a processor
directive as .286,.386,.486 or
.586

• This directive may appear before the Code Segment.

#THE EQU DIRECTIVE

• It is used for redefining symbolic names
EXAMPLE
DATAX DB 25
DATA EQU
DATAX

#THE .STARTUP AND .EXIT DIRECTIVE

• MASM 6.0 introduced the .STARTUP and .EXIT Directive to simplify

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 program initialization and Termination.

• .STARTUP generates the instruction to initialize the Segment Registers.

• .EXIT generates the INT 21H function 4ch instruction for exiting the
Program.

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DEFINING TYPES OF DATA

• The Format of Data Definition is

given as [NAME] DN [EXPRESSION]

EXAMPLES
STRING DB 'HELLO WORLD'
NUM1 DB 10
NUM2 DB 90

DEFINITION DIRECTIVE
BYTE DB
WORD DW
DOUBLE WORD DD
FAR WORD DF
QUAD WORD DQ
TEN BYTES DT

• Duplication of Constants in a Statement is also possible and is

given by [NAME] DN [REPEAT-COUNT DUP (EXPRESSION)]

EXAMPLES
DATAX DB 5 DUP(12) ; 5 Bytes containing hex 0c0c0c0c0c
DATA DB 10 DUP(?) ; 10 Words Uninitialized

DATAZ DB 3 DUP(5 DUP(4)) ; 44444 44444 44444

1. CHARACTER STRINGS

• Character Strings are used for descriptive data.

• Consequently DB is the conventional format for defining character data of

any length

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• An Example is
DB 'Computer City'
DB "Hello World"
DB "[Link]'s College"

2. NUMERIC CONSTANTS

#BINARY : VAL1 DB 10101010B

#DECIMAL : VAL1 DB 230

#HEXADECIMAL : VAL1 DB 23H

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ALP SAMPLES USING DOS AND VIDEO BIOS FUNCTIONS

# SAMPLE 1

;Program to Print Hello World in ALP

;-------------------------------------------------------------

.MODEL SMALL

.STACK

.DATA

STRING DB 'HELLO WORLD $'

.CODE

;------------------------------------------------------------- MAIN PROC

MOV AX,@DATA

MOV DS,AX ; Initialize the DATA Segment

MOV DX,OFFSET STRING ; Load the Offset Address into DX MOV

AH,09H ; AH=09H For String Display until $ INT
21H ; DOS Interrupt Function

MOV AX,4C00H ; End Request with AH=4CH

; or AX=4C00H

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 INT 21H

MAIN ENDP ; End Procedure

END MAIN ; End Program

;-------------------------------------------------------------

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# SAMPLE 2

;Program to Print the Sum of Two 8 Bit Numbers

;-------------------------------------------------------------

.MODEL SMALL

.STACK

.DATA

VAL1 DB 89

VAL2 DB 10

.COD MSG DB 'SUM OF 2 NUMBERS: $'

E

;-------------------------------------------------------------

MAIN PROC

MOV AX,@DATA
MOV DS,AX

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MOV AX,0
MOV AL,VAL1
ADD AL,VAL2

AAM ;AAM Converts Binary Value to Unpacked BCD.

ADD AX,3030H ;Ax is Added with 3030H to Obtain ASCII Value

PUSH AX

;;;;;;;;;;;;;DISPLAY MESSAGE LEA

DX,MSG
MOV AH,09H
INT 21H
;;;;;;;;;;;;;END DISPLAY MESSAGE

POP AX
MOV DL,AH
MOV DH,AL
MOV AH,02H
INT 21H

MOV DL,DH
MOV AH,02H
INT 21H

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 MOV AX,4C00H
INT 21H
MAIN ENDP
END MAIN

;-------------------------------------------------------------

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# SAMPLE 3

;Program To Clear the Screen With Bios Interrupt Function.

;-------------------------------------------------------------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------

MAIN PROC

MOV AX,@DATA
MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 06H : Scroll Up Screen

;AH=Function 06H

;AL=Number of lines to scroll,or 00H for full screen

;BH=Attribute value(color,blinking)

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 ;CX=Strating row:column

;DX=Ending row :column

;;;;;;;;;;;;;;;;;;;;;;;;;;;

MOV AX,0600H ;AH=06,AL=00 for Full Screen

MOV BH,71H ;White background(7),Blue foreground(1) MOV

CX,0000H ;Upper left row:column
MOV DX,184FH ;lower right row:column INT
10H ;Bios Interrupt Function

MOV AX,4C00H
INT 21H

MAIN ENDP
END MAIN
;-------------------------------------------------------------

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# SAMPLE 4

;Progam to Display Character with Attributes

;-------------------------------------------------------------

.MODEL SMALL
.STACK

.DATA

.CODE

;-------------------------------------------------------------

MAIN PROC

MOV
AX,@DAT
A MOV
DS,AX

;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 09H: Display Character

;AH=09H

;AL=ASCII Character

;BH=Page Number

;BL=Attribute or Pixel value.

;CX=Count

;;;;;;;;;;;;;;;;;;;;;;

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 MOV AH,09H ;Request Display

MOV AL,01H ;Happy Face for

display MOV BH,00H ;Page
Number 0
MOV BL,0C1H ;Red background,Blue
foreground MOV CX,79 ;No of repeated
characters
INT 10H ;Bios Interrupt Function

MOV
AX,4C00
H INT
21H

MAIN
ENDP
END
MAIN
;-------------------------------------------------------------

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;Program to Print Hello World in ALP

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

STRING DB 'HELLO WORLD $'

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX ; Initialize the DATA Segment

MOV DX,OFFSET STRING ; Load the Offset Address into DX

MOV AH,09H ; AH=09H For String Display until $

INT 21H ; DOS Interrupt Function

MOV AX,4C00H ; End Request with AH=4CH or

AX=4C00H

INT 21H

MAIN ENDP ; End Procedure

END MAIN ; End Program

;-------------------------------------------------------------
--------

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;Program to Print the Sum of Two 8 Bit Numbers

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL1 DB 89

VAL2 DB 10

MSG DB 'SUM OF 2 NUMBERS: $'

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV AX,0

MOV AL,VAL1

ADD AL,VAL2

AAM ;AAM Converts Binary Value to Unpacked BCD.

ADD AX,3030H ;Ax is Added with 3030H to Obtain ASCII Value

PUSH AX

;;;;;;;;;;;;;DISPLAY MESSAGE

Downloaded from CSIT Tutor

 LEA DX,MSG

MOV AH,09H

INT 21H

;;;;;;;;;;;;;END DISPLAY MESSAGE

POP AX

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;16 Bit Binary Content of Ax
Ax is Converted to
to 4 Digit
Digit ASCII

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DW 256

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX ;DATA SEGMENT INITIALIZATION

MOV AX,VAL

XOR DX,DX ;DX IS CLEARED

MOV CX,100 ;DIVISOR IS PASSED INTO CX REGISTER

DIV CX ;DX:AX PAIR DIVIDED BY CX

;QUOTIENT IN AX

;REMAINDER IN DX

AAM ;QUOTIENT IS ADJUSTED TO UNPACKED BCD

ADD AX,3030H ;QUOTIENT IS CONVERTED TO ASCII

XCHG AX,DX ;DX AND AX ARE SWAPPED

AAM ;REMAINDER IS ADJUSTED TO UNPACKED BCD

ADD AX,3030H ;REMAINDER IS CONVERTED TO ASCII

;;;;;;;;;;;;;;;;;;;DISPLAY OPERATION

Downloaded from CSIT Tutor

 ;;DISPLAY QUOTIENT

;;DISPLAY REMAINDER

;;;;;;;;;;;;;;;;;;;END DISPLAY

MOV AX,4C00H ;END REQUEST

INT 21H ;DOS INTERRUPT FUNCTION

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Print the Difference of Two 8 Bit Numbers

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL1 DB 89

VAL2 DB 10

MSG DB 'DIFFERENCE OF 2 NUMBERS: $'

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV AX,0

MOV AL,VAL1

SUB AL,VAL2

;;;;; AAM Converts Binary Value to Unpacked BCD.

;;;;; AAM Only Works with AX Register

AAM

;;;;; AX is Added with 3030H to Obtain ASCII Value.

ADD AX,3030H

PUSH AX

Downloaded from CSIT Tutor

 ;;;;; DISPLAY MESSAGE With AH=09H

LEA DX,MSG

MOV AH,09H

INT 21H

;;;;; END DISPLAY MESSAGE

POP AX

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Print the Sum of Two 16 Bit Numbers

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL1 DW 2010

VAL2 DW 2050

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX ;INITIALIZE THE DATA SEGMENT

MOV AX,VAL1

ADD AX,VAL2 ;AX Holds 16 bit Value

;; 16 Bit Answer Splitting Strategy.

;; 16 Bit Division is Carried out

;; 32 Bit Divident (DX:AX) and 16 Bit Divisor is

Required.

XOR DX,DX ;Register DX is Cleared

MOV CX,100

DIV CX ;DX:Ax Divided by CX.

;Remainder in DX and Quotient in AX

AAM ;Quotient is Converted to Unpacked BCD

ADD AX,3030H ;Ready For Display i.e Converted to ASCII

MOV BX,AX ;Store the Quotient to BX

XCHG AX,DX ;Exchange the Contents of AX and DX

Downloaded from CSIT Tutor

 AAM ;Remainder is Converted to Unpacked BCD

ADD AX,3030H ;Remainder Converted to ASCII

PUSH AX ;Remainder Pushed to Stack

;;;;;;;;;;;;;;Quotient Ready in BX and Remainder Ready in

AX

;;;;;;;;;;;;;;Display Quotient First and then the

Remainder

;;;;;;;;;;;;;;Display Operation Started

MOV DL,BH

MOV AH,02H

INT 21H

MOV DL,BL

MOV AH,02H

INT 21H

POP AX

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

;;;;;;;;;;;;; Display Operation End

MOV AX,4C00H ; End Request AH=4CH

INT 21H ; Dos Interrupt Function

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Display Numbers From 0 To 9.[0
9.[0 1 2 3 4 5 6 7 8 9 ]

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DB '0'

.CODE

;-------------------------------------------------------------
--------

SPACE MACRO

MOV DL,' '

MOV AH,02H

INT 21H

ENDM

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV CX,26

MOV DL,VAL

TOP:

MOV AH,02H

INT 21H ;DISPLAY THE NUMBER

INC DL ;DL IS INCREMENTED BY 1

PUSH DX ;PUSH THE CONTENT OF DX TO STACK

Downloaded from CSIT Tutor

 ;;;;;;;;; INVOKED SPACE MACRO

SPACE

;;;;;;;;; END OF SPACE MACRO

POP DX ;POP THE CONTENT FROM STACK TO DX

DEC CX ;DECREMENT THE CONTENT OF COUNT BY 1.

JZ LAST ;JUMP TO LABEL LAST IF CX=0

JMP TOP ;UNCONDITIONAL JUMP TO LABEL TOP

LAST:

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Display Numbers From 0 To 9 With Line Feed

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DB 0

.CODE

;-------------------------------------------------------------
--------

LFEED MACRO

MOV AH,06H

MOV DL,0AH

INT 21H

MOV DL,0DH

INT 21H

ENDM

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV CX,10

MOV AH,00H

MOV AL,VAL

TOP:

Downloaded from CSIT Tutor

 MOV BL,AL

AAM

ADD AX,3030H

MOV DL,AL

MOV AH,02H

INT 21H

;;;;;;;; INVOKED LFEED MACRO FOR LINE FEED

LFEED

;;;;;;;; END OF LFEED MACRO

INC BL

MOV AL,BL

DEC CX

JZ LAST

JMP TOP

LAST:

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Display Alphabets From A To Z.
Z. [A B C D E F
…………………….. Z]

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DB 'A'

.CODE

;-------------------------------------------------------------
--------

SPACE MACRO

MOV DL,' '

MOV AH,02H

INT 21H

ENDM

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV CX,26

MOV DL,VAL

TOP:

MOV AH,02H

INT 21H

INC DL

PUSH DX

Downloaded from CSIT Tutor

 ;;;;;;;;; INVOKED SPACE MACRO

SPACE

;;;;;;;;; END OF SPACE MACRO

POP DX

DEC CX

JZ LAST

JMP TOP

LAST:

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Print the Sum of Natural Nos From 1 To
10.[1+2+3….+10]
10.[1+2+3….+10]

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DB 1

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV CX,10

MOV AL,VAL

MOV DL,0

TOP:

ADD DL,AL ;DL=DL+AL

INC AL ;INCREMENT THE CONTENT OF AL

DEC CX ;DECREMENT THE CONTENT OF CX

JZ LAST ;JUMP TO LAST IF CX=0

JMP TOP ;UNCONDITIONAL JUMP TO LABEL TOP

LAST:

MOV AL,DL ;FINAL SUM IN DL IS PASSED TO AL

Downloaded from CSIT Tutor

 ;AAM ALWAYS WORKS WITH AX REGISTER

;;;;;;;;;;;;DISPLAY OPERATION STARTED

AAM

ADD AX,3030H

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

;;;;;;;;;;;;END DISPLAY

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Demonstrate Multiplication Table of a Given Number

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DB 7

.CODE

;-------------------------------------------------------------
--------

GODOWN MACRO

MOV DL,0DH

INT 21H

MOV DL,0AH

INT 21H

ENDM

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX ; Initialize Data Segment

MOV AX,0 ; Make AX as 0

MOV CX,10 ;Initialize the Counter

MOV BL,1

TOP:

Downloaded from CSIT Tutor

 MOV AL,BL

MUL VAL ; Multiply the Content of Val and AL :

Answer in AL

AAM

ADD AX,3030H

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

GODOWN ; Invoked GoDOWN Macro

MOV AX,0

INC BL

DEC CX

JZ LAST

JMP TOP

LAST:

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Calculate Factorial of Given Number

;2005

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL DW 7

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX ; Initialize Data Segment

MOV AX,VAL ; AL is Passed with the Content of DI

MOV CX,AX ; Counter to no given in val

DEC CX ; Decrement the Content of CL to make n-1

TOP:

MUL CX ; Multiply the content of AL and CL

answer in AL

DEC CX ; Decrement the content of cl

JZ LAST ; Jump if Zero to Last

JMP TOP ; JMP to Top Unconditionally

LAST:

MOV CX,100

DIV CX ; Quotient in AX and Remainder in DX

Downloaded from CSIT Tutor

 AAM ; Adjust Quotient to Unpacked BCD

ADD AX,3030H

MOV BX,AX ; Prserve the Content of AX to BX

XCHG AX,DX

AAM

ADD AX,3030H

PUSH AX ; Preserve the Content of AX into Stack

;;;;;;;;;;;;; Display Operation Started

MOV DL,BH

MOV AH,02H

INT 21H

MOV DL,BL

MOV AH,02H

INT 21H ; Quotient Printing is Finished

POP AX

MOV DL,AH

MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H ; Remainder Printing is Finished

;;;;;;;;;;;;; Display Operation Finished

MOV AX,4C00H

INT 21H ; Normal End Request

MAIN ENDP

END MAIN

Downloaded from CSIT Tutor

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Print the Fibonaci Series.[1
Series.[1 2 3 5 8 13 21 ..]

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

VAL1 DB 0

VAL2 DB 1

.CODE

;-------------------------------------------------------------
--------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

MOV AL,VAL1 ; A = VAL1

MOV BL,VAL2 ; B = VAL2

MOV CX,10

MOV AH,00H

TOP:

ADD AL,BL ; P= A+B

MOV BH,BL ; TEMP1=B

PUSH AX ; CONTENT OF A IS PUSHED TO STACK

;;;;;;;;;;; DISPLAY OPERATION STARTED

AAM

ADD AX,3030H

MOV DL,AH

Downloaded from CSIT Tutor

 MOV DH,AL

MOV AH,02H

INT 21H

MOV DL,DH

MOV AH,02H

INT 21H

MOV DL,' '

MOV AH,02H

INT 21H

;;;;;;;;;;; DISPLY OPERATION END

POP AX ; CONTENT OF STACK IS POPED TO AX

MOV BL,AL ; B=P

MOV AL,BH ; A=B

LOOP TOP ; DECREMENT THE CONTENT OF CX BY1

; JUMP TO LABEL TOP UNTIL CX > 0

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program To Demonstrate File Handles For Input and Output

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

KEYDISP DB 'Enter Character/Number[10]: $'

KEYINP DB 20 DUP(' ') ;Additional 2 Characters For

0DH & 0CH

;0DH : Enter

;0CH : Line Feed

KEYOUT DB 'Output : $'

.CODE

;-------------------------------------------------------------
--------

DISPLAY MACRO A

LEA DX,A

MOV AH,09H

INT 21H

ENDM

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

; KEYDISP IS A PARAMETER TO
MACRO

DISPLAY KEYDISP ; Invoked DISPLAY MACRO

CALL READ

; KEYOUT IS A PARAMETER TO MACRO

DISPLAY KEYOUT ; Invoked DISPLAY MACRO

Downloaded from CSIT Tutor

 MOV CX,20

TOP :

MOV DL,[BX]

MOV AH,02H

INT 21H

INC BX

DEC CX

JZ LAST

JMP TOP

LAST:

MOV AX,4C00H

INT 21H

MAIN ENDP

;-------------------------------------------------------------
--------

;READ PROCEDURE FOR KEYBOARD INPUT USING FILE HANDLES

;AH=FUNCTION 3FH

;BX=00H INDICATES INPUT

;CX=MAXIMUM NO OF CHARACTERS TO ACCEPT

;DX=ADDRESS OF AREA FOR ENTERING CHARACTERS

READ PROC

MOV AH,3FH

MOV BX,00H

MOV CX,20

LEA DX,KEYINP

INT 21H

MOV BX,DX

RET

READ ENDP

;-------------------------------------------------------------
--------

END MAIN

Downloaded from CSIT Tutor

;Program to Print the Input String In Reverse
Reverse Order.

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

;;;;;;;;;;;;;;;;;;;;;Data Segment Initialization Started

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;Data Segment Initialization Ended

MOV CX,0 ;Initialize the Counter as 0

READ_CHAR:

MOV AH,01H ;Put AH=01H to Read Character From

Keyboard

INT 21H ;Reads Character and Puts it in AL

CMP AL,0DH ;0DH is the ASCII Code For Enter

Key

;Check if Enter Key is Pressed

JE END_OF_LINE ;If Enter Pressed Go to END_OF_LINE

PUSH AX ;Push Character into Stack

INC CX ;Increment Counter CX

Downloaded from CSIT Tutor

 JMP READ_CHAR ;Unconditional Jump to READ_CHAR

END_OF_LINE:

POP DX ;Pop Character From Stack into

DX

MOV AH,02H ;Code for Displaying character on

VDU

INT 21H ;DOS Interrupt Function

LOOP END_OF_LINE ;Loop Until CX=0

MOV AX,4C00H ;End Request

INT 21H ;Dos Interrrupt Function

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program To Clear the Screen With Bios Interrupt Function.
Function.

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 06H : Scroll Up Screen

;AH=Function 06H

;AL=Number of lines to scroll,or 00H for full screen

;BH=Attribute value(color,blinking)

;CX=Strating row:column

;DX=Ending row :column

;;;;;;;;;;;;;;;;;;;;;;;;;;;

MOV AX,0600H ;AH=06,AL=00 for Full Screen

MOV BH,71H ;White background(7),Blue foreground(1)

MOV CX,0000H ;Upper left row:column

MOV DX,184FH ;lower right row:column

INT 10H ;Bios Interrupt Function

MOV AX,4C00H

INT 21H

Downloaded from CSIT Tutor

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Set the Cursor in Desired Location

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 02H: Set Cursor Position

;AH=Request Cursor with AH=02H

;BH=Page Number [Default 00H]

;DH=Row

;DL=Column

;;;;;;;;;;;;;;;;;;;;

MOV AH,02H ;Request Set Cursor

MOV BH,00 ;Page Number to 0

MOV DH,08 ;Row 8

MOV DL,50 ;Column 50

INT 10H ;Bios Interrupt Function

MOV DL,'C' ;Character to be Displayed in DL

Downloaded from CSIT Tutor

 MOV AH,02H ;Character Mode

INT 21H ;Dos Interrupt Function

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Progam to Display Character with Attributes

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 09H: Display Character

;AH=09H

;AL=ASCII Character

;BH=Page Number

;BL=Attribute or Pixel value.

;CX=Count

;;;;;;;;;;;;;;;;;;;;;;

MOV AH,09H ;Request Display

MOV AL,01H ;Happy Face for display

MOV BH,00H ;Page Number 0

MOV BL,0C1H ;Red background,Blue foreground

MOV CX,79 ;No of repeated characters

INT 10H ;Bios Interrupt Function

MOV AX,4C00H

Downloaded from CSIT Tutor

 INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Demonstrate Screen Scroll Down

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H Function 07H : Scroll Down Screen

;AH=Function 07H

;AL=Number of lines to scroll,or 00H for full screen

;BH=Attribute value(color,blinking)

;CX=Strating row:column

;DX=Ending row :column

;;;;;;;;;;;;;;;;;;;;;;;;;;;

MOV AX,0702H ;AH=07,AL=00 for Full Screen

MOV BH,71H ;White background(7),Blue foreground(1)

MOV CX,0C19H ;Upper left row:column

MOV DX,1236H ;lower right row:column

INT 10H ;Bios Interrupt Function

MOV AX,4C00H

INT 21H

Downloaded from CSIT Tutor

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Plot Pixels in Graphics Mode

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H: Get Current Video Mode

;AH=0FH

;AL=Returns Current Video Mode

;AH=Number of Screen Columns

;BH=Active Video Page

MOV AH,0FH

INT 10H

PUSH AX ;PUSH the Current Mode to Stack

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H : Set Video Mode

;AH=00H

Downloaded from CSIT Tutor

 ;AL=Required Mode

MOV AH,00H

MOV AL,13H

INT 10H

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;INT 10H : Write Pixel Dot

;AH=0CH

;AL=Color of the Pixel

;BH=Page Number

;CX=Column

;DX=ROW

MOV BH,00

MOV DX,10

MOV CX,10

MOV BL,00

TOP:

MOV AH,0CH

MOV AL,BL

INT 10H

INC DX

INC BL

CMP DX,100

JNE TOP

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;KEYBOARD INPUT

;AH=01H

Downloaded from CSIT Tutor

 ;AL=Returns Key IN ASCII

MOV AH,01H

INT 21H

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;Return to Previous Graphics Mode

POP AX

MOV AH,00H

INT 10H

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

MOV AX,4C00H

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program to Print the String in Reverse Order

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

STRING DB '!EMOC-LEW'

REVERSE DB 9 DUP(' ')

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

LEA SI,STRING ;Load Effective Address of STRING into

SI

LEA DI,REVERSE ;Load Effective Address of REVERSE into

DI

ADD DI,9 ;Add the Address of DI With 9

MOV CX,9 ;Initialize Counter as 9

TOP:

MOV AL,[SI] ;Content of SI to AL

MOV [DI],AL ;Content of AL to Content of DI

INC SI ;Increment SI

DEC DI ;Decrement DI

LOOP TOP ;Loop Until CX!=0

Downloaded from CSIT Tutor

 ADD DI,10 ;Add DI With 10 to Locate to End

MOV AL,'$' ;Add String Termination Character

MOV [DI],AL

MOV AH,09H ;AH=09 Specifies String

LEA DX,REVERSE ;Load Effective Address of REVERSE

into DX

INT 21H ;DOS Interrupt Function

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor

;Program To Change The String Into Toggle Case

;-------------------------------------------------------------
--------

.MODEL SMALL

.STACK

.DATA

STRING DB 'Welcome'

CASE DB 7 DUP(' ')

.CODE

;-------------------------------------------------------------
--------

MAIN PROC

MOV AX,@DATA

MOV DS,AX

LEA SI,STRING ;Load Effective Address of STRING into

SI

LEA DI,CASE ;Load Effective Address of CASE with DI

MOV CX,7 ;Load Counter with 7

TOP:

CMP CX,0000H ;Compare CX with 0

JE EXIT ;If CX=0 then Goto Exit

MOV AH,[SI] ;Load Content of SI into AH

CMP AH,60H ;Compare AH with 60H i.6 96

JA ISSMALL

CMP AH,5AH ;Compare AH with 5AH i.e 90

JB ISCAP

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;TO UPPERCASE

ISSMALL:

AND AH,11011111B ;Mask With 11011111B

MOV [DI],AH

Downloaded from CSIT Tutor

 INC SI

INC DI

DEC CX

JMP TOP

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

;TO LOWERCASE

ISCAP:

OR AH,00100000B ;Mask With 00100000B

MOV [DI],AH

INC SI

INC DI

DEC CX

JMP TOP

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

EXIT:

MOV AL,'$' ;Add String Terminator.

MOV [DI],AL ;Pass the Content of AL to DI.

MOV DX,OFFSET CASE

MOV AH,09H

INT 21H

MOV AH,4CH

INT 21H

MAIN ENDP

END MAIN

;-------------------------------------------------------------
--------

Downloaded from CSIT Tutor