Semiconductor Manufacturing Technology
IC Fabrication Process Overview
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Overview of Areas in a Wafer Fab
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Overview of Areas in a Wafer Fab
• 光學微影 (Photolithography)：透過光學投影將設計的圖案轉移到晶圓表面的光阻層上
• 蝕刻 (Etching)：移除未被光阻保護的部分，通常是去除薄膜或多層材料，留下所需的圖案
• 離子佈植 (Ion Implantation)：加速離子並將其植入半導體材料中，改變其電子特性
• 加熱製程 (Thermal Processes)：摻雜、活化、氧化層生長、退火
• 化學氣相沉積 (CVD)：化學方法沉積薄膜，這些薄膜可能是導電層、絕緣層
• 物理氣相沉積 (PVD)：物理方法沉積薄膜，常見的技術為濺鍍。常用於金屬層
• 化學機械平坦化 (CMP)：通過化學和機械的結合來平整晶圓表面，使其在多層製程中保持平坦
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Photolithography
• 黃光區是進行曝光的地方，製程中關鍵的步驟。利用光罩和光阻，藉由曝光和顯影來定義晶片
上微小的電路結構，也就是將光罩圖案轉印到晶圓表面。通常使用DUV或EUV光源。
• 黃光不會對光阻產生曝光效應，可以安全地在製程區域內使用而不會破壞光刻過程。
• 曝光後接續的製程：蝕刻或離子佈植
Light
Mask (reticle)
Projection
lens
Field
wafer
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Positive Lithography
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Negative Lithography
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CMOS Manufacturing Steps (1980-2000)
1. Twin-well Implants
2. Shallow Trench Isolation
3. Gate Structure
4. Lightly Doped Drain Implants
5. Sidewall Spacer
6. Source/Drain Implants
7. Contact Formation
8. Local Interconnect
9. Interlayer Dielectric to Via-1
10. First Metal Layer
11. Second ILD to Via-2
12. Second Metal Layer to Via-3
13. Metal-3 to Pad Etch
14. Parametric Testing
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n-well Formation
• Step1 – epitaxial layer possesses improved quality and fewer defect
• Step2 – initial oxide (15 nm): (1) protects epi layer from contamination, (2) prevents excessive damage
to ion/implantation, (3) control the depth of the dopant during implantation
• Step3 – photolithography
• Step4 – ion implantation
• Step5 – anneal: (1) drive-in, (2) repair damage, (3) activation
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Mask # 1: N-well Formation
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Annealing of Silicon Crystal
• 使用傳統高溫爐管退火容易導致雜質過度擴散 (溫度過高加上過長的製程時間)
• RTP (Rapid thermal process) 常用於佈值後退火，可以減少熱處理時間，從而控制擴散深度，避
免過度擴散。 (~150°C/sec)
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p-well Formation
• Step1 – photolithography, 2nd mask, this mask is the direct opposite of the n-well implant mask
• Step2 – ion implantation, Boron is 1/3 the mass of P, so 1/3 energy is used
• Step3 – anneal
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Mask # 2: P-well Formation
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STI Trench Etch
STI: shallow trench isolation (淺溝隔離)
• Step1 – barrier oxide (new)
• Step2 – silicon nitride: (1) protect active region, (2) stop layer during CMP
• Step3 – photolithography
• Step4 – STI etching
Selective etching opens isolation regions in the epi layer.
+Ions
Thin
Polish
3 Photoresist
Films
4
1 2 3 4 2 Nitride
1 Oxide
Diffusion Photo Etch
n-well p-well
STI trench
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 3: Shallow Trench Isolation Formation
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STI Oxide Fill
• Step1 – liner oxide, being used to improve the interface between the silicon and trench CVD oxide
• Step2 – CVD oxide deposition or spin-on-glass (SOG)
Trench fill by chemical vapor deposition
Oxide
2
2 Thin
Films Polish Trench CVD oxide
1 Nitride
1
Diffusion Photo Etch
n-well p-well
Liner oxide
Implant p- Epitaxial layer
p+ Silicon substrate
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STI Formation
• Step1 – trench oxide polish (CMP): nitride as the CMP stop layer since nitride is harder than oxide
• Step2 – nitride strip: by using hot phosphoric acid (熱磷酸)
• Step3 – anti-punch-through and Vth adjustment ion implantation
Planarization by chemical-mechanical polishing
1
1
Thin Polish
Films
STI oxide after polish
2
2 Nitride strip
Diffusion Photo Etch
n-well p-well
Liner oxide
Implant p- Epitaxial layer
p+ Silicon substrate
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Poly Gate Structure Process
• Step1 – thermal grown oxide: thickness 1.5 ~ 5.0 nm
• Step2 – poly-Si: ~ 300 nm is doped and deposited by CVD
• Step2.5 – antireflective coating (ARC): to avoid light reflection during exposure
• Step3 – photolithography
• Step 4 – poly-Si etching: the most critical etching step in dry etching
3 Photoresist
Polysilicon
Thin deposition 2 ARC 4 Poly gate etch
Polish
Films
1 2 3 4 1 Gate oxide
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 4: Poly-Si Gate Formation
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n- LDD Implant
• Step1 – photolithography
• Step2 – lightly doped drain to reduce S/D leakage. Large mass implant (As instead of P) and
amorphous surface of oxide helps maintain a shallow junction
2 Arsenic n- LDD implant
Thin Polish 1 Photoresist mask
Films
1
Diffusion Photo Etch n- n- n-
n-well p-well
2
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 5: n- LDD Formation
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p- LDD Implant
• Step1 – photolithography
• Step2 – lightly doped drain Large mass implant (BF2 instead of B) and amorphous surface helps
maintain a shallow junction
Note: In modern device, high doped drain is used to reduce series resistance, called S/D extension
2 BF2 p- LDD implant
Thin Photoresist Mask
Polish Photoresist mask
1 1
Films
1
Diffusion Photo Etch n- p- p- n- n- p-
n-well p-well
2
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 6: p- LDD Formation
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Side Wall Spacer Formation
• Step1 – spacer oxide CVD: being used to prevent higher S/D implant from penetrating too close to the
channel, and to cover LDD
• Step2 – etch back by anisotropic plasma etching
2 Spacer etchback by anisotropic plasma etcher
Thin Polish
1
Films +Ions
1 Spacer oxide Side wall spacer
2
Diffusion Photo Etch n- p- p- n- n- p-
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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n+ Source/Drain Implant
• Step1 – photolithography
• Step2 – n+ S/D: energy is higher than LDD I/I, the junction is deeper
2 Arsenic n+ S/D implant
Thin Polish 1 Photoresist mask
Films
1
Diffusion Photo Etch n+ p-well n+
n+ n-well
2
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 7: n+ Source/Drain Formation
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p+ Source/Drain Implant
• Step1 – photolithography
• Step2 – p+ S/D: energy is higher than LDD I/I, the junction is deeper
• Step3 – using rapid thermal anneal (RTA) to prevent dopant spreading and diffusion
2 Boron p+ S/D implant
Thin Photoresist Mask
Polish Photoresist mask
1 1
Films
1
Diffusion Photo Etch
n+ p+ n-well p+ n+ p-well n+ p+
3 2
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 8 : p+ Source/Drain Formation
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Contact Formation
• Step1 – Titanium (Ti): low resistivity and good adhesion for metal contact (Ar sputtering, PVD)
• Step2 – anneal to form TiSi2: tisilicide
• Step3 – chemical etching to remove unreacted Ti (selective etching)
1 Titanium depostion
1 2 3 Thin Polish 2 Tisilicide contact formation (anneal)
Films Titanium etch
3
Diffusion Photo Etch p+ n+
n+ p+ n-well n+ p-well p+
Implant p- Epitaxial layer
p+ Silicon substrate
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Damascene Process
• LI: Local Interconnect
• Damascene process involves filling metal into pre-etched patterns and then planarizing it.
LI metal
LI oxide
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Local Interconnect Oxide (ILD0)
• Step1 – nitride: being used to protect active region
• Step2 – doped oxide (PSG) by CVD
• Step3 – oxide CMP
• Step4 – photolithography & etching
2 Doped oxide CVD
3
2 Thin 1 Nitride CVD 3 Oxide polish 4 LI oxide etch
Polish
1 Films
LI oxide
4
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 9: Local Interconnection Formation
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LI Metal Formation
• Step1 and Step2 – Ti/TiN: Ti for adhesion and TiN for diffusion barrier
• Step3 – Tungsten CVD: being preferred over Al due to its ability to fill holes without leaving voids
• Step4 – Tungsten CMP
1 2 3 4
Ti/TiN 3 Tungsten 4 LI tungsten polish
2 deposition deposition
Thin Polish
Films
LI oxide
Diffusion Photo Etch
1 n-well p-well
Ti deposition
Implant p- Epitaxial layer
p+ Silicon substrate
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Via-1 Formation
Via: electrical pathway from one metal layer to adjacent metal layer
• Step1 – ILD1: insulator between metal (800nm)
• Step2 – ILD CMP
• Step3 – photolithography & etching
1 ILD-1 oxide ILD-1 oxide etch
deposition 2 Oxide polish 3 (Via-1 formation)
2
ILD-1
Thin
1 Films Polish
LI oxide
3
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 10: Via-1 Formation
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Plug-1 Formation
• Step1 and Step2 – Ti / TiN /W: Ti as a glue layer to hold W, TiN as the diffusion barrier
• Step3 – Tungsten(W) CVD: being preferred over Al due to its ability to fill holes without leaving voids
• Step4 – Tungsten CMP
Ti/TiN 3 Tungsten
2 deposition deposition 4Tungsten polish (Plug-1)
1 2 3 4 1 ILD-1
Thin Ti dep.
Films Polish
LI oxide
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Polysilicon, Tungsten LI and Tungsten Plugs
Tungsten LI Polysilicon
Tungsten
plug
Mag. 17,000 X
Micrograph courtesy of Integrated Circuit Engineering
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Metal-1 Interconnect Formation
• Step1 – metal stack: Ti / TiN / Al (or Cu) / TiN (ARC) is used
• Step2 – Al(99%) + Cu (1%): being used to improve reliability
• Step3 – metal cap TiN
• Step4 – metal-1 etching
Ti Deposition Al + Cu (1%) TiN
2 deposition 3 deposition 4 Metal-1 etch
1
1 2 3
ILD-1
Thin Polish
Films
LI oxide
4
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 11: Metal-1 Formation
Common gate for input
P+ Source to Vdd N+ Source to ground
Common drain or output to next stage
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Metal-1 over First Set of Tungsten Vias
TiN metal cap
Metal 1, Al
Tungsten plug Mag. 17,000 X
Micrograph courtesy of Integrated Circuit Engineering
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Via-2 Formation
• Step1 – gap fill: fill the gap between metal
• Step2 – ILD2: insulator between metal
• Step3 – ILD2 CMP
• Step4 – photolithography & etching
ILD-2 oxide ILD-2 oxide etch
2 deposition
3 Oxide polish 4 (Via-2 formation)
1 ILD-2 gap fill
1 2 3
ILD-1
Thin
Polish
Films
LI oxide
4
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
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Mask # 12: Via-2 Formation
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Plug-2 Formation
• Step1 and Step2 – Ti / TiN /W : Ti as a glue layer to hold W, TiN as the diffusion barrier
• Step3 – Tungsten(W) CVD
• Step4 – Tungsten CMP
Tungsten
Ti/TiN Tungsten deposition 3
2 deposition 4 polish (Plug-2)
1 Ti deposition ILD-2
1 2 3 4
ILD-1
Thin Polish
Films
LI oxide
Diffusion Photo Etch
n-well p-well
Implant p- Epitaxial layer
p+ Silicon substrate
42
Metal-2 Interconnect Formation
• Step1 – metal-2: Ti/Al/TiN
• Step2 – ILD-3 gap filling and deposition
• Step3 – ILD-3 CMP
• Step4 – Via-3 etch and via deposition, Ti/TiN/W
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Mask # 13: Metal-2 Formation
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Mask # 14: Via-3 Formation
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Mask # 15: Metal-3 Formation
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Front End of Line (FEOL)
CMOS layout (mask 1 to mask 12)
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Full 0.18 μm CMOS Cross Section
• Passivation layer of nitride is used to protect from moisture, scratched, and contamination.
• ILD-6 oxide is used to alleviate the stress of the nitride.
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Cross-section of AMD Microprocessor
Mag. 18,250 X
Micrograph courtesy of Integrated Circuit Engineering 49