1. What is a lock-up latch and what are its applications?

Lock-up latch is a special latch placed between two flip-flops that are in different clock domains,
especially within a scan chain for Design-for-Testability (DFT). Its main job is to
lock the data to prevent race conditions during a scan shift operation when the clocks are
asynchronous or have different phases.
Without a lock-up latch, a data signal could arrive at the next flip-flop too early or too late, which
would lead to setup and hold time violations and corrupt the test data. The latch works by holding the
data signal stable until the receiving flip-flop's clock domain can safely capture it. This ensures that
no timing violations occur during the test.

Applications:

 It ensures reliable scan test shifting in multi-clock domain systems on a chip (SoCs).
 It maintains data integrity during test operations in asynchronous clock domains.
 It prevents race conditions when signals cross between clock domains in test modes.

2. What is a transparent latch?

Transparent latch is a level-sensitive digital device that allows input data to pass directly to its output
whenever its enable signal is active. It's called "transparent" because when enabled, it acts just like a
simple wire, with the output following the input. When the enable signal becomes inactive, the latch
"holds" or latches the last value it received, and the output remains stable regardless of any further
changes to the input.

 When Enable is High (1): The output (Q) follows the input (D).
 When Enable is Low (0): The output (Q) holds its previous value.

3. What's the difference between a latch and a flip-flop?

The primary difference between a latch and a flip-flop lies in their trigger type and transparency. A
latch is a level-sensitive device, meaning its output can change whenever its enable signal is active.
For example, a transparent D-latch passes the input to the output as long as the clock is high. In
contrast, a flip-flop is an edge-triggered device, which means its output only changes at a specific
clock edge (either rising or falling).

Feature Latch Flip-Flop

Level-sensitive (e.g., HIGH or Edge-triggered (e.g., rising or falling
Trigger Type
LOW) edge)
Transparency Transparent when enabled Not transparent
Lower risk; only changes at the clock
Glitches Higher risk due to its transparency
edge
Complexity Simpler More complex
Power Typically lower power usage Slightly higher power usage
Speed Faster switching Slower but more predictable

4. What are setup and hold times?

 Setup and hold times are two crucial timing parameters that must be met for a flip-flop to reliably
capture data.

 Setup Time (tsetup): This is the minimum time that the data input (D) must be stable before
the active clock edge arrives. It's the time needed to "prepare" the input so the flip-flop can
correctly capture it.
 Hold Time (thold): This is the minimum time that the data input (D) must remain stable after
the active clock edge. It's the time needed for the flip-flop to "lock in" the captured data,
preventing it from being corrupted.

Failure to meet either of these times can lead to a timing violation and a potential circuit
malfunction.

5. What are data arrival time and data required time?

These two concepts are used to check for timing violations in a digital circuit.

 Data Arrival Time: This is the actual time it takes for a data signal to travel from a source flip-
flop's output (Q) to the input (D) of a destination flip-flop. It includes all the delays along the
path, such as the clock-to-Q delay of the source flip-flop, the delay from any logic gates in
between, and the wire delays.
 Data Required Time: This is the latest time by which the data must arrive at the destination
flip-flop's input to be correctly captured on the next clock edge. It's calculated by subtracting the
flip-flop's setup time from the clock period. This ensures that the data is stable before the setup
window begins.

6. What are jitter, skew, and slack?

 Jitter: This is the random, unpredictable variation in a clock's edge timing. It's caused by things
like power noise, temperature changes, or crosstalk, and can lead to timing violations if a clock
edge arrives too early or too late.
 Skew: This is the difference in the arrival times of a single clock signal at two different flip-flops
in a circuit. For example, the clock might arrive at the "launch" flip-flop at a different time than it
arrives at the "capture" flip-flop.
 Slack: This is a measure of the timing margin in a circuit. It is the difference between the data
required time and the data arrival time.
o Positive Slack: The circuit meets its timing requirements, and there is no issue.
o Zero Slack: The circuit barely meets its timing requirements.
o Negative Slack: There is a timing violation, and the circuit may fail.

7. What's the difference between RTL and Synthesis?

Feature RTL (Register Transfer Level) Synthesis

The process of converting RTL
A high-level, human-written description of
What Is It? into a gate-level netlist using a
digital logic.
tool.
Abstraction Low-level; represents actual logic
High-level; describes functional behavior.
Level gates, flip-flops, etc..
Concrete timing (delay, setup,
Timing Clock is defined, but timing is abstract.
hold) is considered.
A testable design with a test
Output The output of the design phase.
infrastructure.
 Feature RTL (Register Transfer Level) Synthesis
To describe how data moves between To improve fault coverage and
Goal
registers. reduce testing costs.
Example Writing Verilog or VHDL code with if-else and case statements.

8. What's the difference between a pin and a pad?

Feature Pin Pad

A physical metal contact on the
Definition A logical connection point for a signal.
silicon or a PCB.
Logical; seen in RTL, schematics, and Physical; seen in layout and
Abstraction
netlists. floorplanning.

9. What is a tri-state buffer?

tri-state buffer is a type of digital buffer that has three possible output states: logic high (1), logic
low (0), and a third state called high impedance (Z). In the high impedance state, the output is
effectively disconnected from the line, meaning it doesn't drive the output high or low. This is
controlled by an enable signal.
The high impedance state is what makes it so useful. It allows multiple devices to share the same bus
or output line without interfering with each other. When using a tri-state buffer, only one device is
allowed to drive the bus at any given time, while all other devices connected to the bus are put into
the high impedance state.

[Link] are Yield and DPPM?

These two terms are used to measure the quality and efficiency of a manufacturing process.

 Yield: This is the percentage of good, non-defective chips out of the total number of chips
produced. A higher yield indicates a more efficient and higher-quality manufacturing process.
The formula is:

Yield=(Total Chips ProducedNumber of Good Chips)×100%

 DPPM (Defective Parts Per Million): This quantifies the number of defective units in a million
produced chips. It provides a more fine-grained measure of defects, which is useful for
monitoring process improvements and setting quality targets. The formula is:

DPPM=(Total Chips ProducedNumber of Defective Chips)×1,000,000

[Link]'s the difference between Functional Verification and DFT?

Aspect Functional Verification Design for Testability (DFT)

To make the design easier to test for
Purpose To check if the design works as intended.
manufacturing defects.
Verifying the functional behavior of the
Focus Enhancing the hardware's testability.
design.
Happens during the RTL design phase before Happens during design implementation before
Timing
fabrication. manufacturing.
Goal Find bugs and logical errors in the design. Improve fault coverage and reduce testing costs.
Example Writing testbenches and running simulations. Adding scan chains and BIST modules.
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 [Link] are defect, fault, error, and failure?

These terms describe different stages of a problem in a digital circuit.

Term Meaning Example

Defect A physical flaw or imperfection in the hardware. A broken transistor on a chip.
A manifestation of a defect that can cause incorrect behavior A signal line being permanently
Fault
in the circuit logic. stuck at a logic 0 ("stuck-at-0").
An incorrect internal state or data caused by a fault during A flip-flop storing the wrong value
Error
operation. after a clock cycle.
When the system deviates from its expected behavior, The chip producing the wrong data
Failure
becoming visible at the output or system level due to an error. or stopping its function.
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[Link]'s the difference between testing and diagnosis?

Aspect Testing Diagnosis

To determine if a fault or defect exists in the To identify the exact cause and location of a
Purpose
system (pass/fail). fault.
Focus Checking if the system works correctly. Pinpointing what's wrong and why.
Detailed information about the fault (type and
Outcome A pass/fail result.
location).
When During manufacturing, quality assurance (QA), or
After a test failure is observed.
Used maintenance.
Locating the specific faulty memory cell
Example Running a memory test to check for errors.
causing the errors.
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[Link] are fault instantiation and fault propagation?

These two concepts are fundamental to fault simulation and test generation.

 Fault Instantiation: This is the act of intentionally modeling or injecting a fault at a specific
location within a circuit for testing and analysis. For example, you might "instantiate" a stuck-at-1
fault on a signal line, which means you assume that line is always at logic 1, regardless of its actual
input. This helps you simulate how the circuit would behave with that fault.
 Fault Propagation: This is the process by which the effect of an instantiated fault travels through
the circuit's logic until it reaches an observable output. For a fault to be detectable, its effect must be
able to propagate to a point where it can be measured and compared against the expected, fault-free
behavior.

[Link] are LVT, SVT, and HVT transistors?

These terms refer to different types of transistors used in chip design, categorized by their threshold voltage
(Vth). This voltage determines how much gate voltage is needed to turn the transistor on.

 LVT (Low Threshold Voltage): These transistors have a low Vth, meaning they turn on with less
voltage.
o Characteristics: They offer fast switching speeds but consume higher leakage power even
when they're off.
 o Usage: They're used in timing-critical paths and high-performance blocks like CPU and
GPU cores.
o Impact on DFT: Their high power consumption can cause issues like IR drop or thermal
problems during test modes.
 SVT (Standard Threshold Voltage): These transistors have a moderate Vth.
o Characteristics: They provide a balanced trade-off between speed and power, with moderate
leakage and dynamic power usage.
o Usage: They are the default choice for most standard cell libraries and general logic.
o Impact on DFT: They offer a good balance for scan chain insertion with minimal power and
timing issues during testing.
 HVT (High Threshold Voltage): These transistors have a high Vth, requiring more voltage to turn
on.
o Characteristics: They have slower switching speeds but very low leakage power, making
them great for power saving.
o Usage: They're used in non-critical paths and low-power designs like IoT and mobile chips.
o Impact on DFT: They can cause setup time violations in scan mode but are excellent for
reducing overall leakage power during testing.