®

ISL6559

Data Sheet July 2003 FN9084.4

Multi-Phase PWM Controller Features

The ISL6559 provides core-voltage regulation by driving 2 to • Multi-Phase Power Conversion
4 interleaved synchronous-rectified buck-converter channels - 2, 3 or 4 Phase Operation
in parallel. Interleaving the channel timing results in • Active Channel Current Balancing
increased ripple frequency which reduces input and output • Precision rDS(ON) Current Sharing
ripple currents. The reduction in ripple results in lower - Lossless
component cost, reduced dissipation, and a smaller - Low Cost
implementation area. • Input Voltage: 12V or 5V Bias
The ISL6559 uses cost and space-saving rDS(ON) sensing • Precision CORE Voltage Regulation
for channel current balance, active voltage positioning, and - ± 1% System Accuracy Over Temperature
over-current protection. Output voltage is monitored by an - Differential Remote Output Voltage Sensing
internal differential remote sense amplifier. A high-bandwidth - Programmable Reference Offset
error amplifier drives the output voltage to match the • Microprocessor Voltage Identification Input
programmed 5-bit DAC reference voltage. The resulting - 5-Bit VID Input
compensation signal guides the creation of pulse width
- 0.800V to 1.550V in 25mV Steps
modulated (PWM) signals to control companion Intersil
- Dynamic VID Technology
MOSFET drivers. The OFS pin allows direct offset of the
• Programmable Droop Voltage
DAC voltage from 0V to 50mV using a single external
resistor. The entire system is trimmed to ensure a system • Fast Transient Recovery Time
accuracy of ± 1% over temperature. • Over Current Protection
• Digital Soft Start
Outstanding features of this controller IC include
• Threshold Sensitive Enable Input
Dynamic VIDTM technology allowing seamless on-the-fly VID
• High Ripple Frequency (160kHz to 4MHz)
changing without the need of any external components.
• QFN Package:
Output voltage “droop” or active voltage positioning is
optional. When employed, it allows the reduction in size and - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat
No Leads - Package Outline
cost of the output capacitors required to support load
transients. A threshold-sensitive enable input allows the use - Near Chip Scale Package footprint, which improves PCB
efficiency and has a thinner profile
of an external resistor divider for start-up coordination with
Intersil MOSFET drivers or any other devices powered from Applications
a separate supply.
• AMD Hammer Family Processor Voltage Regulator
Superior over-voltage protection is achieved by gating on the • Low Output Voltage, High Current DC-DC Converters
lower MOSFET of all phases to crowbar the output voltage. • Voltage Regulator Modules
An optional second crowbar on VIN, formed with an external
MOSFET or SCR gated by the OVP pin, is triggered when
Pinouts
ISL6559CB (28 LEAD SOIC) ISL6559CR (32 LEAD QFN)
an over-voltage condition is detected. Under-voltage
TOP VIEW TOP VIEW
conditions are detected, but PWM operation is not disrupted.
PGOOD
FS/DIS

Over-current conditions cause a hiccup-mode response as GND 1 28 EN

VID3

VID4

GND
OVP
NC

EN

the controller repeatedly tries to restart. After a set number OVP 2 27 FS/DIS

of failed startup attempts, the controller latches off. A power VID4 3 26 PGOOD 32 31 30 29 28 27 26 25
VID3 4 25 PWM4 VID2 1 24 PWM4
good logic signal indicates when the converter output is
VID2 5 24 ISEN4 VID1 2 23 ISEN4
between the UV and OV thresholds. VID1 6 23 ISEN1 VID0 3 22 ISEN1
VID0 7 22 PWM1 NC 4 21 PWM1
Ordering Information OFS 8 21 PWM2 OFS 5 20 PWM2
COMP 9 20 GND
PART NUMBER TEMP. (oC) PACKAGE PKG. DWG. # COMP 6 19 GND
FB 10 19 ISEN2 FB 7 18 ISEN2
ISL6559CB 0 to 70 28 Lead SOIC M28.3 IOUT 11 18 ISEN3
NC 8 17 ISEN3
VDIFF 12 17 PWM3 9 10 11 12 13 14 15 16
ISL6559CB-T 28 Lead SOIC Tape and Reel
VCC

16 VCC
IOUT

GND
GND

VSEN 13
VSEN
VDIFF

RGND

PWM3

ISL6559CR 0 to 70 32 Lead QFN L32.5x5 RGND 14 15 GND

ISL6559CR-T 32 Lead QFN 5x5 Tape and Reel NC = NO CONNECT

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved.
Dynamic VID is a trademark of Intersil Americas Inc. All other trademarks mentioned are the property of their respective owners.
 ISL6559

Block Diagram
PGOOD VCC EN FS/DIS

1.23V

VID4 OSCILLATOR
6V
AND
VID3 SAWTOOTH
DYNAMIC POR
AND
VID2 VID
SOFT START
DAC
VID1 UV
+

VID0 350mV +
PWM1
-
+
-
+ PWM2
E/A
FB
-
+
+ PWM3
COMP
-
+
+ PWM4
OFS x 0.1

100µA -
+
OVP
VDIFF
OV

2.2V I1
VSEN
90µA ISEN1
DIFF
OC
RGND
+ I2
CURRENT ISEN2
+ SENSE
AVERAGE
IOUT 1/N &
+ I3 PHASE
DETECT ISEN3
+

I4
ISEN4

N PHASES

GND

2
 ISL6559

Typical Application - 3 Phase Converter

+12V
+12V
BOOT
PVCC
UGATE

VCC
PHASE

DRIVER
HIP6601B
LGATE RISEN1
PWM GND
+12V

300Ω

ISL6559
VSEN VCC VOUT
+12V
RGND PWM4
+12V
BOOT
VDIFF PVCC
ISEN4 NC UGATE
RFB
FB VCC
PWM1 PHASE
CC
IOUT DRIVER
RC ISEN1 HIP6601B
LGATE RISEN2
COMP
PWM GND
PWM2
OFS

ISEN2
ROFS
FS/DIS
PWM3
RT

ISEN3
+12V

VID4 +12V
BOOT
VID3 PVCC
UGATE
VID2
VCC
VID1 PHASE
VID0
DRIVER
PGOOD HIP6601B
LGATE RISEN3
OVP
PWM GND
GND

3
 ISL6559

Absolute Maximum Ratings Thermal Information

Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Thermal Resistance θJA (oC/W) θJC (oC/W)
Input, Output, or I/O Voltage. . . . . . . . . . . GND -0.3V to VCC + 0.3V SOIC Package (Note 1) . . . . . . . . . . . . 60 N/A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class TBD QFN Package (Note 2) . . . . . . . . . . . . 33 4
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Operating Conditions Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5% Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 125oC

CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device
at these or any other conditions above those indicated in the operational section of this specification is not implied.

NOTES:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. θJC, the
“case temp” is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.

Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC. Unless Otherwise Specified.

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

VCC SUPPLY CURRENT

Nominal Supply VCC = 5VDC; EN = 5VDC; RT = 100 kΩ ±1% 8.0 10.8 14.0 mA

Shutdown Supply VCC = 5VDC; EN = 0VDC; RT = 100 kΩ ±1% 8.0 10.3 13.0 mA
SHUNT REGULATOR

VCC Voltage VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ 5.63 5.8 5.97 V

VCC Sink Current VCC tied to 12VDC thru 300Ω resistor, RT = 100kΩ 15 20 25 mA

POWER-ON RESET AND ENABLE

POR Threshold VCC Rising 4.25 4.35 4.50 V

VCC Falling 3.75 3.85 4.00 V

ENABLE Threshold EN Rising 1.205 1.23 1.255 V

Hysteresis 86 92 98 mV

REFERENCE VOLTAGE AND DAC

Reference Voltage 0.792 0.8 0.808 V

System Accuracy (Note 3) -1 - 1 %VID

VID on Fly Step Size RT = 100kΩ - 25 - mV

VID Pull Up - -20 - µA

VID Input Low Level - - 0.8 V

VID Input High Level 2.0 - - V

PIN-ADJUSTABLE OFFSET
OFS Current - 100 - µA

Offset Accuracy ROFS = 5.00kΩ ±1% 47.0 50.0 53.0 mV

OSCILLATOR
Accuracy -10 - 10 %

Adjustment Range 0.08 - 1.0 MHz

Disable Voltage IFS/DIS = 1mA 0.8 1.0 1.2 V

Sawtooth Amplitude - 1.37 - V

Max Duty Cycle - 75 - %

4
 ISL6559

Electrical Specifications Operating Conditions: VCC = 5V, TA = 0oC to 70oC. Unless Otherwise Specified. (Continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITS

ERROR AMPLIFIER

Open-Loop Gain RL = 10kΩ to ground - 72 - dB

Open-Loop Bandwidth CL = 100pF, RL = 10kΩ to ground - 18 - MHz

Slew Rate CL = 100pF, Load = ±400mA - 7.1 11 V/µs

Maximum Output Voltage RL = 10kΩ to ground 3.6 4.5 - V

Source Current 3.0 7.0 9.0 mA

Sink Current 1.6 3.0 5.4 mA

REMOTE-SENSE AMPLIFIER

Input Impedance - 80 - kΩ

Bandwidth - 20 - MHz

Slew Rate - 6 - V/µs

SENSE CURRENT
IOUT Accuracy ISEN1 = ISEN2 = ISEN3 = ISEN4 = 50µA -5 - 5 %

ISEN Offset Voltage - 6 - mV

Over-Current Trip Level 72 90 108 µA

POWER GOOD AND PROTECTION MONITORS

PGOOD Low Voltage IPGOOD = 4mA - - 0.4 V

Under-Voltage Offset From VID VSEN Falling 320 350 420 mV

Over-Voltage Threshold VSEN Rising 2.08 2.13 2.20 V

OVP Voltage IOVP = 100mA, VCC = 5V 2.2 3.28 4.0 V

NOTE:
3. These parts are designed and adjusted for accuracy within the system tolerance

Functional Pin Description this pin to the gate of an SCR or MOSFET tied across VIN
and ground to prevent damage to a load device.
ISL6559CB (28 LEAD SOIC) ISL6559CR (32 LEAD QFN)
TOP VIEW TOP VIEW
VID4, VID3, VID2, VID1, VID0
PGOOD
FS/DIS

The state of these five inputs program the internal DAC,

VID3

VID4

GND
OVP

GND 1 28 EN
NC

EN

OVP 2 27 FS/DIS which provides the reference voltage for output regulation.
32 31 30 29 28 27 26 25
VID4 3 26 PGOOD
VID2 1 24 PWM4 Connect these pins to either open-drain or active pull-up
VID3 4 25 PWM4
VID1 2 23 ISEN4 type outputs. Pulling these pins above 2.9V can cause a
VID2 5 24 ISEN4
23 ISEN1
VID0 3 22 ISEN1 reference offset inaccuracy.
VID1 6
NC 4 21 PWM1
VID0 7 22 PWM1
OFS 5 20 PWM2
OFS
OFS 8 21 PWM2
COMP 9 20 GND COMP 6 19 GND Connecting a resistor between this pin and ground creates a
FB 10 19 ISEN2 FB 7 18 ISEN2 positive offset voltage which is added to the DAC voltage,
IOUT 11 18 ISEN3 NC 8 17 ISEN3 allowing easy implementation of load-line regulation. For no
9 10 11 12 13 14 15 16
VDIFF 12 17 PWM3 offset, simply tie this pin to ground.
IOUT

GND
GND
VCC
VSEN
VDIFF

RGND

PWM3

VSEN 13 16 VCC
RGND 14 15 GND FB and COMP
NC = NO CONNECT The internal error amplifier inverting input and output
respectively. Connect the external R-C feedback
GND
compensation network of the regulator to these pins.
Bias and reference ground for the IC.
IOUT
OVP
The current carried out of this pin is proportional to output
Over-voltage protection pin. This pin pulls to VCC and is current and can be used to incorporate output voltage droop
latched when an over-voltage condition is detected. Connect

5
 ISL6559

and/or load sharing. The scale factor is set by the ratio of the MOSFET drivers. If this function is not required, simply tie
ISEN resistors and the lower MOSFET rDS(ON). If droop is this pin to VCC.
desired, connect this pin to FB. When not used for droop or
Multi-Phase Power Conversion
load sharing, simply leave this pin open.
Microprocessor load current profiles have changed to the
VSEN, RGND, VDIFF point where the multi-phase power conversion advantage is
VSEN and RGND are the inputs to the differential remote- pronounced. The technical challenges associated with
sense amplifier. Connect these pins to the sense points of producing a single-phase converter which is both cost-
the remote load. Connect an appropriately sized feedback effective and thermally viable have forced a change to the
resistor, RFB, between VDIFF and FB. cost-saving approach of multi-phase. The ISL6559 controller
helps reduce the complexity of implementation by integrating
VCC
vital functions and requiring minimal output components.
Supplies all the power necessary to operate the chip. The IC The block diagram in Figure 1 provides a top level view of
starts to operate when the voltage on this pin exceeds the multi-phase power conversion using the ISL6559 controller.
rising POR threshold and shuts down when the voltage on
this pin drops below the falling POR threshold. Connect this Interleaving
pin directly to a +5V supply or through a series 300Ω resistor The switching of each channel in a multi-phase converter is
to a +12V supply. timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
ISEN1, ISEN2, ISEN3, ISEN4
cycle after the previous channel and 1/3 cycle before the
Current sense inputs. A resistor connected between these following channel. As a result, the three-phase converter has
pins and their respective phase node sets a current a combined ripple frequency three times greater than the
proportional to the current in the lower MOSFET during it’s ripple frequency of any one phase. In addition, the peak-to-
conduction interval. This current is used as a reference for peak amplitude of the combined inductor currents is reduced
channel balancing, load sharing, protection, and load-line in proportion to the number of phases (Equations 1 and 2).
regulation. Inactive channels should have their respective Increased ripple frequency and lower ripple amplitude mean
sense inputs left open. that the designer can use less per-channel inductance and
PWM1, PWM2, PWM3, PWM4 lower total output capacitance for any performance
specification.
Pulse-width modulating outputs. Connect these pins to the
individual HIP660x driver PWM input pins. These logic
outputs command the driver IC(s) in switching the half-
bridge configuration of [Link] number of active IL1 + IL2 + IL3, 7A/DIV
channels is determined by the state of PWM3 and PWM4. If
PWM3 is tied to VCC, this indicates to the controller that two IL3, 7A/DIV
channel operation is desired. In this case, PWM 4 should be
left open or tied to VCC. Shorting PWM4 to VCC indicates PWM3, 5V/DIV
that three channel operation is desired. IL2, 7A/DIV

PGOOD
PWM2, 5V/DIV
Power good is an open-drain logic output that changes to a
logic low when the voltage at VDIFF is 350mV below the VID IL1, 7A/DIV
setting or above 2.2V.
PWM1, 5V/DIV
FS/DIS
1µs/DIV
A dual function pin for setting the switching frequency and
disabling the controller. Place a resistor from this pin to FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
ground to set the switching frequency between 80kHz and
1MHz. Pulling this pin below 0.8V disables the controller. Figure 1 illustrates the multiplicative effect on output ripple
EN frequency. The three channel currents (IL1, IL2, and IL3),
combine to form the AC ripple current and the DC load
Threshold sensitive enable input of the controller. Transition
current. The ripple component has three times the ripple
this pin above 1.23V (typical enable threshold) to initiate a
frequency of each individual channel current. Each PWM
soft-start cycle. Pull this pin below 1.14V, taking into account
pulse is terminated 1/3 of a cycle, or 1.33µs, after the PWM
the enable hysteresis, to disable the controller once in
pulse of the previous phase. The peak-to-peak current
operation. Connect a resistor divider to this pin to set the
waveforms for each phase is about 7A, and the dc
power-on voltage level for proper coordination with Intersil
components of the inductor currents combine to feed the load.

6
 ISL6559

To understand the reduction of ripple current amplitude in single-phase converter must use an input capacitor bank
the multi-phase circuit, examine the equation representing with twice the RMS current capacity as the equivalent three-
an individual channel’s peak-to-peak inductor current. phase converter.
( V IN – V OUT ) V OUT Figures 15, 16 and 17 in the section entitled Input Capacitor
I PP = -----------------------------------------------------
- (EQ. 1)
L fS V Selection can be used to determine the input-capacitor RMS
IN
current based on load current, duty cycle, and the number of
In Equation 1, VIN and VOUT are the input and output channels. They are provided as aids in determining the
voltages respectively, L is the single-channel inductor value, optimal input capacitor solution. Figure 18 shows the single
and fS is the switching frequency. phase input-capacitor RMS current for comparison.
The output capacitors conduct the ripple component of the PWM Operation
inductor current. In the case of multi-phase converters, the
The timing of each converter leg is set by the number of
capacitor current is the sum of the ripple currents from each
of the individual channels. Compare Equation 1 to the active channels. The default channel setting for the ISL6559
expression for the peak-to-peak current after the summation is four. One switching cycle is defined as the time between
of N symmetrically phase-shifted inductor currents in Equa- PWM1 pulse termination signals. The pulse termination
tion 2. Peak-to-peak ripple current decreases by an amount signal is an internally generated clock signal which triggers
proportional to the number of channels. Output-voltage ripple the falling edge of PWM1. The cycle time of the pulse
is a function of capacitance, capacitor equivalent series resis- termination signal is the inverse of the switching frequency
tance (ESR), and inductor ripple current. Reducing the induc- set by the resistor between the FS/DIS pin and ground. Each
tor ripple current allows the designer to use fewer or less cycle begins when the clock signal commands the channel-1
costly output capacitors. PWM output to go low. The PWM1 transition signals the
( V IN – N V OUT ) V OUT channel-1 MOSFET driver to turn off the channel-1 upper
I C, PP = -----------------------------------------------------------
- (EQ. 2)
L fS V MOSFET and turn on the channel-1 synchronous MOSFET.
IN
In the default channel configuration, the PWM2 pulse
Another benefit of interleaving is to reduce input ripple terminates 1/4 of a cycle after PWM1. The PWM 3 output
current. Input capacitance is determined in part by the follows another 1/4 of a cycle after PWM2. PWM4 terminates
maximum input ripple current. Multi-phase topologies can another 1/4 of a cycle after PWM3.
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input If PWM3 is connected to VCC, then two channel operation is
capacitance. The example in Figure 2 illustrates input selected and the PWM2 pulse terminates 1/2 of a cycle later.
currents from a three-phase converter combining to reduce Connecting PWM4 to VCC selects three channel operation
the total input ripple current. and the pulse-termination times are spaced in 1/3 cycle
increments.
INPUT-CAPACITOR CURRENT, 10A/DIV
Once a PWM signal transitions low, it is held low for a
minimum of 1/4 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
CHANNEL 3 expires, the PWM output is enabled. The PWM output state
INPUT CURRENT
10A/DIV is driven by the position of the error amplifier output signal,
VCOMP, minus the current correction signal relative to the
CHANNEL 2 sawtooth ramp as illustrated in Figure 1. When the modified
INPUT CURRENT VCOMP voltage crosses the sawtooth ramp, the PWM output
10A/DIV
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
CHANNEL 1
INPUT CURRENT MOSFET and turns on the upper MOSFET. The PWM signal
10A/DIV will remain high until the pulse termination signal marks the
1µs/DIV beginning of the next cycle by triggering the PWM signal low.
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT- Current Sensing
CAPACITOR RMS CURRENT FOR 3-PHASE
CONVERTER
During the forced off time following a PWM transition low,
the controller senses channel load current by sampling the
The converter depicted in Figure 2 delivers 36A to a 1.5V voltage across the lower MOSFET rDS(ON), see Figure 3. A
load from a 12V input. The RMS input capacitor current is ground-referenced amplifier, internal to the ISL6559,
5.9A. Compare this to a single-phase converter also connects to the PHASE node through a resistor, RISEN. The
stepping down 12V to 1.5V at 36A. The single-phase voltage across RISEN is equivalent to the voltage drop
converter has 11.9A RMS input capacitor current. The across the RDS(ON) of the lower MOSFET while it is

7
 ISL6559

VIN provides a measure of the total load current demand on the

r DS ( ON )
converter and the appropriate level of channel current. Using
I CHANNEL N
SEN = I L -------------------------
R
- UPPER MOSFET Figures 3 and 4, the average current is defined as
In ISEN
I 1 + I 2 + …I N
IL I AVG = ----------------------------------
N (EQ. 4)
SAMPLE
&
HOLD ISEN(n) I OUT r DS ( ON )
- I AVG = ------------
- ----------------------
N R ISEN
RISEN
-
+
I r where N is the number of active channels and IOUT is the
L DS ( ON )
+ total load current.
CHANNEL N
LOWER MOSFET
The average current is then subtracted from the individual
ISL6559 INTERNAL CIRCUIT EXTERNAL CIRCUIT channel sample currents. The resulting error current, IER, is
FIGURE 3. INTERNAL AND EXTERNAL CURRENT-SENSING
then filtered before it adjusts VCOMP. The modified VCOMP
CIRCUITRY signal is compared to a sawtooth ramp signal and produces
a pulse width which corrects for any unbalance and drives
conducting. The resulting current into the ISEN pin is
the error current toward zero. Figure 4 illustrates Intersil’s
proportional to the channel current, IL. The ISEN current is
patented current-balance method as implemented on
then sampled and held after sufficient settling time every
channel-1 of a multi-phase converter.
switching cycle. The sampled current, In, is used for
channel-current balance, load-line regulation, overcurrent Two considerations designers face are MOSFET selection
protection, and module current sharing. From Figure 3, the and inductor design. Both are significantly improved when
following equation for In is derived channel currents track at any load level. The need for
r DS ( ON ) complex drive schemes for multiple MOSFETs, exotic
I n = I L ---------------------- (EQ. 3)
R ISEN
magnetic materials, and expensive heat sinks is avoided.
Resulting in a cost-effective and easy to implement solution
where IL is the channel current. relative to single-phase conversion. Channel-current
balance insures the thermal advantage of multi-phase
If RDS(ON) sensing is not desired, an independent current-
conversion is realized. Heat dissipation is spread over
sense resistor in series with the lower MOSFET source can
multiple channels and a greater area than single phase
serve as a sense element. The circuitry shown in Figure 3
approaches.
represents channel n of an N-channel converter. This
circuitry is repeated for each channel in the converter, but In some circumstances, it may be necessary to deliberately
may not be active depending upon the status of the PWM3 design some channel-current unbalance into the system. In
and PWM4 pins as described in the previous section. a highly compact design, one or two channels may be able
to cool more effectively than the other(s) due to nearby air
Channel-Current Balance
flow or heat sinking components. The other channel(s) may
The sampled current, In, from each active channel is used to have more difficulty cooling with comparatively less air flow
gauge both overall load current and the relative channel and heat sinking. The hotter channels may also be located
current carried in each leg of the converter. The individual close to other heat-generating components tending to drive
sample currents are summed and divided by the number of their temperature even higher. In these cases, the proper
active channels. The resulting average current, IAVG, selection of the current sense resistors (RISEN in Figure 3)
+ introduces channel current unbalance into the system.
VCOMP
+
PWM1 Increasing the value of RISEN in the cooler channels and
- - decreasing it in the hotter channels moves all channels into
SAWTOOTH SIGNAL
thermal balance at the expense of current balance.
f(jω)

I4 * Voltage Regulation
IER
IAVG The output of the error amplifier, VCOMP, is compared to the
÷N Σ I3 * sawtooth waveform to modulate the pulse width of the PWM
-
+ signals. The PWM signals control the timing of the Intersil
I2
MOSFET drivers and regulate the converter output to the
specified reference voltage. Three distinct inputs to the error
I1
amplifier determine the voltage level of VCOMP. The internal
NOTE: *CHANNELS 3 and 4 are OPTIONAL. and external circuitry which control voltage regulation is
FIGURE 4. CHANNEL-1 PWM FUNCTION AND CURRENT- illustrated in Figure 5.
BALANCE ADJUSTMENT

8
 ISL6559

Most multi-phase controllers simply have the output voltage feeds out the OFS pin into a user selected external resistor
fed back to the inverting input of the error amplifier through a to ground. The resulting voltage across the resistor, VOFS, is
resistor. The ISL6559 features an internal differential internally divided down by ten to create the offset voltage.
remote-sense amplifier in the feedback path. The amplifier This method of offsetting the DAC voltage is more accurate
removes the voltage error encountered when measuring the than external methods of level-shifting the FB pin.
output voltage relative to the local controller ground
TABLE 1. VOLTAGE IDENTIFICATION CODES
reference point, resulting in a more accurate means of
sensing output voltage. Connect the microprocessor sense VID4 VID3 VID2 VID1 VID0 DAC
pins to the non-inverting input, VSEN, and inverting input, 0 0 0 0 0 1.550
RGND, of the remote-sense amplifier. The remote-sense 0 0 0 0 1 1.525
amplifier output, VDIFF, is then tied through an external
0 0 0 1 0 1.500
resistor to the inverting input of the error amplifier.
0 0 0 1 1 1.475
A digital to analog converter (DAC) generates a reference
voltage based on the state of logic signals at pins VID4 0 0 1 0 0 1.450
through VID0. The DAC decodes the a 5-bit logic signal 0 0 1 0 1 1.425
(VID) into one of the discrete voltages shown in Table 1. 0 0 1 1 0 1.400
Each VID input offers a 20µA pull-up to an internal 2.5V
0 0 1 1 1 1.375
source for use with open-drain outputs. External pull-up
resistors or active-high output stages can augment the pull- 0 1 0 0 0 1.350
up current sources, but a slight accuracy error can occur if 0 1 0 0 1 1.325
they are pulled above 2.9V. The DAC-selected reference
0 1 0 1 0 1.300
voltage is connected to the non-inverting input of the error
amplifier. 0 1 0 1 1 1.275
0 1 1 0 0 1.250
The ISL6559 features a second non-inverting input to the
error amplifier which allows the user to directly offset the 0 1 1 0 1 1.225
DAC reference voltage in the positive direction only. The 0 1 1 1 0 1.200
offset voltage is created by an internal current source which
0 1 1 1 1 1.175
1 0 0 0 0 1.150
EXTERNAL CIRCUIT ISL6559 INTERNAL CIRCUIT
1 0 0 0 1 1.125
RC CC
COMP 1 0 0 1 0 1.100
ERROR AMPLIFIER
1 0 0 1 1 1.075
FB
- 1 0 1 0 0 1.050
+ VCOMP 1 0 1 0 1 1.025
IAVG
+ IOUT +
RFB VDROOP 1 0 1 1 0 1.000
- 1 0 1 1 1 0.975
REFERENCE
VOLTAGE
1 1 0 0 0 0.950
VDIFF
1 1 0 0 1 0.925

VSEN 1 1 0 1 0 0.900
VOUT
REMOTE + 1 1 0 1 1 0.875
SENSE
POINTS RGND - 1 1 1 0 0 0.850
GND
DIFFERENTIAL 1 1 1 0 1 0.825
REMOTE-SENSE
AMPLIFIER 1 1 1 1 0 0.800
1 1 1 1 1 Shutdown
OFS
1/10
+ OFFSET
ROFS VOFS VOLTAGE The integrating compensation network shown in Figure 5
- 100µA assures that the steady-state error in the output voltage is
limited to the error in the reference voltage (output of the
DAC) plus offset errors in the OFS current source, remote-
FIGURE 5. OUTPUT-VOLTAGE AND LOAD-LINE sense and error amplifiers. Intersil specifies the guaranteed
REGULATION tolerance of the ISL6559 to include all variations in current

9
 ISL6559

sources, amplifiers and the reference so that the output DYNAMIC VID
voltage remains within the specified system tolerance of Next generation microprocessors can change VID inputs at
± 1% over temperature. any time while the regulator is in operation. The power
LOAD-LINE REGULATION management solution is required to monitor the DAC inputs
and respond to VID voltage transitions or ‘on-the-fly’ VID
Microprocessor load current demands change from near no-
changes, in a controlled manner. Supervising the safe output
load to full load often during operation. The resulting sizable
voltage transition within the DAC range of the processor
transient current slew rate causes an output voltage spike
without discontinuity or disruption.
since the converter is not able to respond fast enough to the
rapidly changing current demands. The magnitude of the The ISL6559 checks the five VID inputs at the beginning of
spike is dictated by the ESR and ESL of the output each channel-1 switching cycle. If the VID code has
capacitors selected. In order to drive the cost of the output changed, the controller waits one complete switching cycle
capacitor solution down, one commonly accepted approach to validate the new code. If the VID code is stable for this
is active voltage positioning. By adding a well controlled entire switching cycle, then the controller will begin
output impedance, the output voltage can effectively be level executing the output voltage change. The controller begins
shifted in a direction which works against the voltage spike. incrementing the reference voltage by making 25mV steps
every two switching cycles until it reaches the new VID code.
The average current of all the active channels, IAVG, flows
out IOUT, see Figure 5. IOUT is connected to FB through a The total time required for a VID change, tDV, is dependent
load-line regulation resistor, RFB. The resulting voltage drop on the switching frequency (fS), the size of the change
across RFB is proportional to the output current, effectively (∆VID), and the time before the next switching cycle begins.
creating an output voltage droop with a steady-state value Since the ISL6559 recognizes VID-code changes only at the
defined as beginning of switching cycles, up to one full cycle may pass
before a VID change registers. This is followed by a one-
V DROOP = I AVG R FB (EQ. 5) cycle wait before the output voltage begins to change. The
one-cycle uncertainty in Equation 8 is due to the possibility
that the VID code change may occur up to one full cycle
In most cases, each channel uses the same RISEN value to before being recognized.
sense current. A more complete expression for VDROOP is
1 ∆VID 1 2 ∆VID
derived by combining equations 3 and 4. ------------------ – 1 < t DV ≤ -----  ------------------
-----  2 (EQ. 8)
f S  0.025 f S 0.025
I OUT r DS ( ON )
V DROOP = ------------
- ---------------------- R FB (EQ. 6)
N R ISEN The time required for a converter running with fS = 500kHz
to make a 1.2V to 1.4V reference-voltage change is between
Droop is an optional feature of the ISL6559. If active voltage 30µs and 32µs as calculated using Equation 8. This example
positioning is not required, simply leave the IOUT pin open. is also illustrated in Figure 7.

REFERENCE OFFSET VID, 5V/DIV

01110 00110
Typical microprocessor tolerance windows are centered
VID CHANGE OCCURS
around a nominal DAC set point. Implementing a load-line ANYWHERE HERE
would require offsetting the output voltage above this
nominal DAC set point. Centering the load-line within the
static specification window. The ISL6559 features an internal VREF, 100mV/DIV
100µA current source which feeds out the OFS pin. Placing 1.2V
a resistor from OFS and ground allows the user to set the
amount of positive offset desired directly to the reference
VOUT, 100mV/DIV
voltage. The voltage developed across the OFS resistor, 1.2V
ROFS, is divided down internally by a factor of 10 and
directly counters the DAC voltage at the error amplifier non-
inverting input. Select the resistor value based on the
voltage offset desired, VOFS, using Equation 6. 5µs/DIV

V OFS ⋅ 10 FIGURE 6. DYNAMIC-VID WAVEFORMS FOR 500KHZ

R OFS = --------------------------
- (EQ. 7) ISL6559 BASED MULTI-PHASE BUCK
100µA
CONVERTER

10
 ISL6559

Operation Initialization The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shutdown
Before converter operation is initialized, proper conditions
mode after receiving this code and will start up upon
must exist on the enable and disable inputs. Once these
receiving any other code. This code is not intended as a
conditions are met, the controller begins a soft-start interval.
means of enabling the controller when a load is present.
Once the output voltage is within the proper window of
operation, the PGOOD output changes state to update an To enable the controller, VCC must be greater than the POR
external system monitor. threshold; the voltage on EN must be greater than 1.23V;
FS/DIS must not be grounded; and VID cannot be equal to
Enable and Disable
11111. Once these conditions are true, the controller
The PWM outputs are held in a high-impedance state to immediately initiates a soft-start sequence.
assure the drivers remain off while in shutdown mode. Four
separate input conditions must be met before the ISL6559 is Soft-Start
released from shutdown mode. The soft-start time, tSS, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
First, the bias voltage applied at VCC must reach the internal
example, a converter switching at 250kHz per phase has a
power-on reset (POR) circuit rising threshold. Once this
soft-start time of
threshold is met, proper operation of all aspects of the
ISL6559 is guaranteed. Hysteresis between the rising and 2048 (EQ. 9)
T SS = ------------- = 8.3ms
falling thresholds insures that once enabled, the ISL6559 will f SW
not inadvertently turn off unless the bias voltage drops
During the soft-start interval, the soft-start voltage, VRAMP ,
substantially. See Electrical Specifications for specifics on
increases linearly from zero to 140% of the programmed
POR rising and falling thresholds.
DAC voltage. At the same time a current source, IRAMP , is
ISL6559 INTERNAL CIRCUIT EXTERNAL CIRCUIT
decreasing from 160µA down to zero. These signals are
connected as shown in Figure 8 (IOUT may or may not be
+5V connected to FB depending on the particular application).
+12V
VCC
EXTERNAL CIRCUIT ISL6559 INTERNAL CIRCUIT

ENABLE 10.7kΩ RC CC
COMPARATOR COMP

EN
+ ERROR AMPLIFIER
POR
FB
CIRCUIT -
-
1.40kΩ
+ VCOMP
RFB IOUT
OV LATCH 1.23V (± 2%)
REFERENCE
SIGNAL VOLTAGE
VDIFF IRAMP

FIGURE 7. POWER SEQUENCING USING THRESHOLD- VRAMP

SENSITIVE ENABLE (EN) FUNCTION IAVG

IDEAL DIODES
Second, the ISL6559 features an enable input (EN) for
power sequencing between the controller bias voltage and FIGURE 8. RAMP CURRENT AND VOLTAGE FOR
another voltage rail. The enable comparator holds the REGULATING SOFT-START SLOPE
AND DURATION
ISL6559 in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of
The ideal diodes in Figure 8 assure that the controller tries to
hysteresis to prevent bounce. It is important that the driver
regulate its output to the lower of either the reference voltage
ICs reach their POR level before the ISL6559 becomes
or VRAMP . Since IRAMP creates an initial offset across RFB of
enabled. The schematic in Figure 7 demonstrates
(RFB x 160µA), the first PWM pulse will not be seen until
sequencing the ISL6559 with the HIP660X family of Intersil
VRAMP is greater than the RFB IRAMP offset. This produces a
MOSFET drivers which require 12V bias.
delay after the ISL6559 enables before the output voltage
Third, the frequency select\disable input (FS/DIS) will starts moving. For example, if VID = 1.5V, RFB = 1kΩ and
shutdown the converter when pulled to ground. Under this
condition, the internal oscillator is disabled. The oscillator
resumes operation upon release of FS/DIS and a soft-start
sequence is initiated.

11
 ISL6559

TSS = 8.3ms, the delay time can be expressed using Equation

10. PGOOD
T SS
t DELAY = --------------------------------------------------
- = 560µs (EQ. 10)
1.4 ( VID)
1 + ---------------------------------------- -
R FB 160 × 10 – 6

UV
Following the delay, the soft start ramps linearly until VRAMP

+
90µA

-
POR -
reaches VID. For the system described above, this first + OC
350mV CIRCUIT
linear ramp will continue for approximately +
- IAVG
DAC
T SS
- – t DELAY
t RAMP1 = ---------- REFERENCE
1.4 (EQ. 11)

= 5.27ms VDIFF +
OV OVP
The final portion of the soft-start sequence is the time -
remaining after VRAMP reaches VID and before IRAMP gets to
zero. This is also characterized by a slight change in the slope
2.2V
of the output voltage ramp which, for the current example,
exists for a time of FIGURE 10. POWER GOOD AND PROTECTION CIRCUITRY
t RAMP2 = T SS – t RAMP1 – t DELAY
(EQ. 12) Power Good Signal
= 2.34ms The power good pin (PGOOD) is an open-drain logic output
which indicates that the converter is operating properly and
This behavior is seen in the example in Figure 9 of a converter
the output voltage is within a set window. The under-voltage
switching at 500kHz. For this converter, RFB is set to 2.67kΩ
(UV) and over-voltage (OV) comparators create the output
leading to TSS = 4.0ms, tDELAY = 700ns, tRAMP1 = 2.23ms,
voltage window. The controller also takes advantage of
and tRAMP2 = 1.17ms.
current feedback to detect output over-current (OC)
conditions. PGOOD pulls low during shutdown and releases
high during soft-start once the output voltage exceeds the
VOUT, 500mV/DIV
UV threshold. Once high, PGOOD will only transition low
when the controller is disabled or a fault condition is
detected. It will return high under certain circumstances once
a fault clears.

Under-Voltage Protection
The voltage on VDIFF is internally offset by 350mV before it
is compared with the DAC reference voltage. By positively
EN, 5V/DIV offsetting the output voltage, an UV threshold is created
which moves relative to the VID code. During soft-start, the
slow rising output voltage eventually exceeds the UV
threshold. Assuming the POR leg of the PGOOD NOR gate
has not detected an OC fault, the PGOOD signal will go
1ms/DIV high.
tDELAY tRAMP1 tRAMP2

FIGURE 9. SOFT-START WAVEFORMS FOR ISL6559 BASED If a fault condition arises during operation and the output
MULTI-PHASE BUCK CONVERTER voltage drops below the UV threshold, PGOOD will
NOTE: Switching frequency 500kHz and RFB = 2.67kΩ
immediately pull low, but converter operation will continue.
PGOOD will return high once the output voltage surpasses
Fault Monitoring and Protection
the UV threshold.
The ISL6559 actively monitors voltage and current feedback
to detect fault conditions. Fault monitors trigger protective If the ISL6559 is disabled during operation, the PGOOD
measures to prevent damage to a microprocessor load. One signal will not pull low until the output voltage decays below
common power good indication signal is provided for linking the UV threshold.
to external system monitors. The schematic in Figure 10 Over-Voltage Protection
outlines the interaction between the fault monitors and the
When the output of the differential amplifier (VDIFF) reaches
power good signal.
2.2V, PGOOD immediately goes low indicating a fault. Two

12
 ISL6559

protective actions are taken by the ISL6559 to protect the During the soft-start interval, the over-current protection
microprocessor load. circuitry remains active. As the output voltage ramps up, if
an over-current condition is detected, the ISL6559
First, all PWM outputs are commanded low. Directing the immediately places all PWM signals in a high-impedance
Intersil drivers to turn on the lower MOSFETs; shunting the state. The ISL6559 repeats the 2048-cycle wait period and
output to ground preventing any further increase in output follows with another soft-start attempt, as shown in
voltage. The PWM outputs remain low until VDIFF falls to Figure 11. This hiccup mode of operation repeats up to
the programmed DAC level at which time they go into a high- seven times. On the eighth soft-start attempt, the part
impedance state. The Intersil drivers respond by turning off latches off. Once latched off, the ISL6559 can only be reset
both upper and lower MOSFETs. If the over-voltage when the voltage on EN is brought below 1.23V or VCC is
condition reoccurs, the ISL6559 will again command the brought below the POR falling threshold. Upon completion of
a successful soft-start attempt, operation will continue as
lower MOSFETs to turn on. The ISL6559 will continue to
normal, PGOOD will return high, and the OC latch counter is
protect the load in this fashion as long as the over-voltage
reset.
repeats.
During VID-on-the-fly transitions, the OC comparator output
Second, the OVP pin pulls to VCC and can deliver 100mA is blanked. The quality and mix of output capacitors used in
into the gate of either a MOSFET or SCR placed across the different applications leads to a wide output capacitance
input voltage (VIN) and VOUT. Turning on the MOSFET or range. Depending upon the magnitude and direction of the
SCR collapses the power rail and causes a fuse placed VID change, the change in voltage across the output
further up stream to blow. The fuse must be sized such that capacitors could result in significant current flow. Summing
the MOSFET or SCR will not overheat before the fuse blows. this instantaneous current with the load current already
present could drive the average current above the reference
Once an over-voltage condition is detected, normal PWM
current level and cause an OC trip during the transition. By
operation ceases and PGOOD remains low until the
blanking the OC comparator during the VID-on-the-fly
ISL6559 is reset. Cycling the voltage on EN below 1.23V or
transition, nuisance tripping is avoided.
the bias to VCC below the POR-falling threshold will reset
the controller.
General Design Guide
Over-Current Protection This design guide is intended to provide a high-level
The ISL6559 takes advantage of the proportionality between explanation of the steps necessary to create a multi-phase
the load current and the average current, IAVG, to detect an power converter. It is assumed that the reader is familiar with
over-current condition. See the Channel-Current Balance many of the basic skills and techniques referenced below. In
section for more detail on how the average current is addition to this guide, Intersil provides complete reference
created. The average current is continually compared with a designs that include schematics, bills of materials, and
constant 90µA reference current. Once the average current example board layouts for all common microprocessor
exceeds the reference current, the comparator triggers the applications.
converter to shutdown. The POR circuit places all PWM
Power Stages
signals in a high-impedance state which commands the
drivers to turn off both upper and lower MOSFETs. PGOOD The first step in designing a multi-phase converter is to
pulls low and the system remains in this state while the determine the number of phases. This determination
controller counts 2048 phase clock [Link] is followed by depends heavily on the cost analysis which in turn depends
a soft-start attempt (see Soft-Start). on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board; whether through-hole components are permitted; and
OUTPUT CURRENT, 20A/DIV the total board space available for power-supply circuitry.
Generally speaking, the most economical solutions are
those where each phase handles between 15 and 20A. All
surface-mount designs will tend toward the lower end of this
0A current range and, if through-hole MOSFETs can be used,
higher per-phase currents are possible. In cases where
OUTPUT VOLTAGE, board space is the limiting constraint, current can be pushed
500mV/DIV as high as 30A per phase, but these designs require heat
sinks and forced air to cool the MOSFETs.

MOSFETS
0V The choice of MOSFETs depends on the current each
5ms/DIV
MOSFET will be required to conduct; the switching frequency;
FIGURE 11. OVERCURRENT BEHAVIOR IN HICCUP MODE

13
 ISL6559

the capability of the MOSFETs to dissipate heat; and the The upper MOSFET begins to conduct and this transition
availability and nature of heat sinking and air flow. occurs over a time t2. In Equation 16, the approximate power
loss is PUP,2.
LOWER MOSFET POWER CALCULATION
The calculation for heat dissipated in the lower MOSFET is  I M I PP  t 2 
P UP, 2 ≈ V IN  -----
- – ---------  ----  f S (EQ. 16)
simple, since virtually all of the heat loss in the lower N 2  2
MOSFET is due to current conducted through the channel
resistance (rDS(ON)). In Equation 13, IM is the maximum A third component involves the lower MOSFET’s reverse-
continuous output current; IPP is the peak-to-peak inductor recovery charge, Qrr. Since the inductor current has fully
current (see Equation 1); d is the duty cycle (VOUT/VIN); and commutated to the upper MOSFET before the lower-
L is the per-channel inductance. MOSFET’s body diode can draw all of Qrr, it is conducted
through the upper MOSFET across VIN. The power
 I M 2 I L, 2PP ( 1 – d ) (EQ. 13)
- ( 1 – d ) + --------------------------------
P L = r DS ( ON )  ----- dissipated as a result is PUP,3 and is approximately
 N 12
P UP,3 = V IN Q rr f S (EQ. 17)
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
Finally, the resistive part of the upper MOSFET’s is given in
dead time when inductor current is flowing through the
Equation 18 as PUP,4.
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at IM, VD(ON); the switching  I M I PP2
2
frequency, fS; and the length of dead times, td1 and td2, at P UP,4 ≈ r DS ( ON )  -----
- d + ---------- (EQ. 18)
 N 12
the beginning and the end of the lower-MOSFET conduction
interval respectively.
In this case, of course, rDS(ON) is the on resistance of the
I M I PP I  upper MOSFET.
P D = V D ( ON ) f S  ----- M I PP t
- t d1 +  -----
(EQ. 14)
 N- + --------
2 N
- – --------- d2
2  The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
Thus the total maximum power dissipated in each lower from Equations 15, 16, 17 and 18. Since the power
MOSFET is approximated by the summation of PL and PD. equations depend on MOSFET parameters, choosing the
UPPER MOSFET POWER CALCULATION correct MOSFETs can be an iterative process that involves
repetitively solving the loss equations for different MOSFETs
In addition to rDS(ON) losses, a large portion of the upper-
and different switching frequencies until converging upon the
MOSFET losses are due to currents conducted across the
best solution.
input voltage (VIN) during switching. Since a substantially
higher portion of the upper-MOSFET losses are dependent Current Sensing
on switching frequency, the power calculation is more The ISEN pins are denoted ISEN1, ISEN2, ISEN3 and
complex. Upper MOSFET losses can be divided into ISEN4. The resistors connected between these pins and
separate components involving the upper-MOSFET their respective phase nodes determine the gains in the
switching times; the lower-MOSFET body-diode reverse- load-line regulation loop and the channel-current balance
recovery charge, Qrr; and the upper MOSFET rDS(ON) loop. Select the values for these resistors based on the room
conduction loss. temperature rDS(ON) of the lower MOSFETs; the full-load
When the upper MOSFET turns off, the lower MOSFET operating current, IFL; and the number of phases, N
does not conduct any portion of the inductor current until the according to Equation 19 (see also Figure 3).
voltage at the phase node falls below ground. Once the r DS ( ON ) I FL
R ISEN = ----------------------
- -------
- (EQ. 19)
lower MOSFET begins conducting, the current in the upper 50 ×10 – 6 N
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 15, In certain circumstances, it may be necessary to adjust the
the required time for this commutation is t1 and the value of one or more of the ISEN resistors. This can arise
approximated associated power loss is PUP,1. when the components of one or more channels are inhibited
from dissipating their heat so that the affected channels run
I M I PP  t 1 
P UP,1 ≈ V IN  ----- -  ----  f (EQ. 15) hotter than desired (see the section entitled Channel-Current
 N- + --------
2  2 S Balance). In these cases, chose new, smaller values of RISEN
for the affected phases. Choose RISEN,2 in proportion to the

14
 ISL6559

desired decrease in temperature rise in order to cause

C2 (OPTIONAL)
proportionally less current to flow in the hotter phase.
∆T
R ISEN ,2 = R ISEN ----------2 (EQ. 20)
∆T 1
CC
RC
COMP
In Equation 20, make sure that ∆T2 is the desired temperature
rise above the ambient temperature, and ∆T1 is the measured
temperature rise above the ambient temperature. While a
FB
single adjustment according to Equation 20 is usually
sufficient, it may occasionally be necessary to adjust RISEN
two or more times to achieve perfect thermal balance

ISL6559
+
between all channels. RFB
IOUT
VDROOP
Load-Line Regulation Resistor -
The load-line regulation resistor is labeled RFB in Figure 5.
VDIFF
Its value depends on the desired full-load droop voltage
(VDROOP in Figure 5). If Equation 19 is used to select each
ISEN resistor, the load-line regulation resistor is as shown
in Equation 21.
V DROOP
R FB = ------------------------
- (EQ. 21)
–6 FIGURE 12. COMPENSATION CONFIGURATION FOR
50 ×10
LOAD-LINE REGULATED ISL6559 CIRCUIT
The feedback resistor, RFB, has already been chosen as
If one or more of the ISEN resistors was adjusted for thermal
outlined in Load-Line Regulation Resistor. Select a target
balance, as in Equation 20, the load-line regulation resistor
bandwidth for the compensated system, f0. The target
should be selected according to Equation 22. Where IFL is
bandwidth must be large enough to assure adequate
the full-load operating current and RISEN(n) is the ISEN
transient performance, but smaller than 1/3 of the per-
resistor connected to the nth ISEN pin.
channel switching frequency. The values of the
V DROOP
R FB = --------------------------------
I FL r DS ( ON ) ∑ RISEN ( n ) (EQ. 22) compensation components depend on the relationships of f0
n to the L-C pole frequency and the ESR zero frequency. For
each of the three cases which follow, there is a separate set
Compensation of equations for the compensation components.
The two opposing goals of compensating the voltage 1
Case 1: ------------------- > f 0
regulator are stability and speed. Depending on whether the 2π LC
regulator employs the optional load-line regulation as
2πf 0 V pp LC
described in Load-Line Regulation, there are two distinct R C = R FB -----------------------------------
-
0.75V IN
methods for achieving these goals.
0.75V IN
COMPENSATING LOAD-LINE REGULATED C C = -----------------------------------
-
2πV PP R FB f 0
CONVERTER
1 1
The load-line regulated converter behaves in a similar ------------------- ≤ f 0 < -----------------------------
-
Case 2: 2π LC 2πC ( ESR )
manner to a peak-current mode controller because the two
poles at the output-filter L-C resonant frequency split with V PP ( 2π ) 2 f 02 LC
R C = R FB -------------------------------------------- (EQ. 23)
the introduction of current information into the control loop. 0.75 V IN
The final location of these poles is determined by the system 0.75V IN
function, the gain of the current signal, and the value of the C C = ------------------------------------------------------------
-
( 2π ) 2 f 02 V PP R FB LC
compensation components, RC and CC.
Case 3: 1
Since the system poles and zero are effected by the values f 0 > ------------------------------
2πC ( ESR )
of the components that are meant to compensate them, the
2π f 0 V pp L
solution to the system equation becomes fairly complicated. R C = R FB -----------------------------------------
-
Fortunately there is a simple approximation that comes very 0.75 V IN ( ESR )
close to an optimal solution. Treating the system as though it 0.75V IN ( ESR ) C
were a voltage-mode regulator by compensating the L-C C C = ------------------------------------------------
-
2πV PP R FB f 0 L
poles and the ESR zero of the voltage-mode approximation
yields a solution that is always stable with very close to ideal In Equations 23, L is the per-channel filter inductance
transient performance. divided by the number of active channels; C is the sum total

15
 ISL6559

C2 24, RFB is selected arbitrarily. The remaining compensation

components are then selected according to Equations 24.

RC CC C ( ESR )
COMP R 1 = R FB -----------------------------------------
LC – C ( ESR )

FB LC – C ( ESR )
C 1 = -----------------------------------------
C1 R FB

ISL6559
IOUT
R1 RFB 0.75V IN
C 2 = ------------------------------------------------------------------
-
( 2π ) f 0 f HF LCR FB V PP
2
VDIFF

2
V PP  2π f 0 f HF LCR FB
 
R C = --------------------------------------------------------------------
-
FIGURE 13. COMPENSATION CIRCUIT FOR ISL6559 BASED  
CONVERTER WITHOUT LOAD-LINE 0.75 V IN 2πf HF LC – 1
REGULATION.

of all output capacitors; ESR is the equivalent-series

0.75V IN 2πf 
resistance of the bulk output-filter capacitance; and VPP is  HF LC – 1
C C = ------------------------------------------------------------------- (EQ. 24)
the peak-to-peak sawtooth signal amplitude as described in ( 2π ) 2 f 0 f HF LCR FB V PP
Figure 4 and Electrical Specifications.
In Equations 24, L is the per-channel filter inductance
Once selected, the compensation values in Equations 23 divided by the number of active channels; C is the sum total
assure a stable converter with reasonable transient of all output capacitors; ESR is the equivalent-series
performance. In most cases, transient performance can be
resistance of the bulk output-filter capacitance; and VPP is
improved by making adjustments to RC. Slowly increase the
the peak-to-peak sawtooth signal amplitude as described in
value of RC while observing the transient performance on an
Figure 4 and Electrical Specifications.
oscilloscope until no further improvement is noted. Normally,
CC will not need adjustment. Keep the value of CC from Output Filter Design
Equations 23 unless some performance issue is noted. The output inductors and the output capacitor bank together
The optional capacitor C2, is sometimes needed to bypass form a low-pass filter responsible for smoothing the pulsating
noise away from the PWM comparator (see Figure 12). Keep voltage at the phase nodes. The output filter also must
a position available for C2, and be prepared to install a high- provide the transient energy during the interval of time after
frequency capacitor of between 22pF and 150pF in case any the beginning of the transient until the regulator can
trailing edge jitter problem is noted. respond. Because it has a low bandwidth compared to the
COMPENSATION WITHOUT LOAD-LINE REGULATION switching frequency, the output filter necessarily limits the
system transient response leaving the output capacitor bank
The non load-line regulated converter is accurately modeled
to supply or sink load current while the current in the output
as a voltage-mode regulator with two poles at the L-C
inductors increases or decreases to meet the demand.
resonant frequency and a zero at the ESR frequency. A type
III controller, as shown in Figure 13, provides the necessary In high-speed converters, the output capacitor bank is
compensation. usually the most costly (and often the largest) part of the
circuit. Output filter design begins with minimizing the cost of
The first step is to choose the desired bandwidth, f0, of the
this part of the circuit. The critical load parameters in
compensated system. Choose a frequency high enough to
choosing the output capacitors are the maximum size of the
assure adequate transient performance but not higher than 1/3
load step, ∆I; the load-current slew rate, di/dt; and the
of the switching frequency. The type-III compensator has an
maximum allowable output-voltage deviation under transient
extra high-frequency pole, fHF. This pole can be used for added
loading, ∆VMAX. Capacitors are characterized according to
noise rejection or to assure adequate attenuation at the error-
their capacitance, ESR, and ESL (equivalent series
amplifier high-order pole and zero frequencies. A good general
inductance).
rule is to chose fHF = 10f0, but it can be higher if desired.
Choosing fHF to be lower than 10f0 can cause problems with At the beginning of the load transient, the output capacitors
too much phase shift below the system bandwidth. supply all of the transient current. The output voltage will
initially deviate by an amount approximated by the voltage
In the solutions to the compensation equations, there is a single
drop across the ESL. As the load current increases, the
degree of freedom. For the solutions presented in Equations
voltage drop across the ESR increases linearly until the load
current reaches its final value. The capacitors selected must
have sufficiently low ESL and ESR so that the total output-

16
 ISL6559

voltage deviation is less than the allowable maximum. Input Supply Voltage Selection
Neglecting the contribution of inductor current and regulator The VCC input of the ISL6559 can be connected to either a
response, the output voltage initially deviates by an amount +5V supply directly or through a current limiting resistor to a
di (EQ. 25) +12V supply. An integrated 5.8V shunt regulator maintains
∆V ≈ ( ESL ) ----- + ( ESR ) ∆I
dt the voltage on the VCC pin when a +12V supply is used. A
300Ω resistor is suggested for limiting the current into the
The filter capacitor must have sufficiently low ESL and ESR VCC pin to approximately 20mA.
so that ∆V < ∆VMAX.
Switching Frequency
Most capacitor solutions rely on a mixture of high-frequency There are a number of variables to consider when choosing
capacitors with relatively low capacitance in combination the switching frequency, as there are considerable effects on
with bulk capacitors having high capacitance but limited the upper-MOSFET loss calculation. These effects are
high-frequency performance. Minimizing the ESL of the outlined in MOSFETs, and they establish the upper limit for
high-frequency capacitors allows them to support the output the switching frequency. The lower limit is established by the
voltage as the current increases. Minimizing the ESR of the requirement for fast transient response and small output-
bulk capacitors allows them to supply the increased current voltage ripple as outlined in Output Filter Design. Choose
with less output voltage deviation. the lowest switching frequency that allows the regulator to
The ESR of the bulk capacitors also creates the majority of meet the transient-response requirements.
the output-voltage ripple. As the bulk capacitors sink and Switching frequency is determined by the selection of the
source the inductor ac ripple current (see Interleaving and frequency-setting resistor, RT (see the figure Typical
Equation 2), a voltage develops across the bulk-capacitor Application on page 3). Figure 15 and Equation 29 are
ESR equal to IC,PP (ESR). Thus, once the output capacitors provided to assist in the selecting the correct value for RT.
are selected, the maximum allowable ripple voltage,
1000
VPP(MAX), determines the lower limit on the inductance.
V – N V 
 IN OUT V OUT
L ≥ ( ESR ) ------------------------------------------------------------ (EQ. 26)
f S V IN V PP( MAX )

Since the capacitors are supplying a decreasing portion of

RT (kΩ)

the load current while the regulator recovers from the

100
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
∆VMAX. This places an upper limits on inductance.
2NCVO (EQ. 27)
L ≤ --------------------
- ∆V MAX – ∆I ( ESR )
( ∆I ) 2
10
10 100 1000 10000
( 1.25 ) NC SWITCHING FREQUENCY (kHz)
L ≤ -------------------------- ∆V MAX – ∆I ( ESR )  V IN – V O (EQ. 28)
( ∆I ) 2   FIGURE 14. RT VS SWITCHING FREQUENCY

Equation 28 gives the upper limit on L for the cases when

the trailing edge of the current transient causes a greater [11.09 – 1.13 log ( f S ) ] (EQ. 29)
R T = 10
output-voltage deviation than the leading edge. Equation 27
addresses the leading edge. Normally, the trailing edge Input Capacitor Selection
dictates the selection of L because duty cycles are usually The input capacitors are responsible for sourcing the ac
less than 50%. Nevertheless, both inequalities should be component of the input current flowing into the upper
evaluated, and L should be selected based on the lower of MOSFETs. Their RMS current capacity must be sufficient to
the two results. In each equation, L is the per-channel handle the ac component of the current drawn by the upper
inductance, C is the total output capacitance, and N is the
number of active channels.

17
 ISL6559

MOSFETs which is related to duty cycle and the number of and falling edge voltage [Link] result from the high
active phases. current slew rates produced by the upper MOSFETs turn on
0.3 and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
INPUT-CAPACITOR CURRENT (IRMS / IO)

board parasitics and maximize suppression.

0.3
IC,PP = 0 IC,PP = 0.5 IO
0.2
IC,PP = 0.25 IO IC,PP = 0.75 IO

INPUT-CAPACITOR CURRENT (IRMS / IO)

0.2

0.1
IC,PP = 0
IC,PP = 0.5 IO
IC,PP = 0.75 IO 0.1
0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VIN / VO)
FIGURE 15. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR 2-PHASE 0
CONVERTER 0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (VIN / VO)

For a two phase design, use Figure 15 to determine the FIGURE 17. NORMALIZED INPUT-CAPACITOR RMS
CURRENT VS DUTY CYCLE FOR 4-PHASE
input-capacitor RMS current requirement given the duty
CONVERTER
cycle, maximum sustained output current (IO), and the ratio
of the combined peak-to-peak inductor current (IC,PP) to IO. MULTIPHASE RMS IMPROVEMENT
Select a bulk capacitor with a ripple current rating which will
Figure 18 is provided as a reference to demonstrate the
minimize the total number of input capacitors required to
dramatic reductions in input-capacitor RMS current upon the
support the RMS current calculated. The voltage rating of implementation of the multiphase topology. For example,
the capacitors should also be at least 1.25 times greater compare the input rms current requirements of a two-phase
than the maximum input voltage. converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
Figures 16 and 17 provide the same input RMS current
output current of 40A, and a ratio of IC,PP to IO of 0.5. The
information for three and four phase designs respectively.
single phase converter would require 17.3 Arms current
Use the same approach to selecting the bulk capacitor type capacity while the two-phase converter would only require 10.9
and number as described above. Arms. The advantages become even more pronounced when
0.3 output current is increased and additional phases are added to
IC,PP = 0 IC,PP = 0.5 IO
keep the component cost down relative to the single phase
INPUT-CAPACITOR CURRENT (IRMS / IO)

IC,PP = 0.25 IO IC,PP = 0.75 IO

approach.
0.6

0.2
INPUT-CAPACITOR CURRENT (IRMS / IO)

0.4

0.1

0.2
IC,PP = 0
0
0 0.2 0.4 0.6 0.8 1.0 IC,PP = 0.5 IO
DUTY CYCLE (VIN / VO)
IC,PP = 0.75 IO
FIGURE 16. NORMALIZED INPUT-CAPACITOR RMS
0
CURRENT VS DUTY CYCLE FOR 3-PHASE 0 0.2 0.4 0.6 0.8 1.0
CONVERTER DUTY CYCLE (VIN / VO)
FIGURE 18. NORMALIZED INPUT-CAPACITOR RMS
Low capacitance, high-frequency ceramic capacitors are CURRENT VS DUTY CYCLE FOR SINGLE-PHASE
needed in addition to the bulk capacitors to suppress leading CONVERTER

18
 ISL6559

Layout Considerations The ISL6559 can be placed off to one side or centered
relative to the individual phase switching components.
The following multi-layer printed circuit board layout strategies
Routing of sense lines and PWM signals will guide final
minimize the impact of board parasitics on converter
placement. Critical small signal components to place close
performance. The following sections highlight some important
to the controller include the ISEN resistors, RT resistor,
practices which should not be overlooked during the layout
feedback resistor, and compensation components.
process.
Bypass capacitors for the ISL6559 and HIP660X driver bias
Component Placement
supplies must be placed next to their respective pins. Stray
Within the allotted implementation area, orient the switching trace parasitics will reduce their effectiveness.
components first. The switching components are the most
critical because they switch large amounts of energy and Plane Allocation and Routing
tend to generate large amounts of noise. How the switching Dedicate one solid layer, usually a middle layer, for a ground
components are placed should also take into account power plane. Make all critical component ground connections with
dissipation. Align the output inductors and MOSFETs such vias to this plane. Dedicate one additional layer for power
that space between the components is minimized while planes; breaking the plane up into smaller islands of
creating the PHASE plane. Place the Intersil HIP660X common voltage. Use the remaining layers for small signal
drivers as close as possible to the MOSFETs they control to wiring.
reduce the parasitics due to trace length between critical
Route PHASE planes of copper filled polygons on the top
driver input and output signals. If possible, duplicate the
and bottom once the switching component placement is set.
same placement of these components for each phase.
Size the trace width between the driver gate pins and the
Next, place the input and output capacitors. Position one MOFET gates to carry 1A of current. When routing
high-frequency ceramic input capacitor next to each upper components in the switching path, use short wide traces to
MOSFET drain. Place the bulk input capacitors as close to reduce the associated parasitics.
the upper MOSFET drains as dictated by the component
size and dimensions. Long distances between input
capacitors and MOSFET drains results in too much trace
inductance and a reduction in capacitor performance. Locate
the output capacitors between the inductors and the load,
while keeping them in close proximity around the
microprocessor socket.

19
 ISL6559

Small Outline Plastic Packages (SOIC)

N
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
H 0.25(0.010) M B M
AREA INCHES MILLIMETERS
E
SYMBOL MIN MAX MIN MAX NOTES
-B-
A 0.0926 0.1043 2.35 2.65 -

1 2 3
A1 0.0040 0.0118 0.10 0.30 -
L
B 0.013 0.0200 0.33 0.51 9
SEATING PLANE C 0.0091 0.0125 0.23 0.32 -
-A- D 0.6969 0.7125 17.70 18.10 3
D A h x 45o
E 0.2914 0.2992 7.40 7.60 4
-C- e 0.05 BSC 1.27 BSC -
α H 0.394 0.419 10.00 10.65 -
e A1
C h 0.01 0.029 0.25 0.75 5
B 0.10(0.004)
L 0.016 0.050 0.40 1.27 6
0.25(0.010) M C A M B S
N 28 28 7
α 0o 8o 0o 8o -
NOTES:
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.

20
 ISL6559

Quad Flat No-Lead Plastic Package (QFN) L32.5x5

Micro Lead Frame Plastic Package (MLFP) 32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
(COMPLIANT TO JEDEC MO-220VHHD-2 ISSUE C
MILLIMETERS
SYMBOL MIN NOMINAL MAX NOTES
A 0.80 0.90 1.00 -
A1 - - 0.05 -
A2 - - 1.00 9
A3 0.20 REF 9
b 0.18 0.23 0.30 5,8
D 5.00 BSC -
D1 4.75 BSC 9
D2 2.95 3.10 3.25 7,8
E 5.00 BSC -
E1 4.75 BSC 9
E2 2.95 3.10 3.25 7,8
e 0.50 BSC -
k 0.25 - - -
L 0.30 0.40 0.50 8
L1 - - 0.15 10
N 32 2
Nd 8 3
Ne 8 8 3
P - - 0.60 9
θ - - 12 9
Rev. 1 10/02

NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on each D and E.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land Pattern
Design efforts, see Intersil Technical Brief TB389.
9. Features and dimensions A2, A3, D1, E1, P & θ are present when
Anvil singulation method is used and not present for saw
singulation.
10. Depending on the method of lead termination at the edge of the
package, a maximum 0.15mm pull back (L1) maybe present. L
minus L1 to be equal to or greater than 0.3mm.

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Intersil Corporation’s quality certifications can be viewed at [Link]/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see [Link]

21