Scan assignment -2

Topics
• Different kind of delay present in design
• Cell awareness delay
• Small delay defect (SSD)
• How scan works to identify stuck at faults
• IDDQ lekage concept

Answers
Entrinsic delay is the internal delay of a logic cell (like an inverter,
AND gate, etc.) when no external load is connected to its output.

Gate delay or Cell delay or Propagation delay.

➤Time required in transmission of signal through the gate.
➤Signal transmission is not instantaneous and there is finite time gap between the
signal applied at the I/P of the gate and response of that input found at O/P of the
gate.

➤Propagation delay for rising and falling edge are not same.

➤The propagation delay (tp) is defined as the average of tpLH, tpHL

➤ tp= tpLH + tpHL

• tpLH = response time of the gate for a low to high output transition while
input switching from high to low.
• tpHL = response time of the gate for a high to low output transition while
input switching from low to high.
• The delay is usually calculated at 50% point of input-output switching.
• tr = Rise time = time it takes for the leading edge of a pulse to rise from its
minimum to its maximum [Link] time is typically measured from 10% to
90% _of the value.
• tf = fall time = time it takes for the falling edge of a pulse to rise from its
maximum to its minimum value. fall time is typically measured from 10% to
90% _of the value.

Interconnect delay
Extrinsic delay is the part of the total delay that occurs due to external factors outside
the logic cell, such as:
• Load capacitance (e.g., from fan-out)
• Interconnects/wires between cells
• Parasitics from routing(extra layout)
• Neighboring cell effects(net)
➢ A net delay is an extrinsic delay
➢ Net Delay = Wire Delay + Load Delay

1️⃣ Wire Delay (a.k.a. RC Delay)

 • This delay occurs within the metal wires (routes).
• It depends on:
o R = Resistance of the wire
o C = Capacitance of the wire
• Known as RC delay or Elmore delay.
• Increases with longer wire length, narrower width, and congestion.

Example: A long wire from one gate to another has resistance and picks up
capacitance from nearby wires → signal travels slower.

2️⃣ Load Delay (a.k.a. Fan-out Delay)

• Caused by the capacitance of the gates connected at the end of a net.
• More gates connected (fan-out) = higher load = longer delay.

Example: One driver gate is connected to 4 receiver gates → driver takes more time
to charge/discharge all input capacitors → delay increases.

3️⃣ Parasitic Delay (or Parasitic Effects)

• Parasitic means unintended resistance, capacitance, and sometimes inductance in
wires and cells.
• These effects are not part of the ideal logic design, but are introduced during
physical layout.
• Parasitics are extracted after routing (via RC extraction) and used for post-layout
timing analysis.

Path delay
What is Path Delay?
A path delay is the total time it takes for a signal to travel from one starting point (input) to
a destination (output) in a circuit, usually through combinational logic and interconnects.

Types of Path Delay:

1️⃣ Minimum Path Delay (Shortest Path)

• This is the fastest path a signal can take.
 • Used to check hold time violations.
• If it's too fast, data might get captured too early (before it's stable).

Used in: Hold time analysis

Formula:
mathematica
CopyEdit
Min Path Delay = Smallest (Cell Delay + Net Delay) across all paths

2️⃣ Maximum Path Delay (Critical Path)

• This is the slowest (longest) path from input to output.
• It determines the maximum clock frequency of the circuit.
• If this delay is too high, data won’t arrive in time → setup violation.

Used in: Setup time analysis

Formula:
mathematica
CopyEdit
Critical Path Delay = Largest (Cell Delay + Net Delay) across all paths

3️⃣ Pin-to-Pin Delay

• Delay between a specific input pin and a specific output pin of a logic gate or block.
• It's usually provided in timing libraries for synthesis and STA.

It includes:
• Intrinsic delay
• Load-dependent delay (extrinsic)
• Sometimes routing delay (post-layout)

Formula:
pgsql
CopyEdit
Pin-to-Pin Delay = Intrinsic Delay + Slope × Load Capacitance
 Overall Timing Path Delay Formula
For a complete timing path, like from a flip-flop to flip-flop, the total delay is:

Formula:
pgsql
CopyEdit
Path Delay = ∑ (Cell Delay + Net Delay) from startpoint to endpoint
Where:
• Cell Delay = delay of each gate in the path
• Net Delay = delay due to routing and loading between gates

Simple Example
Imagine a path:
FF1 → AND gate → OR gate → FF2
Let’s say:
• AND gate delay = 0.5 ns
• OR gate delay = 0.4 ns
• Net delay between FF1 and AND = 0.2 ns
• Net delay between AND and OR = 0.3 ns
• Net delay between OR and FF2 = 0.2 ns
Then:
Total Path Delay =
= 0.2 (net1) + 0.5 (AND) + 0.3 (net2) + 0.4 (OR) + 0.2 (net3)
= 1️.6 ns
 Clock latency/ delay

➤ Clock Latency / Clock Insertion Delay:

Defined as the amount of time taken by the clock signal in traveling from its source to the
sinks.

➤ Clock latency comprises of two components:

1. Clock Source Latency
2. Clock Network Latency

➤ Clock latency = Source latency + Network latency

➤ Clock Source Latency / Source Insertion Delay:

Defined as the time taken by the clock signal to reach the clock definition point from clock
source (PLL/Oscillator/some other source).
Also known as Source Insertion Delay.

➤ Clock Network Latency / Network Insertion Delay:

Defined as the time taken by the clock signal in traversing from clock definition point to the
sinks of the clock.
 Pre-CTS and Post-CTS Late

• Pre-CTS Latency refers to the delay in the clock signal before the Clock Tree Synthesis
stage. This can be caused by the initial routing of the clock signal, including any
delays in the source (like the clock buffer or the primary clock source). It measures
the time the clock takes to propagate before the clock tree is built.
• Post-CTS Latency refers to the delay in the clock signal after the Clock Tree Synthesis
is completed. This latency is associated with the delays incurred by the clock routing
after the clock tree has been synthesized and the clock signal is routed to the flip-
flops and other sequential elements in the design.
CTS is crucial because it directly impacts the clock skew (the difference in arrival time of the
clock signal at different flip-flops), which in turn affects the overall timing of the chip. The
goal is to minimize both pre-CTS and post-CTS latency to ensure that the clock reaches all
parts of the chip in a controlled and timely manner.
Note WHY CTS(clock tree synthesis)
Clock Tree Synthesis (CTS) is needed to ensure the clock signal is evenly distributed across
the entire chip, so all sequential elements (like flip-flops) receive the clock at the correct
time. It minimizes clock skew (differences in arrival time), ensuring synchronized operation
and preventing timing errors. Without CTS, the chip could malfunction due to improper
timing between components.
Jitter
Clock Jitter is defined as the deviation of a clock edge from its ideal position in time.
➤ Clock jitter is uncertainty in the clock edge.
➤ The cause may be noise, a fluctuating power source, or interference from nearby
circuits.
➤ Jitter can occur in both direction, positive and negetive.
➤ Can be modeled by adding uncertainty regions around the rising and falling edges
of the clock waveform.
➤ Clock jitter can be cycle-to-cycle, period jitter, long term jitter.
 Transistion delay
Signal Transition Time and Propagation Delay

➤ Transition time is the time taken to change the state of a signal.

➤ It refers to the time taken for the signal to switch from logic 0 to 1 or from 1 to 0.
➤ It is expressed as the rate of change of logic level during a transition.
➤ Also termed as Slew, and is measured in volt/ns.
➤ Rise time is defined as the time taken for a signal to rise from low threshold
voltage to high threshold voltage.
➤ Fall time is defined as the time taken for a signal to fall from high threshold
voltage to low threshold voltage.
➤ Both rise and fall times are measured in either absolute value or percentage.
➤ Low and high thresholds are fixed voltage levels, usually defined around the mid-
voltage level.
➤ Typical threshold voltages used are 1️0% and 90%, or alternatively 2️0% and 80%.

Difference and Relation Between Transition Time and Propagation Delay

➤ Transition Time (Rise/Fall Time): Time taken for a signal to move between
threshold levels (e.g., from 10% to 90% of Vmax). It shows the steepness of the signal
edge.
➤ Propagation Delay: Time taken for a signal change at the input to reflect at the
output, usually measured at the 50% voltage level.
➤ Relation: If the transition is slow (high slew), it delays the output's response,
increasing propagation delay.
➤ This connection is visible in the diagram, where slower input transition affects the
output timing.
Delays Under Timing Check

➤ 1️. Input Delay

• Input delay is the time taken by a signal to arrive at a register (flip-flop) from the
external input port.
• It is measured from the external clock edge to the time the signal becomes stable at
the input pin of the register.
• It is modeled as a delay between the input port and the register D-input.
• Input delay is important in setup and hold checks at the first register stage.

➤ 2️. Output Delay

• Output delay is the time taken for a signal to propagate from the output of a
register to the external output port.
• It is measured from the clock edge to the time the signal appears at the output port.
• This delay includes the clock-to-Q delay and logic delay in the path.
• Used for timing analysis of register-to-output paths.

➤ 3️. Setup Time

• Setup time is the minimum time before the active clock edge that the data must be
stable at the D-input of a flip-flop.
• If data changes during the setup window, the flip-flop may enter a metastable state
or capture wrong data.
• Setup time violation leads to functional errors or incorrect data capture.
➤ 4. Hold Time
• Hold time is the minimum time the data must remain stable after the clock
edge to ensure correct latching.
• If data changes too soon after the clock edge, it can result in hold violation
and incorrect latching.
• Setup and hold times together define the valid data window for capturing.

➤ 5. Clock-to-Q Delay
• Clock-to-Q delay is the time taken by a flip-flop to reflect a change at its Q
output after the active clock edge.
• It is an internal delay of the flip-flop and depends on load and technology.
• This delay is used as the starting point for data propagation in timing analysis.

➤ 6. Register-to-Register Delay
• This is the total time taken for data to travel from one flip-flop to another.
• It includes:
o Clock-to-Q delay of the launching register
o Combinational logic delay in the path
o Setup time requirement of the receiving register
• The clock period must be greater than or equal to this total delay to avoid
setup violations.
External Asynchronous Delay (General Explanation)
• External asynchronous delay happens when a signal comes from outside the
system and is not synchronized with the system clock.
Because its timing is uncertain and random, it can't be checked like regular
(synchronous) signals.
This delay can cause metastability issues, so we use special circuits like flip-
flop synchronizers to safely bring it into the clock domain.
It's not defined by fixed time but treated with uncertainty in timing analysis
tools.
 SDD (small delay defect)
In modern VLSI (Very Large Scale Integration) design, as technology nodes shrink to
nanometer scales, defects that cause minor delays in signal propagation have become
increasingly important. These defects are referred to as Small Delay Defects (SDDs).
Unlike gross defects that result in logical failures or stuck-at faults, SDDs cause only a
slight delay in the circuit’s operation, which might not immediately lead to a functional
failure under normal conditions. However, under high-speed or worst-case conditions,
these delays can accumulate or exceed timing margins, resulting in setup or hold time
violations and ultimately functional errors in the chip.
An SDD is typically caused by very subtle manufacturing imperfections—such as
marginal shorts, resistive opens, process variations, or contamination at vias or
interconnects. These small physical defects don’t always create permanent logic errors
but can delay the signal enough to create timing issues. Detecting such defects requires
more than just traditional stuck-at fault testing. It involves testing the circuit’s ability
to operate at its intended speed, which is why delay testing techniques such as
transition fault testing and path delay testing are used.
One of the major challenges in detecting SDDs is that their effect is not always visible
in functional tests or low-speed scan testing. They may only appear when the circuit is
switching fast and is close to the critical timing paths. Therefore, Advanced DFT (Design
for Test) methods such as launch-on-capture and launch-on-shift delay tests are
implemented to stimulate and capture delay faults under realistic operational speeds.
These methods help in identifying defects that affect the speed but not necessarily the
logic correctness.
To address SDDs effectively, statistical timing analysis, critical path identification, and
fault modeling are crucial during test pattern generation. Additionally, process-aware
testing and adaptive test strategies are increasingly being used, where the test
parameters are tuned based on process variations and environmental conditions. The
increasing significance of SDDs highlights the need for timing-aware design and test
methodologies to ensure chip reliability and yield.
In summary, Small Delay Defects are subtle but critical defects that impact the timing
behavior of VLSI circuits. They don't cause immediate logical errors but can degrade
system performance and cause failure under high-speed operations. Hence, their
detection and management are essential in today's high-frequency and low-margin
digital systems.