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8096 Opcode Table Overview

The document presents an opcode table for a processor, detailing various instructions categorized by their opcode values ranging from 0x00 to 0xFF. Each opcode is associated with different operations such as arithmetic, logical, and control instructions, along with addressing modes like register, immediate, indirect, and indexed. Additionally, it includes notes on specific instructions and their applicability to an extended instruction set.

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24 views1 page

8096 Opcode Table Overview

The document presents an opcode table for a processor, detailing various instructions categorized by their opcode values ranging from 0x00 to 0xFF. Each opcode is associated with different operations such as arithmetic, logical, and control instructions, along with addressing modes like register, immediate, indirect, and indexed. Additionally, it includes notes on specific instructions and their applicability to an extended instruction set.

Uploaded by

onre
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

8096 Opcode Table

x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF

0x SKIP CLR NOT NEG (XCH) DEC EXT INC SHR SHL SHRA (XCH) SHRL SHLL SHRAL NORML
(reg) (idx)

1x — CLRB NOTB NEGB (XCHB) DECB EXTB INCB SHRB SHLB SHRAB (XCHB) — — — —
(reg) (idx)
2x SJMP SJMP SJMP SJMP SJMP SJMP SJMP SJMP SCALL SCALL SCALL SCALL SCALL SCALL SCALL SCALL
3x JBC.0 JBC.1 JBC.2 JBC.3 JBC.4 JBC.5 JBC.6 JBC.7 JBS.0 JBS.1 JBS.2 JBS.3 JBS.4 JBS.5 JBS.6 JBS.7

4x AND3 AND3 AND3 AND3 ADD3 ADD3 ADD3 ADD3 SUB3 SUB3 SUB3 SUB3 MULU3 MULU3 MULU3 MULU3
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

5x ANDB3 ANDB3 ANDB3 ANDB3 ADDB3 ADDB3 ADDB3 ADDB3 SUBB3 SUBB3 SUBB3 SUBB3 MULUB3 MULUB3 MULUB3 MULUB3
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

6x AND2 AND2 AND2 AND2 ADD2 ADD2 ADD2 ADD2 SUB2 SUB2 SUB2 SUB2 MULU2 MULU2 MULU2 MULU2
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

7x ANDB2 ANDB2 ANDB2 ANDB2 ADDB2 ADDB2 ADDB2 ADDB2 SUBB2 SUBB2 SUBB2 SUBB2 MULUB2 MULUB2 MULUB2 MULUB2
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

8x OR OR OR OR XOR XOR XOR XOR CMP CMP CMP CMP DIVU DIVU DIVU DIVU
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

9x ORB ORB ORB ORB XORB XORB XORB XORB CMPB CMPB CMPB CMPB DIVUB DIVUB DIVUB DIVUB
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

Ax LD LD LD LD ADDC ADDC ADDC ADDC SUBC SUBC SUBC SUBC LDBZE LDBZE LDBZE LDBZE
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

Bx LDB LDB LDB LDB ADDCB ADDCB ADDCB ADDCB SUBCB SUBCB SUBCB SUBCB LDBSE LDBSE LDBSE LDBSE
reg imm ind idx reg imm ind idx reg imm ind idx reg imm ind idx

Cx ST (BMOV) ST ST STB (CMPL) STB STB PUSH PUSH PUSH PUSH POP (BMOVI) POP POP
reg ind idx reg ind idx reg imm ind idx reg ind idx
Dx JNST JNH JGT JNC JNVT JNV JGE JNE JST JH JLE JC JVT JV JLT JE
Ex DJNZ (DJNZW) (TIJMP) BR — — — LJMP — — — — — (DPTS) — LCALL
Fx RET — PUSHF POPF (PUSHA) (POPA) (IDLPD) TRAP CLRC SETC DI EI CLRVT NOP Note 1 RST

Notes:
1. 0xFE is signed prefix to DIVU/MULU ops.
2. reg denotes register direct addressing.
3. imm denotes immediate addressing.
4. ind denotes indirect addressing.
5. idx denotes indexed addressing.
6. Instructions in (...) are for 80196KB extended instruction set only (provided for reference).

c 2004, 2008 Neil Johnson


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